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rmileca |
Analysis & Synthesis report for Open_JTAG
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Wed Jun 02 16:01:07 2010
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Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Analysis & Synthesis Summary
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3. Analysis & Synthesis Settings
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4. Parallel Compilation
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5. Analysis & Synthesis Source Files Read
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6. Analysis & Synthesis Resource Usage Summary
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7. Analysis & Synthesis Resource Utilization by Entity
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8. Registers Removed During Synthesis
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9. General Register Statistics
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10. Inverted Register Statistics
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11. Multiplexer Restructuring Statistics (Restructuring Performed)
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12. Analysis & Synthesis Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2010 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+----------------------------------------------------------------------------+
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; Analysis & Synthesis Summary ;
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+-----------------------------+----------------------------------------------+
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; Analysis & Synthesis Status ; Successful - Wed Jun 02 16:01:07 2010 ;
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; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
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; Revision Name ; Open_JTAG ;
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; Top-level Entity Name ; Open_JTAG ;
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; Family ; MAX II ;
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; Total logic elements ; 257 ;
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; Total pins ; 29 ;
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; Total virtual pins ; 0 ;
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; UFM blocks ; 0 / 1 ( 0 % ) ;
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+-----------------------------+----------------------------------------------+
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+----------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Settings ;
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+----------------------------------------------------------------------------+--------------------+--------------------+
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; Option ; Setting ; Default Value ;
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+----------------------------------------------------------------------------+--------------------+--------------------+
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; Device ; EPM570T100C5 ; ;
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; Top-level entity name ; Open_JTAG ; Open_JTAG ;
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; Family name ; MAX II ; Stratix II ;
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; Use Generated Physical Constraints File ; Off ; ;
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; Use smart compilation ; Off ; Off ;
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; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
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; Enable compact report table ; Off ; Off ;
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; Restructure Multiplexers ; Auto ; Auto ;
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; Create Debugging Nodes for IP Cores ; Off ; Off ;
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; Preserve fewer node names ; On ; On ;
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; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
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; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
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; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
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; State Machine Processing ; Auto ; Auto ;
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; Safe State Machine ; Off ; Off ;
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; Extract Verilog State Machines ; On ; On ;
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; Extract VHDL State Machines ; On ; On ;
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; Ignore Verilog initial constructs ; Off ; Off ;
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; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
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; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
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; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
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; Parallel Synthesis ; On ; On ;
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; NOT Gate Push-Back ; On ; On ;
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; Power-Up Don't Care ; On ; On ;
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; Remove Redundant Logic Cells ; Off ; Off ;
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; Remove Duplicate Registers ; On ; On ;
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; Ignore CARRY Buffers ; Off ; Off ;
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; Ignore CASCADE Buffers ; Off ; Off ;
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; Ignore GLOBAL Buffers ; Off ; Off ;
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; Ignore ROW GLOBAL Buffers ; Off ; Off ;
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; Ignore LCELL Buffers ; Off ; Off ;
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; Ignore SOFT Buffers ; On ; On ;
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; Limit AHDL Integers to 32 Bits ; Off ; Off ;
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; Optimization Technique ; Balanced ; Balanced ;
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; Carry Chain Length ; 70 ; 70 ;
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; Auto Carry Chains ; On ; On ;
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; Auto Open-Drain Pins ; On ; On ;
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; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
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; Auto Shift Register Replacement ; Auto ; Auto ;
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; Auto Clock Enable Replacement ; On ; On ;
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; Allow Synchronous Control Signals ; On ; On ;
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; Force Use of Synchronous Clear Signals ; Off ; Off ;
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; Auto Resource Sharing ; Off ; Off ;
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; Use LogicLock Constraints during Resource Balancing ; On ; On ;
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; Ignore translate_off and synthesis_off directives ; Off ; Off ;
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; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
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; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
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; Synchronization Register Chain Length ; 2 ; 2 ;
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; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
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; HDL message level ; Level2 ; Level2 ;
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; Suppress Register Optimization Related Messages ; Off ; Off ;
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; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
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; Clock MUX Protection ; On ; On ;
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; Block Design Naming ; Auto ; Auto ;
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; Synthesis Effort ; Auto ; Auto ;
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; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
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; Analysis & Synthesis Message Level ; Medium ; Medium ;
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; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
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+----------------------------------------------------------------------------+--------------------+--------------------+
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Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
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+-------------------------------------+
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; Parallel Compilation ;
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+----------------------------+--------+
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; Processors ; Number ;
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+----------------------------+--------+
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; Number detected on machine ; 4 ;
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; Maximum allowed ; 1 ;
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+----------------------------+--------+
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+--------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Source Files Read ;
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+----------------------------------+-----------------+------------------------------------+--------------------------------------------+
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; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
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+----------------------------------+-----------------+------------------------------------+--------------------------------------------+
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; tap_sm.vhd ; yes ; User VHDL File ; C:/AlteraWorks/91/Open JTAG/tap_sm.vhd ;
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; clock_mux.vhd ; yes ; User VHDL File ; C:/AlteraWorks/91/Open JTAG/clock_mux.vhd ;
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; serializer.vhd ; yes ; User VHDL File ; C:/AlteraWorks/91/Open JTAG/serializer.vhd ;
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; Open_JTAG.bdf ; yes ; User Block Diagram/Schematic File ; C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf ;
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+----------------------------------+-----------------+------------------------------------+--------------------------------------------+
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+--------------------------------------------------------------------+
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; Analysis & Synthesis Resource Usage Summary ;
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+---------------------------------------------+----------------------+
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; Resource ; Usage ;
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+---------------------------------------------+----------------------+
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; Total logic elements ; 257 ;
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; -- Combinational with no register ; 169 ;
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; -- Register only ; 32 ;
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; -- Combinational with a register ; 56 ;
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; ; ;
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; Logic element usage by number of LUT inputs ; ;
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; -- 4 input functions ; 134 ;
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; -- 3 input functions ; 50 ;
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; -- 2 input functions ; 30 ;
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; -- 1 input functions ; 11 ;
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; -- 0 input functions ; 0 ;
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; ; ;
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; Logic elements by mode ; ;
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; -- normal mode ; 249 ;
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; -- arithmetic mode ; 8 ;
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; -- qfbk mode ; 0 ;
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; -- register cascade mode ; 0 ;
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; -- synchronous clear/load mode ; 3 ;
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; -- asynchronous clear/load mode ; 1 ;
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; ; ;
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; Total registers ; 88 ;
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; Total logic cells in carry chains ; 10 ;
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; I/O pins ; 29 ;
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; Maximum fan-out node ; clock_mux:inst1|wcks ;
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; Maximum fan-out ; 75 ;
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; Total fan-out ; 973 ;
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; Average fan-out ; 3.40 ;
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+---------------------------------------------+----------------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Resource Utilization by Entity ;
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+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+
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; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
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+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+
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; |Open_JTAG ; 257 (2) ; 88 ; 0 ; 29 ; 0 ; 169 (2) ; 32 (0) ; 56 (0) ; 10 (0) ; 0 (0) ; |Open_JTAG ; work ;
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; |clock_mux:inst1| ; 21 (21) ; 14 ; 0 ; 0 ; 0 ; 7 (7) ; 7 (7) ; 7 (7) ; 6 (6) ; 0 (0) ; |Open_JTAG|clock_mux:inst1 ; work ;
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; |serializer:inst2| ; 172 (172) ; 58 ; 0 ; 0 ; 0 ; 114 (114) ; 15 (15) ; 43 (43) ; 4 (4) ; 0 (0) ; |Open_JTAG|serializer:inst2 ; work ;
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; |tap_sm:inst| ; 62 (62) ; 16 ; 0 ; 0 ; 0 ; 46 (46) ; 10 (10) ; 6 (6) ; 0 (0) ; 0 (0) ; |Open_JTAG|tap_sm:inst ; work ;
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+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+
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Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
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+--------------------------------------------------------------------------------+
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; Registers Removed During Synthesis ;
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+---------------------------------------+----------------------------------------+
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; Register name ; Reason for Removal ;
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+---------------------------------------+----------------------------------------+
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; clock_mux:inst1|cclk[0] ; Merged with clock_mux:inst1|count[0] ;
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; serializer:inst2|state[3] ; Stuck at GND due to stuck port data_in ;
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; serializer:inst2|state[2] ; Merged with serializer:inst2|state[1] ;
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; serializer:inst2|state[1] ; Stuck at GND due to stuck port data_in ;
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; Total Number of Removed Registers = 4 ; ;
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+---------------------------------------+----------------------------------------+
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+------------------------------------------------------+
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; General Register Statistics ;
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+----------------------------------------------+-------+
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; Statistic ; Value ;
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+----------------------------------------------+-------+
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; Total registers ; 88 ;
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; Number of registers using Synchronous Clear ; 0 ;
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; Number of registers using Synchronous Load ; 3 ;
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; Number of registers using Asynchronous Clear ; 0 ;
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; Number of registers using Asynchronous Load ; 1 ;
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; Number of registers using Clock Enable ; 57 ;
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; Number of registers using Preset ; 0 ;
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+----------------------------------------------+-------+
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+--------------------------------------------------+
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; Inverted Register Statistics ;
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+----------------------------------------+---------+
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; Inverted Register ; Fan out ;
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+----------------------------------------+---------+
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; serializer:inst2|wr ; 2 ;
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; serializer:inst2|rd ; 2 ;
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; serializer:inst2|trst ; 2 ;
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; serializer:inst2|dir ; 19 ;
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; Total number of inverted registers = 4 ; ;
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+----------------------------------------+---------+
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+--------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Multiplexer Restructuring Statistics (Restructuring Performed) ;
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+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+
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; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
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+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+
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; 4:1 ; 4 bits ; 8 LEs ; 0 LEs ; 8 LEs ; Yes ; |Open_JTAG|serializer:inst2|new_state[2] ;
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; 4:1 ; 3 bits ; 6 LEs ; 0 LEs ; 6 LEs ; Yes ; |Open_JTAG|serializer:inst2|cks[2] ;
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; 5:1 ; 8 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |Open_JTAG|serializer:inst2|shift[0] ;
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; 5:1 ; 4 bits ; 12 LEs ; 0 LEs ; 12 LEs ; Yes ; |Open_JTAG|serializer:inst2|state[2] ;
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; 19:1 ; 2 bits ; 24 LEs ; 4 LEs ; 20 LEs ; Yes ; |Open_JTAG|serializer:inst2|rbyte[6] ;
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; 20:1 ; 4 bits ; 52 LEs ; 8 LEs ; 44 LEs ; Yes ; |Open_JTAG|serializer:inst2|rbyte[3] ;
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| 248 |
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; 37:1 ; 2 bits ; 48 LEs ; 18 LEs ; 30 LEs ; Yes ; |Open_JTAG|serializer:inst2|ssm[1] ;
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| 249 |
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; 21:1 ; 2 bits ; 28 LEs ; 4 LEs ; 24 LEs ; Yes ; |Open_JTAG|serializer:inst2|count[2] ;
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; 40:1 ; 2 bits ; 52 LEs ; 22 LEs ; 30 LEs ; Yes ; |Open_JTAG|serializer:inst2|ssm[2] ;
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; 1:1 ; 8 bits ; 0 LEs ; 0 LEs ; 0 LEs ; Yes ; |Open_JTAG|serializer:inst2|db[0]~reg0 ;
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; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |Open_JTAG|serializer:inst2|Add0 ;
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+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+
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+-------------------------------+
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; Analysis & Synthesis Messages ;
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+-------------------------------+
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Info: *******************************************************************
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Info: Running Quartus II Analysis & Synthesis
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Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
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Info: Processing started: Wed Jun 02 16:01:02 2010
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Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Open_JTAG -c Open_JTAG
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Info: Found 2 design units, including 1 entities, in source file tap_sm.vhd
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Info: Found design unit 1: tap_sm-rtl
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Info: Found entity 1: tap_sm
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Info: Found 2 design units, including 1 entities, in source file clock_mux.vhd
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Info: Found design unit 1: clock_mux-rtl
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Info: Found entity 1: clock_mux
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Info: Found 2 design units, including 1 entities, in source file serializer.vhd
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Info: Found design unit 1: serializer-rtl
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Info: Found entity 1: serializer
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Info: Found 1 design units, including 1 entities, in source file open_jtag.bdf
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Info: Found entity 1: Open_JTAG
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Info: Elaborating entity "Open_JTAG" for the top level hierarchy
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Info: Elaborating entity "tap_sm" for hierarchy "tap_sm:inst"
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Info: Elaborating entity "clock_mux" for hierarchy "clock_mux:inst1"
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Info: Elaborating entity "serializer" for hierarchy "serializer:inst2"
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Warning (10540): VHDL Signal Declaration warning at serializer.vhd(25): used explicit default value for signal "siwu" because signal was never assigned a value
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Warning: Design contains 1 input pin(s) that do not drive logic
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Warning (15610): No output dependent on input pin "rst"
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Info: Implemented 286 device resources after synthesis - the final resource count might be different
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Info: Implemented 5 input pins
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Info: Implemented 16 output pins
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Info: Implemented 8 bidirectional pins
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Info: Implemented 257 logic cells
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Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
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Info: Peak virtual memory: 187 megabytes
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Info: Processing ended: Wed Jun 02 16:01:07 2010
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Info: Elapsed time: 00:00:05
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Info: Total CPU time (on all processors): 00:00:04
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| 292 |
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| 293 |
|
|
|
