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[/] [openmsp430/] [trunk/] [ChangeLog_core.txt] - Blame information for rev 180

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Line No. Rev Author Line
1 177 olivier.gi
2013-01-30 [r175]
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3
        * Update hardware breakpoint unit with the followings: - fixed
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          hardware breakpoint bug with CALL instructions. - modified data
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          read watchpoint behavior to also trigger with read/modify/write
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          instructions. - removed unused ports.
7
 
8
2013-01-30 [r174]
9
 
10
        * Cleanup dmem_wr generation logic. Important note: this is not a
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          bug fix, only beautification.
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13 160 olivier.gi
2012-10-15 [r154]
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15
        * The serial debug interface now supports the I2C protocol (in
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          addition to the UART)
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18 152 olivier.gi
2012-07-22 [r151]
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20
        * Add possibility to configure custom Program, Data and Peripheral
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          memory sizes.
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23 150 olivier.gi
2012-07-19 [r149]
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25
        * Update simulation regression result parser. Fixed failing SFR
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          test (due to newer MSPGCC version). Implement request
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          http://opencores.org/bug,view,2171 (burst accesses through the
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          serial debug interface)
29
 
30 146 olivier.gi
2012-05-30 [r145]
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32
        * Add Dhrystone and CoreMark benchmarks to the simulation
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          environment.
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35 144 olivier.gi
2012-05-09 [r142]
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37
        * Beautify the linker script examples.
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39
2012-05-05 [r141]
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        * Update verification environment to support MSPGCC Uniarch (based
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          on GCC 4.5 and later)
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44 140 olivier.gi
2012-04-23 [r139]
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        * Add some SVN ignore patterns
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48
2012-04-23 [r138]
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        * Update simulation scripts to support Cygwin out of the box for
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          Windows users.
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53 137 olivier.gi
2012-03-22 [r134]
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55
        * Add full ASIC support (low-power modes, DFT, ...). Improved
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          serial debug interface reliability.
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58
2012-03-09 [r132]
59
 
60
        * Update FPGA examples with the POP.B bug fix
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62 131 olivier.gi
2012-03-01 [r130]
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64
        * Fixed POP.B bug (see Bugtracker
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          http://opencores.org/bug,assign,2137 )
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67 129 olivier.gi
2011-12-16 [r128]
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69
        * Fixed CALL x(SR) bug (see Bugtracker
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          http://opencores.org/bug,view,2111 )
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72 123 olivier.gi
2011-10-05 [r122]
73
 
74
        * Add coverage report generation (NCVERILOG only) Add support for
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          the ISIM Xilinx simulator.
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77 118 olivier.gi
2011-06-23 [r117]
78
 
79
        * To facilitate commercial adoption of the openMSP430, the core has
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          moved to a modified BSD license.
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82 116 olivier.gi
2011-05-29 [r115]
83
 
84
        * Add linker script example.
85
 
86 113 olivier.gi
2011-05-21 [r112]
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88
        * Modified comment.
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90
2011-05-20 [r111]
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92
        * Re-organized the "openMSP430_defines.v" file. Re-defined the
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          CPU_ID register of the debug interface (in particular to support
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          custom user versioning). Added RTL configuration possibility to
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          expand the peripheral address space from 512B (0x0000 to 0x0200)
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          to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr
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          bus width goes from 8 to 14 bits and the peripherals address
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          decoders have been updated accordingly.
99
 
100
2011-03-25 [r106]
101
 
102
        * Separated the Timer A defines from the openMSP430 ones. Added the
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          "dbg_en" port in order to allow a separate reset of the debug
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          interface. Added the "core_en" port (when cleared, the CPU will
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          stop execution, the dbg_freeze signal will be set and the aclk &
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          smclk will be stopped). Renamed "per_wen" to "per_we" to prevent
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          confusion with active low signals. Removed to missing unused
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          flops when the DBG_EN is not defined (thanks to Mihai
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          contribution).
110
 
111
2011-03-10 [r105]
112
 
113
        * Removed dummy memory read access for the MOV/PUSH/CALL/RETI
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          instructions. These were not problematic but this is simply
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          cleaner that way.
116
 
117
2011-03-05 [r103]
118
 
119
        * Removed the timescale from all RTL files. Added possibility to
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          exclude the "includes" statements from the RTL.
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122
2011-03-04 [r102]
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124
        * Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955
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          ). The following PUSH instructions are now working as expected: -
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          indexed mode: PUSH x(R1) - indirect register mode: PUSH @R1 -
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          indirect autoincrement: PUSH @R1+
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129
2011-03-04 [r101]
130
 
131
        * Cosmetic change in order to prevent an X propagation whenever
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          executing a byte instruction with an uninitialized memory
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          location as source.
134
 
135
2011-02-28 [r99]
136
 
137
        * Small fix for CVER simulator support.
138
 
139
2011-02-28 [r98]
140
 
141
        * Added support for VCS verilog simulator. VPD and TRN waveforms
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          can now be generated.
143
 
144
2011-02-24 [r95]
145
 
146
        * Update some test patterns for the additional simulator supports.
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148
2011-02-24 [r94]
149
 
150
        * Thanks to Mihai-Costin Manolescu's contribution, the simulation
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          scripts now support the following simulators: - Icarus Verilog -
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          Cver - Verilog-XL - NCVerilog - Modelsim
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154
2011-02-20 [r91]
155
 
156
        * Fixed bug when an IRQ arrives while CPU is halted through the
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          serial debug interface. This bug is CRITICAL for people using
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          working with interrupts and the Serial Debug Interface.
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160
2011-01-28 [r86]
161
 
162
        * Update serial debug interface test patterns to make them work
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          with all program memory configurations.
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165
2011-01-28 [r85]
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167
        * Diverse RTL cosmetic updates.
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169
2011-01-23 [r84]
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        * Update SRAM model in the core testbench to prevent the IEEE
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          warning when running simulations. Update watchdog to fix NMI
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          synchronisation problem. Add synchronizers for the PUC signal in
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          the debug interface.
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176
2010-12-05 [r80]
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178
        * Create initial version of the Actel FPGA implementation example.
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180
2010-11-23 [r79]
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182
        * Update the GPIO peripheral to fix a potential synchronization
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          issue.
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185
2010-11-18 [r76]
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187
        * Add possibility to simulate C code within the "core" environment.
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189
2010-08-28 [r74]
190
 
191
        * Update serial debug interface to support memories with a size
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          which is not a power of 2. Update the software tools accordingly.
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194
2010-08-03 [r73]
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196
        * Update all bash scripts headers with "#!/bin/bash" instead of
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          "#!/bin/sh". This will prevent compatibility problems in systems
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          where bash isn't the default shell.
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200
2010-08-01 [r72]
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202
        * Expand configurability options of the program and data memory
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          sizes.
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205
2010-03-07 [r67-68]
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207
        * Update synthesis scripts with the hardware multiplier support.
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209
        * Added 16x16 Hardware Multiplier.
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211
2010-03-07 [r66]
212
 
213
        * The peripheral templates are now under BSD license. Developers of
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          new peripherals based on these templates won't have to disclose
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          their code.
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217
2010-02-24 [r65]
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219
        * Add possibility to disable waveform dumping by setting the
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          OMSP_NODUMP environment variable to 1.
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222
2010-02-14 [r64]
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224
        * Add Actel synthesis environment for size and speed analysis.
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226
2010-02-14 [r63]
227
 
228
        * Add Altera synthesis environment for size and speed analysis.
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230
2010-02-14 [r62]
231
 
232
        * Add Xilinx synthesis environment for size&speed analysis.
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234
2010-02-03 [r60]
235
 
236
        * Cleanup of the PC (R0) generation logic. Formal equivalence was
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          shown between the new and old code with Synopsys' Formality (to
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          make sure that nothing has been broken :-P ).
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240
2010-02-01 [r58]
241
 
242
        * Update the debug hardware breakpoint verification patterns to
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          reflect the latest design updates.
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245
2010-02-01 [r57]
246
 
247
        * Update design to exclude the range mode from the debug hardware
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          breakpoint units. As this feature is not used by GDB, it has been
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          disabled in order to improve the timings and save a bit of
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          area/utilisation. Note that if required, this feature can be
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          re-enabled through the `HWBRK_RANGE define located in the
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          "openMSP430_defines.v" file.
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254
2010-01-28 [r56]
255
 
256
        * Update Design Compiler Synthesis scripts.
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258
2010-01-27 [r55]
259
 
260
        * Add a "sandbox" test pattern to play around with the simulation
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          :-P
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263
2010-01-27 [r54]
264
 
265
        * Update FPGA projects with the combinatorial loop fixed.
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267
2010-01-27 [r53]
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269
        * Fixed the following combinatorial timing loop: 1- irq_detect
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          (omsp_frontend) 2- decode (omsp_frontend) 3- dbg_swbrk (omsp_dbg)
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          4- halt_flag_set (omsp_dbg) 6- dbg_halt_cmd (omsp_dbg) 7-
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          irq_detect (omsp_frontend) Without this fix, problem could occur
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          whenever an IRQ request arrives during a software breakpoint
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          instruction fetch.
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276
2009-12-29 [r34]
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278
        * To avoid potential conflicts with other Verilog modules in bigger
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          projects, the openMSP430 sub-modules have all been renamed with
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          the "omsp_" prefix.
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282
2009-12-29 [r33]
283
 
284
        * In order to avoid confusion, the following changes have been
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          implemented to the Verilog code: - renamed the "rom_*" ports and
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          defines to "pmem_*" (program memory). - renamed the "ram_*" ports
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          and defines to "dmem_*" (data memory). In addition, in order to
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          prevent potential conflicts with the Verilog defines of other
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          IPs, a Verilog undefine file has been created.
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291
2009-08-30 [r23]
292
 
293
        * Renamed the "openMSP430.inc" file to "openMSP430_defines.v" &
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          added the "timescale.v" file. In order to follow the same
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          structure as other OpenCores projects, the timescale and the
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          defines are now included from within the Verilog files (using the
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          `include construct).
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299
2009-08-04 [r19]
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301
        * added SVN property for keywords
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303
2009-08-04 [r18]
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305
        * Updated headers with SVN info
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307
2009-08-04 [r17]
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309
        * Updated header with SVN info
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311
2009-07-13 [r6]
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        * Some more SVN ignore properties...
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2009-06-30 [r2]
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        * Upload complete openMSP430 project to the SVN repository
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