OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [dbg_uart_tasks.v] - Blame information for rev 17

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi 
//----------------------------------------------------------------------------
2 
// Copyright (C) 2001 Authors
3 
//
4 
// This source file may be used and distributed without restriction provided
5 
// that this copyright statement is not removed from the file and that any
6 
// derivative work contains the original copyright notice and the associated
7 
// disclaimer.
8 
//
9 
// This source file is free software; you can redistribute it and/or modify
10 
// it under the terms of the GNU Lesser General Public License as published
11 
// by the Free Software Foundation; either version 2.1 of the License, or
12 
// (at your option) any later version.
13 
//
14 
// This source is distributed in the hope that it will be useful, but WITHOUT
15 
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
17 
// License for more details.
18 
//
19 
// You should have received a copy of the GNU Lesser General Public License
20 
// along with this source; if not, write to the Free Software Foundation,
21 
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
22 
//
23 
//----------------------------------------------------------------------------
24 
//
25 
// *File Name: dbg_uart_tasks.v
26 
//
27 
// *Module Description:
28 
//                      openMSP430 debug interface UART tasks
29 
//
30 
// *Author(s):
31 
//              - Olivier Girard,    olgirard@gmail.com
32 
//
33 
//----------------------------------------------------------------------------
34 17 olivier.gi 
// $Rev: 17 $
35 
// $LastChangedBy: olivier.girard $
36 
// $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
37 
//----------------------------------------------------------------------------
38 2 olivier.gi 
 
39 
// Register B/W and addresses
40 
parameter           CPU_ID_LO    =  (8'h00 | 8'h00);
41 
parameter           CPU_ID_HI    =  (8'h00 | 8'h01);
42 
parameter           CPU_CTL      =  (8'h40 | 8'h02);
43 
parameter           CPU_STAT     =  (8'h40 | 8'h03);
44 
parameter           MEM_CTL      =  (8'h40 | 8'h04);
45 
parameter           MEM_ADDR     =  (8'h00 | 8'h05);
46 
parameter           MEM_DATA     =  (8'h00 | 8'h06);
47 
parameter           MEM_CNT      =  (8'h00 | 8'h07);
48 
parameter           BRK0_CTL     =  (8'h40 | 8'h08);
49 
parameter           BRK0_STAT    =  (8'h40 | 8'h09);
50 
parameter           BRK0_ADDR0   =  (8'h00 | 8'h0A);
51 
parameter           BRK0_ADDR1   =  (8'h00 | 8'h0B);
52 
parameter           BRK1_CTL     =  (8'h40 | 8'h0C);
53 
parameter           BRK1_STAT    =  (8'h40 | 8'h0D);
54 
parameter           BRK1_ADDR0   =  (8'h00 | 8'h0E);
55 
parameter           BRK1_ADDR1   =  (8'h00 | 8'h0F);
56 
parameter           BRK2_CTL     =  (8'h40 | 8'h10);
57 
parameter           BRK2_STAT    =  (8'h40 | 8'h11);
58 
parameter           BRK2_ADDR0   =  (8'h00 | 8'h12);
59 
parameter           BRK2_ADDR1   =  (8'h00 | 8'h13);
60 
parameter           BRK3_CTL     =  (8'h40 | 8'h14);
61 
parameter           BRK3_STAT    =  (8'h40 | 8'h15);
62 
parameter           BRK3_ADDR0   =  (8'h00 | 8'h16);
63 
parameter           BRK3_ADDR1   =  (8'h00 | 8'h17);
64 
 
65 
// Read / Write commands
66 
parameter           DBG_WR       =   8'h80;
67 
parameter           DBG_RD       =   8'h00;
68 
 
69 
// Synchronization value
70 
parameter           DBG_SYNC     =   8'h80;
71 
 
72 
 
73 
//----------------------------------------------------------------------------
74 
// UART COMMUNICATION DATA RATE CONFIGURATION
75 
//----------------------------------------------------------------------------
76 
// If the auto synchronization mode is set, then the communication speed
77 
// is configured by the testbench.
78 
// If not, the values from the openMSP430.inc file are taken over.
79 
`ifdef DBG_UART_AUTO_SYNC
80 
parameter UART_BAUD = 4000000;
81 
parameter UART_CNT  = ((20000000/UART_BAUD)-1);
82 
`else
83 
parameter UART_CNT  = `DBG_UART_CNT;
84 
`endif
85 
 
86 
//----------------------------------------------------------------------------
87 
// Receive UART frame from CPU Debug interface (8N1)
88 
//----------------------------------------------------------------------------
89 
task dbg_uart_rx;
90 
      output [7:0] dbg_rxbuf;
91 
 
92 
      reg [7:0] dbg_rxbuf;
93 
      reg [7:0] rxbuf;
94 
      integer   rxcnt;
95 
      begin
96 
         @(negedge dbg_uart_txd);
97 
         dbg_rxbuf = 0;
98 
         rxbuf = 0;
99 
         repeat((UART_CNT+1)/2) @(posedge mclk);
100 
         for (rxcnt = 0; rxcnt < 8; rxcnt = rxcnt + 1)
101 
           begin
102 
              repeat(UART_CNT+1) @(posedge mclk);
103 
              rxbuf = {dbg_uart_txd, rxbuf[7:1]};
104 
           end
105 
         dbg_rxbuf = rxbuf;
106 
      end
107 
endtask
108 
 
109 
task dbg_uart_rx16;
110 
 
111 
      reg [7:0] rxbuf_lo;
112 
      reg [7:0] rxbuf_hi;
113 
      begin
114 
         rxbuf_lo = 8'h00;
115 
         rxbuf_hi = 8'h00;
116 
         dbg_uart_rx(rxbuf_lo);
117 
         dbg_uart_rx(rxbuf_hi);
118 
         dbg_uart_buf = {rxbuf_hi, rxbuf_lo};
119 
      end
120 
endtask
121 
 
122 
task dbg_uart_rx8;
123 
 
124 
      reg [7:0] rxbuf;
125 
      begin
126 
         rxbuf = 8'h00;
127 
         dbg_uart_rx(rxbuf);
128 
         dbg_uart_buf = {8'h00, rxbuf};
129 
      end
130 
endtask
131 
 
132 
//----------------------------------------------------------------------------
133 
// Transmit UART frame to CPU Debug interface (8N1)
134 
//----------------------------------------------------------------------------
135 
task dbg_uart_tx;
136 
      input  [7:0] txbuf;
137 
 
138 
      reg [9:0] txbuf_full;
139 
      integer   txcnt;
140 
      begin
141 
         dbg_uart_rxd = 1'b1;
142 
         txbuf_full   = {1'b1, txbuf, 1'b0};
143 
         for (txcnt = 0; txcnt < 10; txcnt = txcnt + 1)
144 
           begin
145 
              repeat(UART_CNT+1) @(posedge mclk);
146 
              dbg_uart_rxd =  txbuf_full[txcnt];
147 
           end
148 
      end
149 
endtask
150 
 
151 
task dbg_uart_tx16;
152 
      input  [15:0] txbuf;
153 
 
154 
      begin
155 
         dbg_uart_tx(txbuf[7:0]);
156 
         dbg_uart_tx(txbuf[15:8]);
157 
      end
158 
endtask
159 
 
160 
 
161 
//----------------------------------------------------------------------------
162 
// Write to Debug register
163 
//----------------------------------------------------------------------------
164 
task dbg_uart_wr;
165 
      input  [7:0] dbg_reg;
166 
      input [15:0] dbg_data;
167 
 
168 
      begin
169 
         dbg_uart_tx(DBG_WR | dbg_reg);
170 
         dbg_uart_tx(dbg_data[7:0]);
171 
         if (~dbg_reg[6])
172 
           dbg_uart_tx(dbg_data[15:8]);
173 
      end
174 
endtask
175 
 
176 
 
177 
//----------------------------------------------------------------------------
178 
// Read Debug register
179 
//----------------------------------------------------------------------------
180 
task dbg_uart_rd;
181 
      input  [7:0] dbg_reg;
182 
 
183 
      reg [7:0] rxbuf_lo;
184 
      reg [7:0] rxbuf_hi;
185 
      begin
186 
         rxbuf_lo = 8'h00;
187 
         rxbuf_hi = 8'h00;
188 
         dbg_uart_tx(DBG_RD | dbg_reg);
189 
         dbg_uart_rx(rxbuf_lo);
190 
         if (~dbg_reg[6])
191 
           dbg_uart_rx(rxbuf_hi);
192 
 
193 
         dbg_uart_buf = {rxbuf_hi, rxbuf_lo};
194 
      end
195 
endtask

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.