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[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [dbg_uart_tasks.v] - Blame information for rev 29

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1 2 olivier.gi 
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: dbg_uart_tasks.v
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//
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// *Module Description:
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//                      openMSP430 debug interface UART tasks
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
34 17 olivier.gi 
// $Rev: 17 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
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//----------------------------------------------------------------------------
38 2 olivier.gi 
 
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// Register B/W and addresses
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parameter           CPU_ID_LO    =  (8'h00 | 8'h00);
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parameter           CPU_ID_HI    =  (8'h00 | 8'h01);
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parameter           CPU_CTL      =  (8'h40 | 8'h02);
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parameter           CPU_STAT     =  (8'h40 | 8'h03);
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parameter           MEM_CTL      =  (8'h40 | 8'h04);
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parameter           MEM_ADDR     =  (8'h00 | 8'h05);
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parameter           MEM_DATA     =  (8'h00 | 8'h06);
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parameter           MEM_CNT      =  (8'h00 | 8'h07);
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parameter           BRK0_CTL     =  (8'h40 | 8'h08);
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parameter           BRK0_STAT    =  (8'h40 | 8'h09);
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parameter           BRK0_ADDR0   =  (8'h00 | 8'h0A);
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parameter           BRK0_ADDR1   =  (8'h00 | 8'h0B);
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parameter           BRK1_CTL     =  (8'h40 | 8'h0C);
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parameter           BRK1_STAT    =  (8'h40 | 8'h0D);
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parameter           BRK1_ADDR0   =  (8'h00 | 8'h0E);
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parameter           BRK1_ADDR1   =  (8'h00 | 8'h0F);
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parameter           BRK2_CTL     =  (8'h40 | 8'h10);
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parameter           BRK2_STAT    =  (8'h40 | 8'h11);
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parameter           BRK2_ADDR0   =  (8'h00 | 8'h12);
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parameter           BRK2_ADDR1   =  (8'h00 | 8'h13);
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parameter           BRK3_CTL     =  (8'h40 | 8'h14);
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parameter           BRK3_STAT    =  (8'h40 | 8'h15);
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parameter           BRK3_ADDR0   =  (8'h00 | 8'h16);
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parameter           BRK3_ADDR1   =  (8'h00 | 8'h17);
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// Read / Write commands
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parameter           DBG_WR       =   8'h80;
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parameter           DBG_RD       =   8'h00;
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// Synchronization value
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parameter           DBG_SYNC     =   8'h80;
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//----------------------------------------------------------------------------
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// UART COMMUNICATION DATA RATE CONFIGURATION
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//----------------------------------------------------------------------------
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// If the auto synchronization mode is set, then the communication speed
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// is configured by the testbench.
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// If not, the values from the openMSP430.inc file are taken over.
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`ifdef DBG_UART_AUTO_SYNC
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parameter UART_BAUD = 4000000;
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parameter UART_CNT  = ((20000000/UART_BAUD)-1);
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`else
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parameter UART_CNT  = `DBG_UART_CNT;
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`endif
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//----------------------------------------------------------------------------
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// Receive UART frame from CPU Debug interface (8N1)
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//----------------------------------------------------------------------------
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task dbg_uart_rx;
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      output [7:0] dbg_rxbuf;
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      reg [7:0] dbg_rxbuf;
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      reg [7:0] rxbuf;
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      integer   rxcnt;
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      begin
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         @(negedge dbg_uart_txd);
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         dbg_rxbuf = 0;
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         rxbuf = 0;
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         repeat((UART_CNT+1)/2) @(posedge mclk);
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         for (rxcnt = 0; rxcnt < 8; rxcnt = rxcnt + 1)
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           begin
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              repeat(UART_CNT+1) @(posedge mclk);
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              rxbuf = {dbg_uart_txd, rxbuf[7:1]};
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           end
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         dbg_rxbuf = rxbuf;
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      end
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endtask
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task dbg_uart_rx16;
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      reg [7:0] rxbuf_lo;
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      reg [7:0] rxbuf_hi;
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      begin
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         rxbuf_lo = 8'h00;
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         rxbuf_hi = 8'h00;
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         dbg_uart_rx(rxbuf_lo);
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         dbg_uart_rx(rxbuf_hi);
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         dbg_uart_buf = {rxbuf_hi, rxbuf_lo};
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      end
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endtask
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task dbg_uart_rx8;
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      reg [7:0] rxbuf;
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      begin
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         rxbuf = 8'h00;
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         dbg_uart_rx(rxbuf);
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         dbg_uart_buf = {8'h00, rxbuf};
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      end
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endtask
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//----------------------------------------------------------------------------
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// Transmit UART frame to CPU Debug interface (8N1)
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//----------------------------------------------------------------------------
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task dbg_uart_tx;
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      input  [7:0] txbuf;
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      reg [9:0] txbuf_full;
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      integer   txcnt;
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      begin
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         dbg_uart_rxd = 1'b1;
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         txbuf_full   = {1'b1, txbuf, 1'b0};
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         for (txcnt = 0; txcnt < 10; txcnt = txcnt + 1)
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           begin
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              repeat(UART_CNT+1) @(posedge mclk);
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              dbg_uart_rxd =  txbuf_full[txcnt];
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           end
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      end
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endtask
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task dbg_uart_tx16;
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      input  [15:0] txbuf;
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      begin
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         dbg_uart_tx(txbuf[7:0]);
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         dbg_uart_tx(txbuf[15:8]);
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      end
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endtask
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//----------------------------------------------------------------------------
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// Write to Debug register
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//----------------------------------------------------------------------------
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task dbg_uart_wr;
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      input  [7:0] dbg_reg;
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      input [15:0] dbg_data;
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      begin
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         dbg_uart_tx(DBG_WR | dbg_reg);
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         dbg_uart_tx(dbg_data[7:0]);
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         if (~dbg_reg[6])
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           dbg_uart_tx(dbg_data[15:8]);
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      end
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endtask
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//----------------------------------------------------------------------------
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// Read Debug register
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//----------------------------------------------------------------------------
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task dbg_uart_rd;
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      input  [7:0] dbg_reg;
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      reg [7:0] rxbuf_lo;
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      reg [7:0] rxbuf_hi;
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      begin
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         rxbuf_lo = 8'h00;
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         rxbuf_hi = 8'h00;
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         dbg_uart_tx(DBG_RD | dbg_reg);
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         dbg_uart_rx(rxbuf_lo);
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         if (~dbg_reg[6])
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           dbg_uart_rx(rxbuf_hi);
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         dbg_uart_buf = {rxbuf_hi, rxbuf_lo};
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      end
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endtask

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