| 1 |
2 |
olivier.gi |
//----------------------------------------------------------------------------
|
| 2 |
|
|
// Copyright (C) 2001 Authors
|
| 3 |
|
|
//
|
| 4 |
|
|
// This source file may be used and distributed without restriction provided
|
| 5 |
|
|
// that this copyright statement is not removed from the file and that any
|
| 6 |
|
|
// derivative work contains the original copyright notice and the associated
|
| 7 |
|
|
// disclaimer.
|
| 8 |
|
|
//
|
| 9 |
|
|
// This source file is free software; you can redistribute it and/or modify
|
| 10 |
|
|
// it under the terms of the GNU Lesser General Public License as published
|
| 11 |
|
|
// by the Free Software Foundation; either version 2.1 of the License, or
|
| 12 |
|
|
// (at your option) any later version.
|
| 13 |
|
|
//
|
| 14 |
|
|
// This source is distributed in the hope that it will be useful, but WITHOUT
|
| 15 |
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 16 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
|
| 17 |
|
|
// License for more details.
|
| 18 |
|
|
//
|
| 19 |
|
|
// You should have received a copy of the GNU Lesser General Public License
|
| 20 |
|
|
// along with this source; if not, write to the Free Software Foundation,
|
| 21 |
|
|
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
| 22 |
|
|
//
|
| 23 |
|
|
//----------------------------------------------------------------------------
|
| 24 |
|
|
//
|
| 25 |
|
|
// *File Name: msp_debug.v
|
| 26 |
|
|
//
|
| 27 |
|
|
// *Module Description:
|
| 28 |
|
|
// MSP430 core debug utility signals
|
| 29 |
|
|
//
|
| 30 |
|
|
// *Author(s):
|
| 31 |
|
|
// - Olivier Girard, olgirard@gmail.com
|
| 32 |
|
|
//
|
| 33 |
|
|
//----------------------------------------------------------------------------
|
| 34 |
17 |
olivier.gi |
// $Rev: 17 $
|
| 35 |
|
|
// $LastChangedBy: olivier.girard $
|
| 36 |
|
|
// $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
|
| 37 |
|
|
//----------------------------------------------------------------------------
|
| 38 |
2 |
olivier.gi |
`timescale 1ns / 100ps
|
| 39 |
|
|
|
| 40 |
|
|
module msp_debug (
|
| 41 |
|
|
|
| 42 |
|
|
// OUTPUTs
|
| 43 |
|
|
e_state, // Execution state
|
| 44 |
|
|
i_state, // Instruction fetch state
|
| 45 |
|
|
inst_cycle, // Cycle number within current instruction
|
| 46 |
|
|
inst_full, // Currently executed instruction (full version)
|
| 47 |
|
|
inst_number, // Instruction number since last system reset
|
| 48 |
|
|
inst_pc, // Instruction Program counter
|
| 49 |
|
|
inst_short, // Currently executed instruction (short version)
|
| 50 |
|
|
|
| 51 |
|
|
// INPUTs
|
| 52 |
|
|
mclk, // Main system clock
|
| 53 |
|
|
puc // Main system reset
|
| 54 |
|
|
);
|
| 55 |
|
|
|
| 56 |
|
|
// OUTPUTs
|
| 57 |
|
|
//============
|
| 58 |
|
|
output [8*32-1:0] e_state; // Execution state
|
| 59 |
|
|
output [8*32-1:0] i_state; // Instruction fetch state
|
| 60 |
|
|
output [31:0] inst_cycle; // Cycle number within current instruction
|
| 61 |
|
|
output [8*32-1:0] inst_full; // Currently executed instruction (full version)
|
| 62 |
|
|
output [31:0] inst_number; // Instruction number since last system reset
|
| 63 |
|
|
output [15:0] inst_pc; // Instruction Program counter
|
| 64 |
|
|
output [8*32-1:0] inst_short; // Currently executed instruction (short version)
|
| 65 |
|
|
|
| 66 |
|
|
// INPUTs
|
| 67 |
|
|
//============
|
| 68 |
|
|
input mclk; // Main system clock
|
| 69 |
|
|
input puc; // Main system reset
|
| 70 |
|
|
|
| 71 |
|
|
|
| 72 |
|
|
//=============================================================================
|
| 73 |
|
|
// 1) ASCII FORMATING FUNCTIONS
|
| 74 |
|
|
//=============================================================================
|
| 75 |
|
|
|
| 76 |
|
|
// This function simply concatenates two strings together, ignorning the NULL
|
| 77 |
|
|
// at the end of string2.
|
| 78 |
|
|
// The specified number of space will be inserted between string1 and string2
|
| 79 |
|
|
function [64*8-1:0] myFormat;
|
| 80 |
|
|
|
| 81 |
|
|
input [32*8-1:0] string1;
|
| 82 |
|
|
input [32*8-1:0] string2;
|
| 83 |
|
|
input [3:0] space;
|
| 84 |
|
|
|
| 85 |
|
|
integer i,j;
|
| 86 |
|
|
begin
|
| 87 |
|
|
myFormat = 0;
|
| 88 |
|
|
j = 0;
|
| 89 |
|
|
for ( i=0; i < 32; i=i+1) // Copy string2
|
| 90 |
|
|
begin
|
| 91 |
|
|
myFormat[8*i +: 8] = string2[8*i +: 8];
|
| 92 |
|
|
if ((string2[8*i +: 8] == 0) && (j == 0)) j=i;
|
| 93 |
|
|
end
|
| 94 |
|
|
|
| 95 |
|
|
for ( i=0; i < space; i=i+1) // Add spaces
|
| 96 |
|
|
myFormat[8*(j+i) +: 8] = " ";
|
| 97 |
|
|
j=j+space;
|
| 98 |
|
|
|
| 99 |
|
|
for ( i=0; i < 32; i=i+1) // Copy string1
|
| 100 |
|
|
myFormat[8*(j+i) +: 8] = string1[8*i +: 8];
|
| 101 |
|
|
|
| 102 |
|
|
end
|
| 103 |
|
|
endfunction
|
| 104 |
|
|
|
| 105 |
|
|
|
| 106 |
|
|
//=============================================================================
|
| 107 |
|
|
// 2) CONNECTIONS TO MSP430 CORE INTERNALS
|
| 108 |
|
|
//=============================================================================
|
| 109 |
|
|
|
| 110 |
|
|
wire [2:0] i_state_bin = dut.frontend_0.i_state;
|
| 111 |
|
|
wire [3:0] e_state_bin = dut.frontend_0.e_state;
|
| 112 |
|
|
|
| 113 |
|
|
wire decode = dut.frontend_0.decode;
|
| 114 |
|
|
wire [15:0] ir = dut.frontend_0.ir;
|
| 115 |
|
|
wire irq_detect = dut.frontend_0.irq_detect;
|
| 116 |
|
|
wire [3:0] irq_num = dut.frontend_0.irq_num;
|
| 117 |
|
|
wire [15:0] pc = dut.frontend_0.pc;
|
| 118 |
|
|
|
| 119 |
|
|
|
| 120 |
|
|
//=============================================================================
|
| 121 |
|
|
// 3) GENERATE DEBUG SIGNALS
|
| 122 |
|
|
//=============================================================================
|
| 123 |
|
|
|
| 124 |
|
|
// Instruction fetch state
|
| 125 |
|
|
//=========================
|
| 126 |
|
|
reg [8*32-1:0] i_state;
|
| 127 |
|
|
|
| 128 |
|
|
always @(i_state_bin)
|
| 129 |
|
|
case(i_state_bin)
|
| 130 |
|
|
3'h0 : i_state = "IRQ_FETCH";
|
| 131 |
|
|
3'h1 : i_state = "IRQ_DONE";
|
| 132 |
|
|
3'h2 : i_state = "DEC";
|
| 133 |
|
|
3'h3 : i_state = "EXT1";
|
| 134 |
|
|
3'h4 : i_state = "EXT2";
|
| 135 |
|
|
3'h5 : i_state = "IDLE";
|
| 136 |
|
|
default : i_state = "XXXXX";
|
| 137 |
|
|
endcase
|
| 138 |
|
|
|
| 139 |
|
|
|
| 140 |
|
|
// Execution state
|
| 141 |
|
|
//=========================
|
| 142 |
|
|
|
| 143 |
|
|
reg [8*32-1:0] e_state;
|
| 144 |
|
|
|
| 145 |
|
|
always @(e_state_bin)
|
| 146 |
|
|
case(e_state_bin)
|
| 147 |
|
|
4'h0 : e_state = "IRQ_0";
|
| 148 |
|
|
4'h1 : e_state = "IRQ_1";
|
| 149 |
|
|
4'h2 : e_state = "IRQ_2";
|
| 150 |
|
|
4'h3 : e_state = "IRQ_3";
|
| 151 |
|
|
4'h4 : e_state = "IRQ_4";
|
| 152 |
|
|
4'h5 : e_state = "SRC_AD";
|
| 153 |
|
|
4'h6 : e_state = "SRC_RD";
|
| 154 |
|
|
4'h7 : e_state = "SRC_WR";
|
| 155 |
|
|
4'h8 : e_state = "DST_AD";
|
| 156 |
|
|
4'h9 : e_state = "DST_RD";
|
| 157 |
|
|
4'hA : e_state = "DST_WR";
|
| 158 |
|
|
4'hB : e_state = "EXEC";
|
| 159 |
|
|
4'hC : e_state = "JUMP";
|
| 160 |
|
|
4'hD : e_state = "IDLE";
|
| 161 |
|
|
default : e_state = "xxxx";
|
| 162 |
|
|
endcase
|
| 163 |
|
|
|
| 164 |
|
|
|
| 165 |
|
|
// Count instruction number & cycles
|
| 166 |
|
|
//====================================
|
| 167 |
|
|
|
| 168 |
|
|
reg [31:0] inst_number;
|
| 169 |
|
|
always @(posedge mclk or posedge puc)
|
| 170 |
|
|
if (puc) inst_number <= 0;
|
| 171 |
|
|
else if (decode) inst_number <= inst_number+1;
|
| 172 |
|
|
|
| 173 |
|
|
reg [31:0] inst_cycle;
|
| 174 |
|
|
always @(posedge mclk or posedge puc)
|
| 175 |
|
|
if (puc) inst_cycle <= 0;
|
| 176 |
|
|
else if (decode) inst_cycle <= 0;
|
| 177 |
|
|
else inst_cycle <= inst_cycle+1;
|
| 178 |
|
|
|
| 179 |
|
|
|
| 180 |
|
|
// Decode instruction
|
| 181 |
|
|
//====================================
|
| 182 |
|
|
|
| 183 |
|
|
// Buffer opcode
|
| 184 |
|
|
reg [15:0] opcode;
|
| 185 |
|
|
always @(posedge mclk or posedge puc)
|
| 186 |
|
|
if (puc) opcode <= 0;
|
| 187 |
|
|
else if (decode) opcode <= ir;
|
| 188 |
|
|
|
| 189 |
|
|
// Interrupts
|
| 190 |
|
|
reg irq;
|
| 191 |
|
|
always @(posedge mclk or posedge puc)
|
| 192 |
|
|
if (puc) irq <= 1'b1;
|
| 193 |
|
|
else if (decode) irq <= irq_detect;
|
| 194 |
|
|
|
| 195 |
|
|
// Instruction type
|
| 196 |
|
|
reg [8*32-1:0] inst_type;
|
| 197 |
|
|
always @(opcode or irq)
|
| 198 |
|
|
if (irq)
|
| 199 |
|
|
inst_type = "IRQ";
|
| 200 |
|
|
else
|
| 201 |
|
|
case(opcode[15:13])
|
| 202 |
|
|
3'b000 : inst_type = "SIG-OP";
|
| 203 |
|
|
3'b001 : inst_type = "JUMP";
|
| 204 |
|
|
default : inst_type = "TWO-OP";
|
| 205 |
|
|
endcase
|
| 206 |
|
|
|
| 207 |
|
|
|
| 208 |
|
|
// Instructions name
|
| 209 |
|
|
reg [8*32-1:0] inst_name;
|
| 210 |
|
|
always @(opcode or inst_type or irq_num)
|
| 211 |
|
|
if (inst_type=="IRQ")
|
| 212 |
|
|
case(irq_num[3:0])
|
| 213 |
|
|
4'b0000 : inst_name = "IRQ 0";
|
| 214 |
|
|
4'b0001 : inst_name = "IRQ 1";
|
| 215 |
|
|
4'b0010 : inst_name = "IRQ 2";
|
| 216 |
|
|
4'b0011 : inst_name = "IRQ 3";
|
| 217 |
|
|
4'b0100 : inst_name = "IRQ 4";
|
| 218 |
|
|
4'b0101 : inst_name = "IRQ 5";
|
| 219 |
|
|
4'b0110 : inst_name = "IRQ 6";
|
| 220 |
|
|
4'b0111 : inst_name = "IRQ 7";
|
| 221 |
|
|
4'b1000 : inst_name = "IRQ 8";
|
| 222 |
|
|
4'b1001 : inst_name = "IRQ 9";
|
| 223 |
|
|
4'b1010 : inst_name = "IRQ 10";
|
| 224 |
|
|
4'b1011 : inst_name = "IRQ 11";
|
| 225 |
|
|
4'b1100 : inst_name = "IRQ 12";
|
| 226 |
|
|
4'b1101 : inst_name = "IRQ 13";
|
| 227 |
|
|
4'b1110 : inst_name = "NMI";
|
| 228 |
|
|
default : inst_name = "RESET";
|
| 229 |
|
|
endcase
|
| 230 |
|
|
else if (inst_type=="SIG-OP")
|
| 231 |
|
|
case(opcode[15:7])
|
| 232 |
|
|
9'b000100_000 : inst_name = "RRC";
|
| 233 |
|
|
9'b000100_001 : inst_name = "SWPB";
|
| 234 |
|
|
9'b000100_010 : inst_name = "RRA";
|
| 235 |
|
|
9'b000100_011 : inst_name = "SXT";
|
| 236 |
|
|
9'b000100_100 : inst_name = "PUSH";
|
| 237 |
|
|
9'b000100_101 : inst_name = "CALL";
|
| 238 |
|
|
9'b000100_110 : inst_name = "RETI";
|
| 239 |
|
|
default : inst_name = "xxxx";
|
| 240 |
|
|
endcase
|
| 241 |
|
|
else if (inst_type=="JUMP")
|
| 242 |
|
|
case(opcode[15:10])
|
| 243 |
|
|
6'b001_000 : inst_name = "JNE";
|
| 244 |
|
|
6'b001_001 : inst_name = "JEQ";
|
| 245 |
|
|
6'b001_010 : inst_name = "JNC";
|
| 246 |
|
|
6'b001_011 : inst_name = "JC";
|
| 247 |
|
|
6'b001_100 : inst_name = "JN";
|
| 248 |
|
|
6'b001_101 : inst_name = "JGE";
|
| 249 |
|
|
6'b001_110 : inst_name = "JL";
|
| 250 |
|
|
6'b001_111 : inst_name = "JMP";
|
| 251 |
|
|
default : inst_name = "xxxx";
|
| 252 |
|
|
endcase
|
| 253 |
|
|
else if (inst_type=="TWO-OP")
|
| 254 |
|
|
case(opcode[15:12])
|
| 255 |
|
|
4'b0100 : inst_name = "MOV";
|
| 256 |
|
|
4'b0101 : inst_name = "ADD";
|
| 257 |
|
|
4'b0110 : inst_name = "ADDC";
|
| 258 |
|
|
4'b0111 : inst_name = "SUBC";
|
| 259 |
|
|
4'b1000 : inst_name = "SUB";
|
| 260 |
|
|
4'b1001 : inst_name = "CMP";
|
| 261 |
|
|
4'b1010 : inst_name = "DADD";
|
| 262 |
|
|
4'b1011 : inst_name = "BIT";
|
| 263 |
|
|
4'b1100 : inst_name = "BIC";
|
| 264 |
|
|
4'b1101 : inst_name = "BIS";
|
| 265 |
|
|
4'b1110 : inst_name = "XOR";
|
| 266 |
|
|
4'b1111 : inst_name = "AND";
|
| 267 |
|
|
default : inst_name = "xxxx";
|
| 268 |
|
|
endcase
|
| 269 |
|
|
|
| 270 |
|
|
// Instructions byte/word mode
|
| 271 |
|
|
reg [8*32-1:0] inst_bw;
|
| 272 |
|
|
always @(opcode or inst_type)
|
| 273 |
|
|
if (inst_type=="IRQ")
|
| 274 |
|
|
inst_bw = "";
|
| 275 |
|
|
else if (inst_type=="SIG-OP")
|
| 276 |
|
|
inst_bw = opcode[6] ? ".B" : "";
|
| 277 |
|
|
else if (inst_type=="JUMP")
|
| 278 |
|
|
inst_bw = "";
|
| 279 |
|
|
else if (inst_type=="TWO-OP")
|
| 280 |
|
|
inst_bw = opcode[6] ? ".B" : "";
|
| 281 |
|
|
|
| 282 |
|
|
// Source register
|
| 283 |
|
|
reg [8*32-1:0] inst_src;
|
| 284 |
|
|
wire [3:0] src_reg = (inst_type=="SIG-OP") ? opcode[3:0] : opcode[11:8];
|
| 285 |
|
|
|
| 286 |
|
|
always @(src_reg or inst_type)
|
| 287 |
|
|
if (inst_type=="IRQ")
|
| 288 |
|
|
inst_src = "";
|
| 289 |
|
|
else if (inst_type=="JUMP")
|
| 290 |
|
|
inst_src = "";
|
| 291 |
|
|
else if ((inst_type=="SIG-OP") || (inst_type=="TWO-OP"))
|
| 292 |
|
|
case(src_reg)
|
| 293 |
|
|
4'b0000 : inst_src = "r0";
|
| 294 |
|
|
4'b0001 : inst_src = "r1";
|
| 295 |
|
|
4'b0010 : inst_src = "r2";
|
| 296 |
|
|
4'b0011 : inst_src = "r3";
|
| 297 |
|
|
4'b0100 : inst_src = "r4";
|
| 298 |
|
|
4'b0101 : inst_src = "r5";
|
| 299 |
|
|
4'b0110 : inst_src = "r6";
|
| 300 |
|
|
4'b0111 : inst_src = "r7";
|
| 301 |
|
|
4'b1000 : inst_src = "r8";
|
| 302 |
|
|
4'b1001 : inst_src = "r9";
|
| 303 |
|
|
4'b1010 : inst_src = "r10";
|
| 304 |
|
|
4'b1011 : inst_src = "r11";
|
| 305 |
|
|
4'b1100 : inst_src = "r12";
|
| 306 |
|
|
4'b1101 : inst_src = "r13";
|
| 307 |
|
|
4'b1110 : inst_src = "r14";
|
| 308 |
|
|
default : inst_src = "r15";
|
| 309 |
|
|
endcase
|
| 310 |
|
|
|
| 311 |
|
|
// Destination register
|
| 312 |
|
|
reg [8*32-1:0] inst_dst;
|
| 313 |
|
|
always @(opcode or inst_type)
|
| 314 |
|
|
if (inst_type=="IRQ")
|
| 315 |
|
|
inst_dst = "";
|
| 316 |
|
|
else if (inst_type=="SIG-OP")
|
| 317 |
|
|
inst_dst = "";
|
| 318 |
|
|
else if (inst_type=="JUMP")
|
| 319 |
|
|
inst_dst = "";
|
| 320 |
|
|
else if (inst_type=="TWO-OP")
|
| 321 |
|
|
case(opcode[3:0])
|
| 322 |
|
|
4'b0000 : inst_dst = "r0";
|
| 323 |
|
|
4'b0001 : inst_dst = "r1";
|
| 324 |
|
|
4'b0010 : inst_dst = "r2";
|
| 325 |
|
|
4'b0011 : inst_dst = "r3";
|
| 326 |
|
|
4'b0100 : inst_dst = "r4";
|
| 327 |
|
|
4'b0101 : inst_dst = "r5";
|
| 328 |
|
|
4'b0110 : inst_dst = "r6";
|
| 329 |
|
|
4'b0111 : inst_dst = "r7";
|
| 330 |
|
|
4'b1000 : inst_dst = "r8";
|
| 331 |
|
|
4'b1001 : inst_dst = "r9";
|
| 332 |
|
|
4'b1010 : inst_dst = "r10";
|
| 333 |
|
|
4'b1011 : inst_dst = "r11";
|
| 334 |
|
|
4'b1100 : inst_dst = "r12";
|
| 335 |
|
|
4'b1101 : inst_dst = "r13";
|
| 336 |
|
|
4'b1110 : inst_dst = "r14";
|
| 337 |
|
|
default : inst_dst = "r15";
|
| 338 |
|
|
endcase
|
| 339 |
|
|
|
| 340 |
|
|
// Source Addressing mode
|
| 341 |
|
|
reg [8*32-1:0] inst_as;
|
| 342 |
|
|
always @(inst_type or src_reg or opcode or inst_src)
|
| 343 |
|
|
begin
|
| 344 |
|
|
if (inst_type=="IRQ")
|
| 345 |
|
|
inst_as = "";
|
| 346 |
|
|
else if (inst_type=="JUMP")
|
| 347 |
|
|
inst_as = "";
|
| 348 |
|
|
else if (src_reg==4'h3) // Addressing mode using R3
|
| 349 |
|
|
case (opcode[5:4])
|
| 350 |
|
|
2'b11 : inst_as = "#-1";
|
| 351 |
|
|
2'b10 : inst_as = "#2";
|
| 352 |
|
|
2'b01 : inst_as = "#1";
|
| 353 |
|
|
default: inst_as = "#0";
|
| 354 |
|
|
endcase
|
| 355 |
|
|
else if (src_reg==4'h2) // Addressing mode using R2
|
| 356 |
|
|
case (opcode[5:4])
|
| 357 |
|
|
2'b11 : inst_as = "#8";
|
| 358 |
|
|
2'b10 : inst_as = "#4";
|
| 359 |
|
|
2'b01 : inst_as = "&EDE";
|
| 360 |
|
|
default: inst_as = inst_src;
|
| 361 |
|
|
endcase
|
| 362 |
|
|
else if (src_reg==4'h0) // Addressing mode using R0
|
| 363 |
|
|
case (opcode[5:4])
|
| 364 |
|
|
2'b11 : inst_as = "#N";
|
| 365 |
|
|
2'b10 : inst_as = myFormat("@", inst_src, 0);
|
| 366 |
|
|
2'b01 : inst_as = "EDE";
|
| 367 |
|
|
default: inst_as = inst_src;
|
| 368 |
|
|
endcase
|
| 369 |
|
|
else // General Addressing mode
|
| 370 |
|
|
case (opcode[5:4])
|
| 371 |
|
|
2'b11 : begin
|
| 372 |
|
|
inst_as = myFormat("@", inst_src, 0);
|
| 373 |
|
|
inst_as = myFormat(inst_as, "+", 0);
|
| 374 |
|
|
end
|
| 375 |
|
|
2'b10 : inst_as = myFormat("@", inst_src, 0);
|
| 376 |
|
|
2'b01 : begin
|
| 377 |
|
|
inst_as = myFormat("x(", inst_src, 0);
|
| 378 |
|
|
inst_as = myFormat(inst_as, ")", 0);
|
| 379 |
|
|
end
|
| 380 |
|
|
default: inst_as = inst_src;
|
| 381 |
|
|
endcase
|
| 382 |
|
|
end
|
| 383 |
|
|
|
| 384 |
|
|
// Destination Addressing mode
|
| 385 |
|
|
reg [8*32-1:0] inst_ad;
|
| 386 |
|
|
always @(opcode or inst_type or inst_dst)
|
| 387 |
|
|
begin
|
| 388 |
|
|
if (inst_type!="TWO-OP")
|
| 389 |
|
|
inst_ad = "";
|
| 390 |
|
|
else if (opcode[3:0]==4'h2) // Addressing mode using R2
|
| 391 |
|
|
case (opcode[7])
|
| 392 |
|
|
1'b1 : inst_ad = "&EDE";
|
| 393 |
|
|
default: inst_ad = inst_dst;
|
| 394 |
|
|
endcase
|
| 395 |
|
|
else if (opcode[3:0]==4'h0) // Addressing mode using R0
|
| 396 |
|
|
case (opcode[7])
|
| 397 |
|
|
2'b1 : inst_ad = "EDE";
|
| 398 |
|
|
default: inst_ad = inst_dst;
|
| 399 |
|
|
endcase
|
| 400 |
|
|
else // General Addressing mode
|
| 401 |
|
|
case (opcode[7])
|
| 402 |
|
|
2'b1 : begin
|
| 403 |
|
|
inst_ad = myFormat("x(", inst_dst, 0);
|
| 404 |
|
|
inst_ad = myFormat(inst_ad, ")", 0);
|
| 405 |
|
|
end
|
| 406 |
|
|
default: inst_ad = inst_dst;
|
| 407 |
|
|
endcase
|
| 408 |
|
|
end
|
| 409 |
|
|
|
| 410 |
|
|
|
| 411 |
|
|
// Currently executed instruction
|
| 412 |
|
|
//================================
|
| 413 |
|
|
|
| 414 |
|
|
wire [32*8-1:0] inst_short = inst_name;
|
| 415 |
|
|
|
| 416 |
|
|
reg [32*8-1:0] inst_full;
|
| 417 |
|
|
always @(inst_type or inst_name or inst_bw or inst_as or inst_ad)
|
| 418 |
|
|
begin
|
| 419 |
|
|
inst_full = myFormat(inst_name, inst_bw, 0);
|
| 420 |
|
|
inst_full = myFormat(inst_full, inst_as, 1);
|
| 421 |
|
|
if (inst_type=="TWO-OP")
|
| 422 |
|
|
inst_full = myFormat(inst_full, ",", 0);
|
| 423 |
|
|
inst_full = myFormat(inst_full, inst_ad, 1);
|
| 424 |
|
|
if (opcode==16'h4303)
|
| 425 |
|
|
inst_full = "NOP";
|
| 426 |
|
|
if (opcode==`DBG_SWBRK_OP)
|
| 427 |
|
|
inst_full = "SBREAK";
|
| 428 |
|
|
|
| 429 |
|
|
end
|
| 430 |
|
|
|
| 431 |
|
|
|
| 432 |
|
|
// Instruction program counter
|
| 433 |
|
|
//================================
|
| 434 |
|
|
|
| 435 |
|
|
reg [15:0] inst_pc;
|
| 436 |
|
|
always @(posedge mclk or posedge puc)
|
| 437 |
|
|
if (puc) inst_pc <= 16'h0000;
|
| 438 |
|
|
else if (decode) inst_pc <= pc;
|
| 439 |
|
|
|
| 440 |
|
|
|
| 441 |
|
|
endmodule // msp_debug
|
| 442 |
|
|
|
