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[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [registers.v] - Blame information for rev 17

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1 2 olivier.gi 
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: registers.v
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//
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// *Module Description:
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//                      Direct connections to internal registers & memory.
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//
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
35 17 olivier.gi 
// $Rev: 17 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
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//----------------------------------------------------------------------------
39 2 olivier.gi 
 
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// CPU registers
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//======================
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wire       [15:0] r0    = dut.execution_unit_0.register_file_0.r0;
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wire       [15:0] r1    = dut.execution_unit_0.register_file_0.r1;
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wire       [15:0] r2    = dut.execution_unit_0.register_file_0.r2;
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wire       [15:0] r3    = dut.execution_unit_0.register_file_0.r3;
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wire       [15:0] r4    = dut.execution_unit_0.register_file_0.r4;
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wire       [15:0] r5    = dut.execution_unit_0.register_file_0.r5;
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wire       [15:0] r6    = dut.execution_unit_0.register_file_0.r6;
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wire       [15:0] r7    = dut.execution_unit_0.register_file_0.r7;
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wire       [15:0] r8    = dut.execution_unit_0.register_file_0.r8;
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wire       [15:0] r9    = dut.execution_unit_0.register_file_0.r9;
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wire       [15:0] r10   = dut.execution_unit_0.register_file_0.r10;
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wire       [15:0] r11   = dut.execution_unit_0.register_file_0.r11;
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wire       [15:0] r12   = dut.execution_unit_0.register_file_0.r12;
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wire       [15:0] r13   = dut.execution_unit_0.register_file_0.r13;
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wire       [15:0] r14   = dut.execution_unit_0.register_file_0.r14;
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wire       [15:0] r15   = dut.execution_unit_0.register_file_0.r15;
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// RAM cells
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//======================
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wire       [15:0] mem200 = ram_0.mem[0];
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wire       [15:0] mem202 = ram_0.mem[1];
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wire       [15:0] mem204 = ram_0.mem[2];
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wire       [15:0] mem206 = ram_0.mem[3];
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wire       [15:0] mem208 = ram_0.mem[4];
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wire       [15:0] mem20A = ram_0.mem[5];
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wire       [15:0] mem20C = ram_0.mem[6];
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wire       [15:0] mem20E = ram_0.mem[7];
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wire       [15:0] mem210 = ram_0.mem[8];
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wire       [15:0] mem212 = ram_0.mem[9];
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wire       [15:0] mem214 = ram_0.mem[10];
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wire       [15:0] mem216 = ram_0.mem[11];
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wire       [15:0] mem218 = ram_0.mem[12];
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wire       [15:0] mem21A = ram_0.mem[13];
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wire       [15:0] mem21C = ram_0.mem[14];
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wire       [15:0] mem21E = ram_0.mem[15];
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wire       [15:0] mem220 = ram_0.mem[16];
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wire       [15:0] mem222 = ram_0.mem[17];
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wire       [15:0] mem224 = ram_0.mem[18];
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wire       [15:0] mem226 = ram_0.mem[19];
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wire       [15:0] mem228 = ram_0.mem[20];
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wire       [15:0] mem22A = ram_0.mem[21];
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wire       [15:0] mem22C = ram_0.mem[22];
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wire       [15:0] mem22E = ram_0.mem[23];
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wire       [15:0] mem230 = ram_0.mem[24];
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wire       [15:0] mem232 = ram_0.mem[25];
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wire       [15:0] mem234 = ram_0.mem[26];
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wire       [15:0] mem236 = ram_0.mem[27];
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wire       [15:0] mem238 = ram_0.mem[28];
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wire       [15:0] mem23A = ram_0.mem[29];
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wire       [15:0] mem23C = ram_0.mem[30];
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wire       [15:0] mem23E = ram_0.mem[31];
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wire       [15:0] mem240 = ram_0.mem[32];
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wire       [15:0] mem242 = ram_0.mem[33];
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wire       [15:0] mem244 = ram_0.mem[34];
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wire       [15:0] mem246 = ram_0.mem[35];
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wire       [15:0] mem248 = ram_0.mem[36];
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wire       [15:0] mem24A = ram_0.mem[37];
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wire       [15:0] mem24C = ram_0.mem[38];
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wire       [15:0] mem24E = ram_0.mem[39];
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wire       [15:0] mem250 = ram_0.mem[40];
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wire       [15:0] mem252 = ram_0.mem[41];
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wire       [15:0] mem254 = ram_0.mem[42];
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wire       [15:0] mem256 = ram_0.mem[43];
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wire       [15:0] mem258 = ram_0.mem[44];
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wire       [15:0] mem25A = ram_0.mem[45];
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wire       [15:0] mem25C = ram_0.mem[46];
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wire       [15:0] mem25E = ram_0.mem[47];
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wire       [15:0] mem260 = ram_0.mem[48];
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wire       [15:0] mem262 = ram_0.mem[49];
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wire       [15:0] mem264 = ram_0.mem[50];
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wire       [15:0] mem266 = ram_0.mem[51];
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wire       [15:0] mem268 = ram_0.mem[52];
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wire       [15:0] mem26A = ram_0.mem[53];
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wire       [15:0] mem26C = ram_0.mem[54];
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wire       [15:0] mem26E = ram_0.mem[55];
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wire       [15:0] mem270 = ram_0.mem[56];
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wire       [15:0] mem272 = ram_0.mem[57];
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wire       [15:0] mem274 = ram_0.mem[58];
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wire       [15:0] mem276 = ram_0.mem[59];
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wire       [15:0] mem278 = ram_0.mem[60];
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wire       [15:0] mem27A = ram_0.mem[61];
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wire       [15:0] mem27C = ram_0.mem[62];
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wire       [15:0] mem27E = ram_0.mem[63];
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wire       [15:0] mem280 = ram_0.mem[64];
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// Interrupt vectors
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//======================
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wire       [15:0] irq_vect_15 = rom_0.mem[(1<<(`ROM_MSB+1))-1];  // RESET Vector
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wire       [15:0] irq_vect_14 = rom_0.mem[(1<<(`ROM_MSB+1))-2];  // NMI
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wire       [15:0] irq_vect_13 = rom_0.mem[(1<<(`ROM_MSB+1))-3];  // IRQ 13
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wire       [15:0] irq_vect_12 = rom_0.mem[(1<<(`ROM_MSB+1))-4];  // IRQ 12
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wire       [15:0] irq_vect_11 = rom_0.mem[(1<<(`ROM_MSB+1))-5];  // IRQ 11
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wire       [15:0] irq_vect_10 = rom_0.mem[(1<<(`ROM_MSB+1))-6];  // IRQ 10
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wire       [15:0] irq_vect_09 = rom_0.mem[(1<<(`ROM_MSB+1))-7];  // IRQ  9
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wire       [15:0] irq_vect_08 = rom_0.mem[(1<<(`ROM_MSB+1))-8];  // IRQ  8
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wire       [15:0] irq_vect_07 = rom_0.mem[(1<<(`ROM_MSB+1))-9];  // IRQ  7
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wire       [15:0] irq_vect_06 = rom_0.mem[(1<<(`ROM_MSB+1))-10]; // IRQ  6
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wire       [15:0] irq_vect_05 = rom_0.mem[(1<<(`ROM_MSB+1))-11]; // IRQ  5
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wire       [15:0] irq_vect_04 = rom_0.mem[(1<<(`ROM_MSB+1))-12]; // IRQ  4
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wire       [15:0] irq_vect_03 = rom_0.mem[(1<<(`ROM_MSB+1))-13]; // IRQ  3
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wire       [15:0] irq_vect_02 = rom_0.mem[(1<<(`ROM_MSB+1))-14]; // IRQ  2
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wire       [15:0] irq_vect_01 = rom_0.mem[(1<<(`ROM_MSB+1))-15]; // IRQ  1
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wire       [15:0] irq_vect_00 = rom_0.mem[(1<<(`ROM_MSB+1))-16]; // IRQ  0

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