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[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [registers.v] - Blame information for rev 196

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1 2 olivier.gi 
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: registers.v
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//
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// *Module Description:
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//                      Direct connections to internal registers & memory.
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//
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 145 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-05-30 23:03:05 +0200 (Wed, 30 May 2012) $
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//----------------------------------------------------------------------------
39 2 olivier.gi 
 
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// CPU registers
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//======================
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wire       [15:0] r0    = dut.execution_unit_0.register_file_0.r0;
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wire       [15:0] r1    = dut.execution_unit_0.register_file_0.r1;
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wire       [15:0] r2    = dut.execution_unit_0.register_file_0.r2;
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wire       [15:0] r3    = dut.execution_unit_0.register_file_0.r3;
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wire       [15:0] r4    = dut.execution_unit_0.register_file_0.r4;
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wire       [15:0] r5    = dut.execution_unit_0.register_file_0.r5;
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wire       [15:0] r6    = dut.execution_unit_0.register_file_0.r6;
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wire       [15:0] r7    = dut.execution_unit_0.register_file_0.r7;
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wire       [15:0] r8    = dut.execution_unit_0.register_file_0.r8;
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wire       [15:0] r9    = dut.execution_unit_0.register_file_0.r9;
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wire       [15:0] r10   = dut.execution_unit_0.register_file_0.r10;
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wire       [15:0] r11   = dut.execution_unit_0.register_file_0.r11;
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wire       [15:0] r12   = dut.execution_unit_0.register_file_0.r12;
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wire       [15:0] r13   = dut.execution_unit_0.register_file_0.r13;
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wire       [15:0] r14   = dut.execution_unit_0.register_file_0.r14;
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wire       [15:0] r15   = dut.execution_unit_0.register_file_0.r15;
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// RAM cells
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//======================
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64 33 olivier.gi 
wire       [15:0] mem200 = dmem_0.mem[0];
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wire       [15:0] mem202 = dmem_0.mem[1];
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wire       [15:0] mem204 = dmem_0.mem[2];
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wire       [15:0] mem206 = dmem_0.mem[3];
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wire       [15:0] mem208 = dmem_0.mem[4];
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wire       [15:0] mem20A = dmem_0.mem[5];
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wire       [15:0] mem20C = dmem_0.mem[6];
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wire       [15:0] mem20E = dmem_0.mem[7];
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wire       [15:0] mem210 = dmem_0.mem[8];
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wire       [15:0] mem212 = dmem_0.mem[9];
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wire       [15:0] mem214 = dmem_0.mem[10];
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wire       [15:0] mem216 = dmem_0.mem[11];
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wire       [15:0] mem218 = dmem_0.mem[12];
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wire       [15:0] mem21A = dmem_0.mem[13];
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wire       [15:0] mem21C = dmem_0.mem[14];
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wire       [15:0] mem21E = dmem_0.mem[15];
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wire       [15:0] mem220 = dmem_0.mem[16];
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wire       [15:0] mem222 = dmem_0.mem[17];
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wire       [15:0] mem224 = dmem_0.mem[18];
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wire       [15:0] mem226 = dmem_0.mem[19];
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wire       [15:0] mem228 = dmem_0.mem[20];
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wire       [15:0] mem22A = dmem_0.mem[21];
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wire       [15:0] mem22C = dmem_0.mem[22];
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wire       [15:0] mem22E = dmem_0.mem[23];
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wire       [15:0] mem230 = dmem_0.mem[24];
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wire       [15:0] mem232 = dmem_0.mem[25];
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wire       [15:0] mem234 = dmem_0.mem[26];
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wire       [15:0] mem236 = dmem_0.mem[27];
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wire       [15:0] mem238 = dmem_0.mem[28];
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wire       [15:0] mem23A = dmem_0.mem[29];
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wire       [15:0] mem23C = dmem_0.mem[30];
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wire       [15:0] mem23E = dmem_0.mem[31];
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wire       [15:0] mem240 = dmem_0.mem[32];
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wire       [15:0] mem242 = dmem_0.mem[33];
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wire       [15:0] mem244 = dmem_0.mem[34];
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wire       [15:0] mem246 = dmem_0.mem[35];
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wire       [15:0] mem248 = dmem_0.mem[36];
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wire       [15:0] mem24A = dmem_0.mem[37];
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wire       [15:0] mem24C = dmem_0.mem[38];
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wire       [15:0] mem24E = dmem_0.mem[39];
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wire       [15:0] mem250 = dmem_0.mem[40];
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wire       [15:0] mem252 = dmem_0.mem[41];
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wire       [15:0] mem254 = dmem_0.mem[42];
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wire       [15:0] mem256 = dmem_0.mem[43];
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wire       [15:0] mem258 = dmem_0.mem[44];
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wire       [15:0] mem25A = dmem_0.mem[45];
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wire       [15:0] mem25C = dmem_0.mem[46];
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wire       [15:0] mem25E = dmem_0.mem[47];
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wire       [15:0] mem260 = dmem_0.mem[48];
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wire       [15:0] mem262 = dmem_0.mem[49];
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wire       [15:0] mem264 = dmem_0.mem[50];
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wire       [15:0] mem266 = dmem_0.mem[51];
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wire       [15:0] mem268 = dmem_0.mem[52];
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wire       [15:0] mem26A = dmem_0.mem[53];
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wire       [15:0] mem26C = dmem_0.mem[54];
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wire       [15:0] mem26E = dmem_0.mem[55];
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wire       [15:0] mem270 = dmem_0.mem[56];
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wire       [15:0] mem272 = dmem_0.mem[57];
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wire       [15:0] mem274 = dmem_0.mem[58];
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wire       [15:0] mem276 = dmem_0.mem[59];
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wire       [15:0] mem278 = dmem_0.mem[60];
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wire       [15:0] mem27A = dmem_0.mem[61];
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wire       [15:0] mem27C = dmem_0.mem[62];
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wire       [15:0] mem27E = dmem_0.mem[63];
128 2 olivier.gi 
 
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// Interrupt vectors
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//======================
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133 145 olivier.gi 
wire       [15:0] irq_vect_15 = pmem_0.mem[(`PMEM_SIZE>>1)-1];  // RESET Vector
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wire       [15:0] irq_vect_14 = pmem_0.mem[(`PMEM_SIZE>>1)-2];  // NMI
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wire       [15:0] irq_vect_13 = pmem_0.mem[(`PMEM_SIZE>>1)-3];  // IRQ 13
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wire       [15:0] irq_vect_12 = pmem_0.mem[(`PMEM_SIZE>>1)-4];  // IRQ 12
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wire       [15:0] irq_vect_11 = pmem_0.mem[(`PMEM_SIZE>>1)-5];  // IRQ 11
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wire       [15:0] irq_vect_10 = pmem_0.mem[(`PMEM_SIZE>>1)-6];  // IRQ 10
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wire       [15:0] irq_vect_09 = pmem_0.mem[(`PMEM_SIZE>>1)-7];  // IRQ  9
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wire       [15:0] irq_vect_08 = pmem_0.mem[(`PMEM_SIZE>>1)-8];  // IRQ  8
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wire       [15:0] irq_vect_07 = pmem_0.mem[(`PMEM_SIZE>>1)-9];  // IRQ  7
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wire       [15:0] irq_vect_06 = pmem_0.mem[(`PMEM_SIZE>>1)-10]; // IRQ  6
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wire       [15:0] irq_vect_05 = pmem_0.mem[(`PMEM_SIZE>>1)-11]; // IRQ  5
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wire       [15:0] irq_vect_04 = pmem_0.mem[(`PMEM_SIZE>>1)-12]; // IRQ  4
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wire       [15:0] irq_vect_03 = pmem_0.mem[(`PMEM_SIZE>>1)-13]; // IRQ  3
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wire       [15:0] irq_vect_02 = pmem_0.mem[(`PMEM_SIZE>>1)-14]; // IRQ  2
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wire       [15:0] irq_vect_01 = pmem_0.mem[(`PMEM_SIZE>>1)-15]; // IRQ  1
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wire       [15:0] irq_vect_00 = pmem_0.mem[(`PMEM_SIZE>>1)-16]; // IRQ  0
149 94 olivier.gi 
 
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// Interrupt detection
151 134 olivier.gi 
wire              nmi_detect  = dut.frontend_0.nmi_pnd;
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wire              irq_detect  = dut.frontend_0.irq_detect;
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// Debug interface
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wire              dbg_clk     = dut.clock_module_0.dbg_clk;
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wire              dbg_rst     = dut.clock_module_0.dbg_rst;
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// CPU ID
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//======================
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 wire  [2:0] dbg_cpu_version  =  `CPU_VERSION;
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`ifdef ASIC
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 wire        dbg_cpu_asic     =  1'b1;
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`else
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 wire        dbg_cpu_asic     =  1'b0;
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`endif
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 wire  [4:0] dbg_user_version =  `USER_VERSION;
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 wire  [6:0] dbg_per_space    = (`PER_SIZE  >> 9);
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`ifdef MULTIPLIER
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 wire        dbg_mpy_info     =  1'b1;
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`else
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 wire        dbg_mpy_info     =  1'b0;
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`endif
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 wire  [8:0] dbg_dmem_size    = (`DMEM_SIZE >> 7);
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 wire  [5:0] dbg_pmem_size    = (`PMEM_SIZE >> 10);
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 wire [31:0] dbg_cpu_id       = {dbg_pmem_size,
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                                 dbg_dmem_size,
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                                 dbg_mpy_info,
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                                 dbg_per_space,
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                                 dbg_user_version,
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                                 dbg_cpu_asic,
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                                 dbg_cpu_version};

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