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[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [tb_openMSP430.v] - Blame information for rev 34

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1 2 olivier.gi
//----------------------------------------------------------------------------
2
// Copyright (C) 2001 Authors
3
//
4
// This source file may be used and distributed without restriction provided
5
// that this copyright statement is not removed from the file and that any
6
// derivative work contains the original copyright notice and the associated
7
// disclaimer.
8
//
9
// This source file is free software; you can redistribute it and/or modify
10
// it under the terms of the GNU Lesser General Public License as published
11
// by the Free Software Foundation; either version 2.1 of the License, or
12
// (at your option) any later version.
13
//
14
// This source is distributed in the hope that it will be useful, but WITHOUT
15
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
17
// License for more details.
18
//
19
// You should have received a copy of the GNU Lesser General Public License
20
// along with this source; if not, write to the Free Software Foundation,
21
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
22
//
23
//----------------------------------------------------------------------------
24
// 
25
// *File Name: tb_openMSP430.v
26
// 
27
// *Module Description:
28
//                      openMSP430 testbench
29
//
30
// *Author(s):
31
//              - Olivier Girard,    olgirard@gmail.com
32
//
33
//----------------------------------------------------------------------------
34 17 olivier.gi
// $Rev: 34 $
35
// $LastChangedBy: olivier.girard $
36
// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Tue, 29 Dec 2009) $
37
//----------------------------------------------------------------------------
38 23 olivier.gi
`include "timescale.v"
39
`include "openMSP430_defines.v"
40 2 olivier.gi
 
41
 
42
module  tb_openMSP430;
43
 
44
//
45
// Wire & Register definition
46
//------------------------------
47
 
48 33 olivier.gi
// Data Memory interface
49
wire [`DMEM_MSB:0] dmem_addr;
50
wire               dmem_cen;
51
wire        [15:0] dmem_din;
52
wire         [1:0] dmem_wen;
53
wire        [15:0] dmem_dout;
54 2 olivier.gi
 
55 33 olivier.gi
// Program Memory interface
56
wire [`PMEM_MSB:0] pmem_addr;
57
wire               pmem_cen;
58
wire        [15:0] pmem_din;
59
wire         [1:0] pmem_wen;
60
wire        [15:0] pmem_dout;
61 2 olivier.gi
 
62
// Peripherals interface
63 33 olivier.gi
wire         [7:0] per_addr;
64
wire        [15:0] per_din;
65
wire        [15:0] per_dout;
66
wire         [1:0] per_wen;
67
wire               per_en;
68 2 olivier.gi
 
69
// Digital I/O
70 33 olivier.gi
wire               irq_port1;
71
wire               irq_port2;
72
wire        [15:0] per_dout_dio;
73
wire         [7:0] p1_dout;
74
wire         [7:0] p1_dout_en;
75
wire         [7:0] p1_sel;
76
wire         [7:0] p2_dout;
77
wire         [7:0] p2_dout_en;
78
wire         [7:0] p2_sel;
79
wire         [7:0] p3_dout;
80
wire         [7:0] p3_dout_en;
81
wire         [7:0] p3_sel;
82
wire         [7:0] p4_dout;
83
wire         [7:0] p4_dout_en;
84
wire         [7:0] p4_sel;
85
wire         [7:0] p5_dout;
86
wire         [7:0] p5_dout_en;
87
wire         [7:0] p5_sel;
88
wire         [7:0] p6_dout;
89
wire         [7:0] p6_dout_en;
90
wire         [7:0] p6_sel;
91
reg          [7:0] p1_din;
92
reg          [7:0] p2_din;
93
reg          [7:0] p3_din;
94
reg          [7:0] p4_din;
95
reg          [7:0] p5_din;
96
reg          [7:0] p6_din;
97 2 olivier.gi
 
98
// Peripheral templates
99 33 olivier.gi
wire        [15:0] per_dout_temp_8b;
100
wire        [15:0] per_dout_temp_16b;
101 2 olivier.gi
 
102
// Timer A
103 33 olivier.gi
wire               irq_ta0;
104
wire               irq_ta1;
105
wire        [15:0] per_dout_timerA;
106
reg                inclk;
107
reg                taclk;
108
reg                ta_cci0a;
109
reg                ta_cci0b;
110
reg                ta_cci1a;
111
reg                ta_cci1b;
112
reg                ta_cci2a;
113
reg                ta_cci2b;
114
wire               ta_out0;
115
wire               ta_out0_en;
116
wire               ta_out1;
117
wire               ta_out1_en;
118
wire               ta_out2;
119
wire               ta_out2_en;
120 2 olivier.gi
 
121
// Clock / Reset & Interrupts
122 33 olivier.gi
reg                dco_clk;
123
reg                lfxt_clk;
124
wire               mclk;
125
wire               aclk_en;
126
wire               smclk_en;
127
reg                reset_n;
128
wire               puc;
129
reg                nmi;
130
reg         [13:0] irq;
131
wire        [13:0] irq_acc;
132
wire        [13:0] irq_in;
133 2 olivier.gi
 
134
// Debug interface
135 33 olivier.gi
wire               dbg_freeze;
136
wire               dbg_uart_txd;
137
reg                dbg_uart_rxd;
138
reg         [15:0] dbg_uart_buf;
139 2 olivier.gi
 
140
// Core testbench debuging signals
141 33 olivier.gi
wire    [8*32-1:0] i_state;
142
wire    [8*32-1:0] e_state;
143
wire        [31:0] inst_cycle;
144
wire    [8*32-1:0] inst_full;
145
wire        [31:0] inst_number;
146
wire        [15:0] inst_pc;
147
wire    [8*32-1:0] inst_short;
148 2 olivier.gi
 
149
// Testbench variables
150 33 olivier.gi
integer            error;
151
reg                stimulus_done;
152 2 olivier.gi
 
153
 
154
//
155
// Include files
156
//------------------------------
157
 
158
// CPU & Memory registers
159
`include "registers.v"
160
 
161
// Debug interface tasks
162
`include "dbg_uart_tasks.v"
163
 
164
// Verilog stimulus
165
`include "stimulus.v"
166
 
167
 
168
//
169
// Initialize ROM
170
//------------------------------
171
initial
172
  begin
173 33 olivier.gi
     $readmemh("./pmem.mem", pmem_0.mem);
174 2 olivier.gi
  end
175
 
176
//
177
// Generate Clock & Reset
178
//------------------------------
179
initial
180
  begin
181
     dco_clk = 1'b0;
182
     forever #25 dco_clk <= ~dco_clk;   // 20 MHz
183
  end
184
initial
185
  begin
186
     lfxt_clk = 1'b0;
187
     forever #763 lfxt_clk <= ~lfxt_clk; // 655 kHz
188
  end
189
 
190
initial
191
  begin
192
     reset_n       = 1'b1;
193
     #100;
194
     reset_n       = 1'b0;
195
     #600;
196
     reset_n       = 1'b1;
197
  end
198
 
199
initial
200
  begin
201
     error         = 0;
202
     stimulus_done = 1;
203
     irq           = 14'b0000;
204
     nmi           = 1'b0;
205
     dbg_uart_rxd  = 1'b0;
206
     dbg_uart_buf  = 16'h0000;
207
     p1_din        = 8'h00;
208
     p2_din        = 8'h00;
209
     p3_din        = 8'h00;
210
     p4_din        = 8'h00;
211
     p5_din        = 8'h00;
212
     p6_din        = 8'h00;
213
     inclk         = 1'b0;
214
     taclk         = 1'b0;
215
     ta_cci0a      = 1'b0;
216
     ta_cci0b      = 1'b0;
217
     ta_cci1a      = 1'b0;
218
     ta_cci1b      = 1'b0;
219
     ta_cci2a      = 1'b0;
220
     ta_cci2b      = 1'b0;
221
  end
222
 
223
 
224
//
225 33 olivier.gi
// Program Memory
226 2 olivier.gi
//----------------------------------
227
 
228 33 olivier.gi
ram #(`PMEM_MSB) pmem_0 (
229 2 olivier.gi
 
230
// OUTPUTs
231 33 olivier.gi
    .ram_dout    (pmem_dout),          // Program Memory data output
232 2 olivier.gi
 
233
// INPUTs
234 33 olivier.gi
    .ram_addr    (pmem_addr),          // Program Memory address
235
    .ram_cen     (pmem_cen),           // Program Memory chip enable (low active)
236
    .ram_clk     (mclk),               // Program Memory clock
237
    .ram_din     (pmem_din),           // Program Memory data input
238
    .ram_wen     (pmem_wen)            // Program Memory write enable (low active)
239 2 olivier.gi
);
240
 
241
 
242
//
243 33 olivier.gi
// Data Memory
244 2 olivier.gi
//----------------------------------
245
 
246 33 olivier.gi
ram #(`DMEM_MSB) dmem_0 (
247 2 olivier.gi
 
248
// OUTPUTs
249 33 olivier.gi
    .ram_dout    (dmem_dout),          // Data Memory data output
250 2 olivier.gi
 
251
// INPUTs
252 33 olivier.gi
    .ram_addr    (dmem_addr),          // Data Memory address
253
    .ram_cen     (dmem_cen),           // Data Memory chip enable (low active)
254
    .ram_clk     (mclk),               // Data Memory clock
255
    .ram_din     (dmem_din),           // Data Memory data input
256
    .ram_wen     (dmem_wen)            // Data Memory write enable (low active)
257 2 olivier.gi
);
258
 
259
 
260
//
261
// openMSP430 Instance
262
//----------------------------------
263
 
264
openMSP430 dut (
265
 
266
// OUTPUTs
267
    .aclk_en      (aclk_en),           // ACLK enable
268
    .dbg_freeze   (dbg_freeze),        // Freeze peripherals
269
    .dbg_uart_txd (dbg_uart_txd),      // Debug interface: UART TXD
270 33 olivier.gi
    .dmem_addr    (dmem_addr),         // Data Memory address
271
    .dmem_cen     (dmem_cen),          // Data Memory chip enable (low active)
272
    .dmem_din     (dmem_din),          // Data Memory data input
273
    .dmem_wen     (dmem_wen),          // Data Memory write enable (low active)
274 2 olivier.gi
    .irq_acc      (irq_acc),           // Interrupt request accepted (one-hot signal)
275
    .mclk         (mclk),              // Main system clock
276
    .per_addr     (per_addr),          // Peripheral address
277
    .per_din      (per_din),           // Peripheral data input
278
    .per_wen      (per_wen),           // Peripheral write enable (high active)
279
    .per_en       (per_en),            // Peripheral enable (high active)
280 33 olivier.gi
    .pmem_addr    (pmem_addr),         // Program Memory address
281
    .pmem_cen     (pmem_cen),          // Program Memory chip enable (low active)
282
    .pmem_din     (pmem_din),          // Program Memory data input (optional)
283
    .pmem_wen     (pmem_wen),          // Program Memory write enable (low active) (optional)
284 2 olivier.gi
    .puc          (puc),               // Main system reset
285
    .smclk_en     (smclk_en),          // SMCLK enable
286
 
287
// INPUTs
288
    .dbg_uart_rxd (dbg_uart_rxd),      // Debug interface: UART RXD
289
    .dco_clk      (dco_clk),           // Fast oscillator (fast clock)
290 33 olivier.gi
    .dmem_dout    (dmem_dout),         // Data Memory data output
291 2 olivier.gi
    .irq          (irq_in),            // Maskable interrupts
292
    .lfxt_clk     (lfxt_clk),          // Low frequency oscillator (typ 32kHz)
293
    .nmi          (nmi),               // Non-maskable interrupt (asynchronous)
294
    .per_dout     (per_dout),          // Peripheral data output
295 33 olivier.gi
    .pmem_dout    (pmem_dout),         // Program Memory data output
296
    .reset_n      (reset_n)            // Reset Pin (low active)
297 2 olivier.gi
);
298
 
299
//
300
// Digital I/O
301
//----------------------------------
302
 
303 34 olivier.gi
omsp_gpio #(.P1_EN(1),
304
            .P2_EN(1),
305
            .P3_EN(1),
306
            .P4_EN(1),
307
            .P5_EN(1),
308
            .P6_EN(1)) gpio_0 (
309 2 olivier.gi
 
310
// OUTPUTs
311
    .irq_port1    (irq_port1),         // Port 1 interrupt
312
    .irq_port2    (irq_port2),         // Port 2 interrupt
313
    .p1_dout      (p1_dout),           // Port 1 data output
314
    .p1_dout_en   (p1_dout_en),        // Port 1 data output enable
315
    .p1_sel       (p1_sel),            // Port 1 function select
316
    .p2_dout      (p2_dout),           // Port 2 data output
317
    .p2_dout_en   (p2_dout_en),        // Port 2 data output enable
318
    .p2_sel       (p2_sel),            // Port 2 function select
319
    .p3_dout      (p3_dout),           // Port 3 data output
320
    .p3_dout_en   (p3_dout_en),        // Port 3 data output enable
321
    .p3_sel       (p3_sel),            // Port 3 function select
322
    .p4_dout      (p4_dout),           // Port 4 data output
323
    .p4_dout_en   (p4_dout_en),        // Port 4 data output enable
324
    .p4_sel       (p4_sel),            // Port 4 function select
325
    .p5_dout      (p5_dout),           // Port 5 data output
326
    .p5_dout_en   (p5_dout_en),        // Port 5 data output enable
327
    .p5_sel       (p5_sel),            // Port 5 function select
328
    .p6_dout      (p6_dout),           // Port 6 data output
329
    .p6_dout_en   (p6_dout_en),        // Port 6 data output enable
330
    .p6_sel       (p6_sel),            // Port 6 function select
331
    .per_dout     (per_dout_dio),      // Peripheral data output
332
 
333
// INPUTs
334
    .mclk         (mclk),              // Main system clock
335
    .p1_din       (p1_din),            // Port 1 data input
336
    .p2_din       (p2_din),            // Port 2 data input
337
    .p3_din       (p3_din),            // Port 3 data input
338
    .p4_din       (p4_din),            // Port 4 data input
339
    .p5_din       (p5_din),            // Port 5 data input
340
    .p6_din       (p6_din),            // Port 6 data input
341
    .per_addr     (per_addr),          // Peripheral address
342
    .per_din      (per_din),           // Peripheral data input
343
    .per_en       (per_en),            // Peripheral enable (high active)
344
    .per_wen      (per_wen),           // Peripheral write enable (high active)
345
    .puc          (puc)                // Main system reset
346
);
347
 
348
//
349
// Timers
350
//----------------------------------
351
 
352 34 olivier.gi
omsp_timerA timerA_0 (
353 2 olivier.gi
 
354
// OUTPUTs
355
    .irq_ta0      (irq_ta0),           // Timer A interrupt: TACCR0
356
    .irq_ta1      (irq_ta1),           // Timer A interrupt: TAIV, TACCR1, TACCR2
357
    .per_dout     (per_dout_timerA),   // Peripheral data output
358
    .ta_out0      (ta_out0),           // Timer A output 0
359
    .ta_out0_en   (ta_out0_en),        // Timer A output 0 enable
360
    .ta_out1      (ta_out1),           // Timer A output 1
361
    .ta_out1_en   (ta_out1_en),        // Timer A output 1 enable
362
    .ta_out2      (ta_out2),           // Timer A output 2
363
    .ta_out2_en   (ta_out2_en),        // Timer A output 2 enable
364
 
365
// INPUTs
366
    .aclk_en      (aclk_en),           // ACLK enable (from CPU)
367
    .dbg_freeze   (dbg_freeze),        // Freeze Timer A counter
368
    .inclk        (inclk),             // INCLK external timer clock (SLOW)
369
    .irq_ta0_acc  (irq_acc[9]),        // Interrupt request TACCR0 accepted
370
    .mclk         (mclk),              // Main system clock
371
    .per_addr     (per_addr),          // Peripheral address
372
    .per_din      (per_din),           // Peripheral data input
373
    .per_en       (per_en),            // Peripheral enable (high active)
374
    .per_wen      (per_wen),           // Peripheral write enable (high active)
375
    .puc          (puc),               // Main system reset
376
    .smclk_en     (smclk_en),          // SMCLK enable (from CPU)
377
    .ta_cci0a     (ta_cci0a),          // Timer A compare 0 input A
378
    .ta_cci0b     (ta_cci0b),          // Timer A compare 0 input B
379
    .ta_cci1a     (ta_cci1a),          // Timer A compare 1 input A
380
    .ta_cci1b     (ta_cci1b),          // Timer A compare 1 input B
381
    .ta_cci2a     (ta_cci2a),          // Timer A compare 2 input A
382
    .ta_cci2b     (ta_cci2b),          // Timer A compare 2 input B
383
    .taclk        (taclk)              // TACLK external timer clock (SLOW)
384
);
385
 
386
//
387
// Peripheral templates
388
//----------------------------------
389
 
390
template_periph_8b template_periph_8b_0 (
391
 
392
// OUTPUTs
393
    .per_dout     (per_dout_temp_8b),  // Peripheral data output
394
 
395
// INPUTs
396
    .mclk         (mclk),              // Main system clock
397
    .per_addr     (per_addr),          // Peripheral address
398
    .per_din      (per_din),           // Peripheral data input
399
    .per_en       (per_en),            // Peripheral enable (high active)
400
    .per_wen      (per_wen),           // Peripheral write enable (high active)
401
    .puc          (puc)                // Main system reset
402
);
403
 
404
template_periph_16b template_periph_16b_0 (
405
 
406
// OUTPUTs
407
    .per_dout     (per_dout_temp_16b), // Peripheral data output
408
 
409
// INPUTs
410
    .mclk         (mclk),              // Main system clock
411
    .per_addr     (per_addr),          // Peripheral address
412
    .per_din      (per_din),           // Peripheral data input
413
    .per_en       (per_en),            // Peripheral enable (high active)
414
    .per_wen      (per_wen),           // Peripheral write enable (high active)
415
    .puc          (puc)                // Main system reset
416
);
417
 
418
 
419
//
420
// Combine peripheral data bus
421
//----------------------------------
422
 
423
assign per_dout = per_dout_dio       |
424
                  per_dout_timerA    |
425
                  per_dout_temp_8b   |
426
                  per_dout_temp_16b;
427
 
428
 
429
//
430
// Map peripheral interrupts
431
//----------------------------------------
432
 
433
assign irq_in = irq | {1'b0,           // Vector 13  (0xFFFA)
434
                       1'b0,           // Vector 12  (0xFFF8)
435
                       1'b0,           // Vector 11  (0xFFF6)
436
                       1'b0,           // Vector 10  (0xFFF4) - Watchdog -
437
                       irq_ta0,        // Vector  9  (0xFFF2)
438
                       irq_ta1,        // Vector  8  (0xFFF0)
439
                       1'b0,           // Vector  7  (0xFFEE)
440
                       1'b0,           // Vector  6  (0xFFEC)
441
                       1'b0,           // Vector  5  (0xFFEA)
442
                       1'b0,           // Vector  4  (0xFFE8)
443
                       irq_port2,      // Vector  3  (0xFFE6)
444
                       irq_port1,      // Vector  2  (0xFFE4)
445
                       1'b0,           // Vector  1  (0xFFE2)
446
                       1'b0};          // Vector  0  (0xFFE0)
447
 
448
 
449
//
450
// Debug utility signals
451
//----------------------------------------
452
msp_debug msp_debug_0 (
453
 
454
// OUTPUTs
455
    .e_state      (e_state),           // Execution state
456
    .i_state      (i_state),           // Instruction fetch state
457
    .inst_cycle   (inst_cycle),        // Cycle number within current instruction
458
    .inst_full    (inst_full),         // Currently executed instruction (full version)
459
    .inst_number  (inst_number),       // Instruction number since last system reset
460
    .inst_pc      (inst_pc),           // Instruction Program counter
461
    .inst_short   (inst_short),        // Currently executed instruction (short version)
462
 
463
// INPUTs
464
    .mclk         (mclk),              // Main system clock
465
    .puc          (puc)                // Main system reset
466
);
467
 
468
 
469
//
470
// Generate Waveform
471
//----------------------------------------
472
initial
473
  begin
474
   `ifdef VPD_FILE
475
     $vcdplusfile("tb_openMSP430.vpd");
476
     $vcdpluson();
477
   `else
478
     $dumpfile("tb_openMSP430.vcd");
479
     $dumpvars(0, tb_openMSP430);
480
   `endif
481
  end
482
 
483
//
484
// End of simulation
485
//----------------------------------------
486
 
487
initial // Timeout
488
  begin
489
    `ifdef LONG_TIMEOUT
490
     #5000000;
491
   `else
492
     #500000;
493
   `endif
494
     $display(" ===============================================");
495
     $display("|               SIMULATION FAILED               |");
496
     $display("|              (simulation Timeout)             |");
497
     $display(" ===============================================");
498
     $finish;
499
  end
500
 
501
initial // Normal end of test
502
  begin
503
     @(inst_pc===16'hffff)
504
     $display(" ===============================================");
505
     if (error!=0)
506
       begin
507
          $display("|               SIMULATION FAILED               |");
508
          $display("|     (some verilog stimulus checks failed)     |");
509
       end
510
     else if (~stimulus_done)
511
       begin
512
          $display("|               SIMULATION FAILED               |");
513
          $display("|     (the verilog stimulus didn't complete)    |");
514
       end
515
     else
516
       begin
517
          $display("|               SIMULATION PASSED               |");
518
       end
519
     $display(" ===============================================");
520
     $finish;
521
  end
522
 
523
 
524
//
525
// Tasks Definition
526
//------------------------------
527
 
528
   task tb_error;
529
      input [65*8:0] error_string;
530
      begin
531
         $display("ERROR: %s %t", error_string, $time);
532
         error = error+1;
533
      end
534
   endtask
535
 
536
 
537
endmodule

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