OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_and_gate.v] - Blame information for rev 145

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 134 olivier.gi
//----------------------------------------------------------------------------
2
// Copyright (C) 2009 , Olivier Girard
3
//
4
// Redistribution and use in source and binary forms, with or without
5
// modification, are permitted provided that the following conditions
6
// are met:
7
//     * Redistributions of source code must retain the above copyright
8
//       notice, this list of conditions and the following disclaimer.
9
//     * Redistributions in binary form must reproduce the above copyright
10
//       notice, this list of conditions and the following disclaimer in the
11
//       documentation and/or other materials provided with the distribution.
12
//     * Neither the name of the authors nor the names of its contributors
13
//       may be used to endorse or promote products derived from this software
14
//       without specific prior written permission.
15
//
16
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
21
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26
// THE POSSIBILITY OF SUCH DAMAGE
27
//
28
//----------------------------------------------------------------------------
29
//
30
// *File Name: omsp_and_gate.v
31
// 
32
// *Module Description:
33
//                       Generic AND gate cell for the openMSP430
34
//
35
// *Author(s):
36
//              - Olivier Girard,    olgirard@gmail.com
37
//
38
//----------------------------------------------------------------------------
39
// $Rev: 103 $
40
// $LastChangedBy: olivier.girard $
41
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
42
//----------------------------------------------------------------------------
43
 
44
module  omsp_and_gate (
45
 
46
// OUTPUTs
47
    y,                         // AND gate output
48
 
49
// INPUTs
50
    a,                         // AND gate input A
51
    b                          // AND gate input B
52
);
53
 
54
// OUTPUTs
55
//=========
56
output         y;              // AND gate output
57
 
58
// INPUTs
59
//=========
60
input          a;              // AND gate input A
61
input          b;              // AND gate input B
62
 
63
 
64
//=============================================================================
65
// 1)  SOME COMMENTS ON THIS MODULE
66
//=============================================================================
67
//
68
//    In its ASIC version, some combinatorial pathes of the openMSP430 are
69
// sensitive to glitches, in particular the ones generating the wakeup
70
// signals.
71
//    To prevent synthesis from optmizing combinatorial clouds into glitchy
72
// logic, this AND gate module has been instanciated in the critical places.
73
//
74
//    Make sure that synthesis doesn't ungroup this module. As an alternative,
75
// a standard cell from the library could also be directly instanciated here
76
// (don't forget the "dont_touch" attribute)
77
//
78
//
79
//=============================================================================
80
// 2)  AND GATE
81
//=============================================================================
82
 
83
assign  y  =  a & b;
84
 
85
 
86
endmodule // omsp_and_gate
87
 
88
 
89
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.