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olivier.gi |
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//----------------------------------------------------------------------------
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//
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olivier.gi |
// *File Name: omsp_dbg_hwbrk.v
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olivier.gi |
//
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// *Module Description:
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// Hardware Breakpoint / Watchpoint module
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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olivier.gi |
// $Rev: 57 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2010-02-01 23:56:03 +0100 (Mon, 01 Feb 2010) $
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//----------------------------------------------------------------------------
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olivier.gi |
`include "timescale.v"
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`include "openMSP430_defines.v"
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olivier.gi |
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olivier.gi |
module omsp_dbg_hwbrk (
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olivier.gi |
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// OUTPUTs
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brk_halt, // Hardware breakpoint command
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brk_pnd, // Hardware break/watch-point pending
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brk_dout, // Hardware break/watch-point register data input
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// INPUTs
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brk_reg_rd, // Hardware break/watch-point register read select
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brk_reg_wr, // Hardware break/watch-point register write select
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dbg_din, // Debug register data input
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eu_mab, // Execution-Unit Memory address bus
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eu_mb_en, // Execution-Unit Memory bus enable
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eu_mb_wr, // Execution-Unit Memory bus write transfer
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eu_mdb_in, // Memory data bus input
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eu_mdb_out, // Memory data bus output
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exec_done, // Execution completed
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fe_mb_en, // Frontend Memory bus enable
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mclk, // Main system clock
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pc, // Program counter
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por // Power on reset
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);
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// OUTPUTs
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//=========
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output brk_halt; // Hardware breakpoint command
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output brk_pnd; // Hardware break/watch-point pending
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output [15:0] brk_dout; // Hardware break/watch-point register data input
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// INPUTs
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//=========
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input [3:0] brk_reg_rd; // Hardware break/watch-point register read select
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input [3:0] brk_reg_wr; // Hardware break/watch-point register write select
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input [15:0] dbg_din; // Debug register data input
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input [15:0] eu_mab; // Execution-Unit Memory address bus
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input eu_mb_en; // Execution-Unit Memory bus enable
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input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
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input [15:0] eu_mdb_in; // Memory data bus input
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input [15:0] eu_mdb_out; // Memory data bus output
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input exec_done; // Execution completed
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input fe_mb_en; // Frontend Memory bus enable
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input mclk; // Main system clock
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input [15:0] pc; // Program counter
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input por; // Power on reset
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//=============================================================================
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// 1) WIRE & PARAMETER DECLARATION
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//=============================================================================
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wire range_wr_set;
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wire range_rd_set;
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wire addr1_wr_set;
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wire addr1_rd_set;
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wire addr0_wr_set;
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wire addr0_rd_set;
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parameter BRK_CTL = 0,
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BRK_STAT = 1,
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BRK_ADDR0 = 2,
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BRK_ADDR1 = 3;
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//=============================================================================
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// 2) CONFIGURATION REGISTERS
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//=============================================================================
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// BRK_CTL Register
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//-----------------------------------------------------------------------------
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// 7 6 5 4 3 2 1 0
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// Reserved RANGE_MODE INST_EN BREAK_EN ACCESS_MODE
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//
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// ACCESS_MODE: - 00 : Disabled
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// - 01 : Detect read access
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// - 10 : Detect write access
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// - 11 : Detect read/write access
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// NOTE: '10' & '11' modes are not supported on the instruction flow
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//
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// BREAK_EN: - 0 : Watchmode enable
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// - 1 : Break enable
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//
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// INST_EN: - 0 : Checks are done on the execution unit (data flow)
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// - 1 : Checks are done on the frontend (instruction flow)
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//
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// RANGE_MODE: - 0 : Address match on BRK_ADDR0 or BRK_ADDR1
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// - 1 : Address match on BRK_ADDR0->BRK_ADDR1 range
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//
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//-----------------------------------------------------------------------------
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reg [4:0] brk_ctl;
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wire brk_ctl_wr = brk_reg_wr[BRK_CTL];
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always @ (posedge mclk or posedge por)
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if (por) brk_ctl <= 5'h00;
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else if (brk_ctl_wr) brk_ctl <= {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]};
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wire [7:0] brk_ctl_full = {3'b000, brk_ctl};
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// BRK_STAT Register
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//-----------------------------------------------------------------------------
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// 7 6 5 4 3 2 1 0
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// Reserved RANGE_WR RANGE_RD ADDR1_WR ADDR1_RD ADDR0_WR ADDR0_RD
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//-----------------------------------------------------------------------------
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reg [5:0] brk_stat;
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wire brk_stat_wr = brk_reg_wr[BRK_STAT];
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wire [5:0] brk_stat_set = {range_wr_set & `HWBRK_RANGE,
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range_rd_set & `HWBRK_RANGE,
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addr1_wr_set, addr1_rd_set,
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addr0_wr_set, addr0_rd_set};
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wire [5:0] brk_stat_clr = ~dbg_din[5:0];
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always @ (posedge mclk or posedge por)
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if (por) brk_stat <= 6'h00;
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else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set);
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else brk_stat <= (brk_stat | brk_stat_set);
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wire [7:0] brk_stat_full = {2'b00, brk_stat};
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wire brk_pnd = |brk_stat;
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// BRK_ADDR0 Register
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//-----------------------------------------------------------------------------
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reg [15:0] brk_addr0;
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wire brk_addr0_wr = brk_reg_wr[BRK_ADDR0];
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always @ (posedge mclk or posedge por)
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if (por) brk_addr0 <= 16'h0000;
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else if (brk_addr0_wr) brk_addr0 <= dbg_din;
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// BRK_ADDR1/DATA0 Register
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//-----------------------------------------------------------------------------
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reg [15:0] brk_addr1;
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wire brk_addr1_wr = brk_reg_wr[BRK_ADDR1];
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always @ (posedge mclk or posedge por)
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if (por) brk_addr1 <= 16'h0000;
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else if (brk_addr1_wr) brk_addr1 <= dbg_din;
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//============================================================================
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// 3) DATA OUTPUT GENERATION
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//============================================================================
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wire [15:0] brk_ctl_rd = {8'h00, brk_ctl_full} & {16{brk_reg_rd[BRK_CTL]}};
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wire [15:0] brk_stat_rd = {8'h00, brk_stat_full} & {16{brk_reg_rd[BRK_STAT]}};
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wire [15:0] brk_addr0_rd = brk_addr0 & {16{brk_reg_rd[BRK_ADDR0]}};
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wire [15:0] brk_addr1_rd = brk_addr1 & {16{brk_reg_rd[BRK_ADDR1]}};
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wire [15:0] brk_dout = brk_ctl_rd |
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brk_stat_rd |
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brk_addr0_rd |
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brk_addr1_rd;
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//============================================================================
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// 4) BREAKPOINT / WATCHPOINT GENERATION
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//============================================================================
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// Comparators
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//---------------------------
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// Note: here the comparison logic is instanciated several times in order
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// to improve the timings, at the cost of a bit more area.
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wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE];
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wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
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wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) &
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brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
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reg fe_mb_en_buf;
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always @ (posedge mclk or posedge por)
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if (por) fe_mb_en_buf <= 1'b0;
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else fe_mb_en_buf <= fe_mb_en;
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wire equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
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wire equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
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wire equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) &
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brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
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olivier.gi |
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// Detect accesses
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//---------------------------
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// Detect Instruction read access
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wire i_addr0_rd = equ_i_addr0 & brk_ctl[`BRK_I_EN];
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wire i_addr1_rd = equ_i_addr1 & brk_ctl[`BRK_I_EN];
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wire i_range_rd = equ_i_range & brk_ctl[`BRK_I_EN];
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// Detect Execution-Unit write access
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wire d_addr0_wr = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
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wire d_addr1_wr = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
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wire d_range_wr = equ_d_range & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
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// Detect DATA read access
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// Whenever an "ADD r9. &0x200" instruction is executed, &0x200 will be read
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// before being written back. In that case, the read flag should not be set.
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// In general, We should here make sure no write access occures during the
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// same instruction cycle before setting the read flag.
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reg [2:0] d_rd_trig;
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always @ (posedge mclk or posedge por)
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if (por) d_rd_trig <= 3'h0;
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else if (exec_done) d_rd_trig <= 3'h0;
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else d_rd_trig <= {equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
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equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
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equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr};
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wire d_addr0_rd = d_rd_trig[0] & exec_done & ~d_addr0_wr;
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wire d_addr1_rd = d_rd_trig[1] & exec_done & ~d_addr1_wr;
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wire d_range_rd = d_rd_trig[2] & exec_done & ~d_range_wr;
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// Set flags
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assign addr0_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr0_rd | i_addr0_rd);
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assign addr0_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr0_wr;
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assign addr1_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr1_rd | i_addr1_rd);
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assign addr1_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr1_wr;
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assign range_rd_set = brk_ctl[`BRK_MODE_RD] & (d_range_rd | i_range_rd);
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assign range_wr_set = brk_ctl[`BRK_MODE_WR] & d_range_wr;
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// Break CPU
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assign brk_halt = brk_ctl[`BRK_EN] & |brk_stat_set;
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olivier.gi |
endmodule // omsp_dbg_hwbrk
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olivier.gi |
`include "openMSP430_undefines.v"
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