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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_dbg_uart.v] - Blame information for rev 117

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1 2 olivier.gi
//----------------------------------------------------------------------------
2 117 olivier.gi
// Copyright (C) 2009 , Olivier Girard
3 2 olivier.gi
//
4 117 olivier.gi
// Redistribution and use in source and binary forms, with or without
5
// modification, are permitted provided that the following conditions
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// are met:
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//     * Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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//     * Redistributions in binary form must reproduce the above copyright
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//       notice, this list of conditions and the following disclaimer in the
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//       documentation and/or other materials provided with the distribution.
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//     * Neither the name of the authors nor the names of its contributors
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//       may be used to endorse or promote products derived from this software
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//       without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
27 2 olivier.gi
//
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//----------------------------------------------------------------------------
29
//
30 34 olivier.gi
// *File Name: omsp_dbg_uart.v
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// 
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// *Module Description:
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//                       Debug UART communication interface (8N1, Half-duplex)
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
38
//----------------------------------------------------------------------------
39 17 olivier.gi
// $Rev: 117 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-06-23 21:30:51 +0200 (Thu, 23 Jun 2011) $
42
//----------------------------------------------------------------------------
43 103 olivier.gi
`ifdef OMSP_NO_INCLUDE
44
`else
45 23 olivier.gi
`include "openMSP430_defines.v"
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`endif
47 2 olivier.gi
 
48 34 olivier.gi
module  omsp_dbg_uart (
49 2 olivier.gi
 
50
// OUTPUTs
51
    dbg_addr,                       // Debug register address
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    dbg_din,                        // Debug register data input
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    dbg_rd,                         // Debug register data read
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    dbg_uart_txd,                   // Debug interface: UART TXD
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    dbg_wr,                         // Debug register data write
56
 
57
// INPUTs
58 106 olivier.gi
    dbg_clk,                        // Debug unit clock
59 2 olivier.gi
    dbg_dout,                       // Debug register data output
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    dbg_rd_rdy,                     // Debug register data is ready for read
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    dbg_rst,                        // Debug unit reset
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    dbg_uart_rxd,                   // Debug interface: UART RXD
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    mem_burst,                      // Burst on going
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    mem_burst_end,                  // End TX/RX burst
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    mem_burst_rd,                   // Start TX burst
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    mem_burst_wr,                   // Start RX burst
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    mem_bw                          // Burst byte width
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);
69
 
70
// OUTPUTs
71
//=========
72
output        [5:0] dbg_addr;       // Debug register address
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output       [15:0] dbg_din;        // Debug register data input
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output              dbg_rd;         // Debug register data read
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output              dbg_uart_txd;   // Debug interface: UART TXD
76
output              dbg_wr;         // Debug register data write
77
 
78
// INPUTs
79
//=========
80 106 olivier.gi
input               dbg_clk;        // Debug unit clock
81 2 olivier.gi
input        [15:0] dbg_dout;       // Debug register data output
82
input               dbg_rd_rdy;     // Debug register data is ready for read
83 106 olivier.gi
input               dbg_rst;        // Debug unit reset
84 2 olivier.gi
input               dbg_uart_rxd;   // Debug interface: UART RXD
85
input               mem_burst;      // Burst on going
86
input               mem_burst_end;  // End TX/RX burst
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input               mem_burst_rd;   // Start TX burst
88
input               mem_burst_wr;   // Start RX burst
89
input               mem_bw;         // Burst byte width
90
 
91
 
92
//=============================================================================
93
// 1)  UART RECEIVE LINE SYNCHRONIZTION & FILTERING
94
//=============================================================================
95
 
96 111 olivier.gi
// Synchronize RXD input
97 2 olivier.gi
//--------------------------------
98 111 olivier.gi
`ifdef SYNC_DBG_UART_RXD
99
 
100
    wire uart_rxd_n;
101
 
102
    omsp_sync_cell sync_cell_uart_rxd (
103
        .data_out (uart_rxd_n),
104
        .clk      (dbg_clk),
105
        .data_in  (~dbg_uart_rxd),
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        .rst      (dbg_rst)
107
    );
108
    wire uart_rxd = ~uart_rxd_n;
109
`else
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    wire uart_rxd = dbg_uart_rxd;
111
`endif
112
 
113
// RXD input buffer
114
//--------------------------------
115
reg  [1:0] rxd_buf;
116 106 olivier.gi
always @ (posedge dbg_clk or posedge dbg_rst)
117 111 olivier.gi
  if (dbg_rst) rxd_buf <=  2'h3;
118
  else         rxd_buf <=  {rxd_buf[0], uart_rxd};
119 2 olivier.gi
 
120
// Majority decision
121
//------------------------
122
reg        rxd_maj;
123
 
124 111 olivier.gi
wire [1:0] rxd_maj_cnt = {1'b0, uart_rxd}   +
125
                         {1'b0, rxd_buf[0]} +
126
                         {1'b0, rxd_buf[1]};
127 2 olivier.gi
wire       rxd_maj_nxt = (rxd_maj_cnt>=2'b10);
128
 
129 106 olivier.gi
always @ (posedge dbg_clk or posedge dbg_rst)
130
  if (dbg_rst) rxd_maj <=  1'b0;
131
  else         rxd_maj <=  rxd_maj_nxt;
132 2 olivier.gi
 
133
wire rxd_s  =  rxd_maj;
134
wire rxd_fe =  rxd_maj & ~rxd_maj_nxt;
135
wire rxd_re = ~rxd_maj &  rxd_maj_nxt;
136
 
137
 
138
//=============================================================================
139
// 2)  UART STATE MACHINE
140
//=============================================================================
141
 
142
// Receive state
143
//------------------------
144
reg  [2:0] uart_state;
145
reg  [2:0] uart_state_nxt;
146
 
147
wire       sync_done;
148
wire       xfer_done;
149
reg [19:0] xfer_buf;
150
 
151
// State machine definition
152
parameter  RX_SYNC  = 3'h0;
153
parameter  RX_CMD   = 3'h1;
154
parameter  RX_DATA1 = 3'h2;
155
parameter  RX_DATA2 = 3'h3;
156
parameter  TX_DATA1 = 3'h4;
157
parameter  TX_DATA2 = 3'h5;
158
 
159
// State transition
160
always @(uart_state or xfer_buf or mem_burst or mem_burst_wr or mem_burst_rd or mem_burst_end or mem_bw)
161
  case (uart_state)
162
    RX_SYNC  : uart_state_nxt =  RX_CMD;
163
    RX_CMD   : uart_state_nxt =  mem_burst_wr                ?
164
                                (mem_bw                      ? RX_DATA2 : RX_DATA1) :
165
                                 mem_burst_rd                ?
166
                                (mem_bw                      ? TX_DATA2 : TX_DATA1) :
167
                                (xfer_buf[`DBG_UART_WR]      ?
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                                (xfer_buf[`DBG_UART_BW]      ? RX_DATA2 : RX_DATA1) :
169
                                (xfer_buf[`DBG_UART_BW]      ? TX_DATA2 : TX_DATA1));
170
    RX_DATA1 : uart_state_nxt =  RX_DATA2;
171
    RX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
172
                                (mem_bw                      ? RX_DATA2 : RX_DATA1) :
173
                                 RX_CMD;
174
    TX_DATA1 : uart_state_nxt =  TX_DATA2;
175
    TX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
176
                                (mem_bw                      ? TX_DATA2 : TX_DATA1) :
177
                                 RX_CMD;
178
    default  : uart_state_nxt =  RX_CMD;
179
  endcase
180
 
181
// State machine
182 106 olivier.gi
always @(posedge dbg_clk or posedge dbg_rst)
183
  if (dbg_rst)                          uart_state <= RX_SYNC;
184 2 olivier.gi
  else if (xfer_done    | sync_done |
185
           mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;
186
 
187
// Utility signals
188
wire cmd_valid = (uart_state==RX_CMD) & xfer_done;
189
wire tx_active = (uart_state==TX_DATA1) | (uart_state==TX_DATA2);
190
 
191
 
192
//=============================================================================
193
// 3)  UART SYNCHRONIZATION
194
//=============================================================================
195 106 olivier.gi
// After DBG_RST, the host needs to fist send a synchronization character (0x80)
196 2 olivier.gi
// If this feature doesn't work properly, it is possible to disable it by
197
// commenting the DBG_UART_AUTO_SYNC define in the openMSP430.inc file.
198
 
199
reg        sync_busy;
200 106 olivier.gi
always @ (posedge dbg_clk or posedge dbg_rst)
201
  if (dbg_rst)                             sync_busy <=  1'b0;
202 2 olivier.gi
  else if ((uart_state==RX_SYNC) & rxd_fe) sync_busy <=  1'b1;
203
  else if ((uart_state==RX_SYNC) & rxd_re) sync_busy <=  1'b0;
204
 
205
assign sync_done =  (uart_state==RX_SYNC) & rxd_re & sync_busy;
206
 
207
`ifdef DBG_UART_AUTO_SYNC
208
 
209 74 olivier.gi
reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt;
210 106 olivier.gi
always @ (posedge dbg_clk or posedge dbg_rst)
211
  if (dbg_rst)        sync_cnt <=  {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000};
212 74 olivier.gi
  else if (sync_busy) sync_cnt <=  sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1'b0}}, 1'b1};
213 2 olivier.gi
 
214 74 olivier.gi
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3];
215 2 olivier.gi
`else
216 74 olivier.gi
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT;
217 2 olivier.gi
`endif
218
 
219
 
220
//=============================================================================
221
// 4)  UART RECEIVE / TRANSMIT
222
//=============================================================================
223
 
224
// Transfer counter
225
//------------------------
226 74 olivier.gi
reg                      [3:0] xfer_bit;
227
reg [`DBG_UART_XFER_CNT_W-1:0] xfer_cnt;
228 2 olivier.gi
 
229
wire       txd_start    = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
230
wire       rxd_start    = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC));
231 74 olivier.gi
wire       xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1'b0}});
232 2 olivier.gi
assign     xfer_done    = (xfer_bit==4'hb);
233
 
234 106 olivier.gi
always @ (posedge dbg_clk or posedge dbg_rst)
235
  if (dbg_rst)                       xfer_bit <=  4'h0;
236 2 olivier.gi
  else if (txd_start | rxd_start)    xfer_bit <=  4'h1;
237
  else if (xfer_done)                xfer_bit <=  4'h0;
238
  else if (xfer_bit_inc)             xfer_bit <=  xfer_bit+4'h1;
239
 
240 106 olivier.gi
always @ (posedge dbg_clk or posedge dbg_rst)
241
  if (dbg_rst)                       xfer_cnt <=  {`DBG_UART_XFER_CNT_W{1'b0}};
242 74 olivier.gi
  else if (rxd_start)                xfer_cnt <=  {1'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]};
243 2 olivier.gi
  else if (txd_start | xfer_bit_inc) xfer_cnt <=  bit_cnt_max;
244 74 olivier.gi
  else                               xfer_cnt <=  xfer_cnt+{`DBG_UART_XFER_CNT_W{1'b1}};
245 2 olivier.gi
 
246
 
247
// Receive/Transmit buffer
248
//-------------------------
249
wire [19:0] xfer_buf_nxt =  {rxd_s, xfer_buf[19:1]};
250
 
251 106 olivier.gi
always @ (posedge dbg_clk or posedge dbg_rst)
252
  if (dbg_rst)           xfer_buf <=  20'h00000;
253 2 olivier.gi
  else if (dbg_rd_rdy)   xfer_buf <=  {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
254
  else if (xfer_bit_inc) xfer_buf <=  xfer_buf_nxt;
255
 
256
 
257
// Generate TXD output
258
//------------------------
259
reg dbg_uart_txd;
260
 
261 106 olivier.gi
always @ (posedge dbg_clk or posedge dbg_rst)
262
  if (dbg_rst)                       dbg_uart_txd <=  1'b1;
263 2 olivier.gi
  else if (xfer_bit_inc & tx_active) dbg_uart_txd <=  xfer_buf[0];
264
 
265
 
266
//=============================================================================
267
// 5) INTERFACE TO DEBUG REGISTERS
268
//=============================================================================
269
 
270
reg [5:0] dbg_addr;
271 106 olivier.gi
 always @ (posedge dbg_clk or posedge dbg_rst)
272
  if (dbg_rst)        dbg_addr <=  6'h00;
273 2 olivier.gi
  else if (cmd_valid) dbg_addr <=  xfer_buf[`DBG_UART_ADDR];
274
 
275
reg       dbg_bw;
276 106 olivier.gi
always @ (posedge dbg_clk or posedge dbg_rst)
277
  if (dbg_rst)        dbg_bw   <=  1'b0;
278 2 olivier.gi
  else if (cmd_valid) dbg_bw   <=  xfer_buf[`DBG_UART_BW];
279
 
280
wire        dbg_din_bw =  mem_burst  ? mem_bw : dbg_bw;
281
 
282
wire [15:0] dbg_din    =  dbg_din_bw ? {8'h00,           xfer_buf[18:11]} :
283
                                       {xfer_buf[18:11], xfer_buf[8:1]};
284
wire        dbg_wr     = (xfer_done & (uart_state==RX_DATA2));
285
wire        dbg_rd     = mem_burst ? (xfer_done & (uart_state==TX_DATA2)) :
286
                                     (cmd_valid & ~xfer_buf[`DBG_UART_WR]) | mem_burst_rd;
287
 
288
 
289
 
290 34 olivier.gi
endmodule // omsp_dbg_uart
291 2 olivier.gi
 
292 103 olivier.gi
`ifdef OMSP_NO_INCLUDE
293
`else
294 33 olivier.gi
`include "openMSP430_undefines.v"
295 103 olivier.gi
`endif

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