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1 2 olivier.gi
//----------------------------------------------------------------------------
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// Copyright (C) 2009 , Olivier Girard
3 2 olivier.gi
//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//     * Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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//     * Redistributions in binary form must reproduce the above copyright
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//       notice, this list of conditions and the following disclaimer in the
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//       documentation and/or other materials provided with the distribution.
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//     * Neither the name of the authors nor the names of its contributors
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//       may be used to endorse or promote products derived from this software
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//       without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
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//
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//----------------------------------------------------------------------------
29
//
30 34 olivier.gi
// *File Name: omsp_sfr.v
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// 
32
// *Module Description:
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//                       Processor Special function register
34 134 olivier.gi
//                       Non-Maskable Interrupt generation
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
39
//----------------------------------------------------------------------------
40 17 olivier.gi
// $Rev: 134 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
43
//----------------------------------------------------------------------------
44 103 olivier.gi
`ifdef OMSP_NO_INCLUDE
45
`else
46 23 olivier.gi
`include "openMSP430_defines.v"
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`endif
48 2 olivier.gi
 
49 34 olivier.gi
module  omsp_sfr (
50 2 olivier.gi
 
51
// OUTPUTs
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    cpu_id,                       // CPU ID
53
    nmi_pnd,                      // NMI Pending
54
    nmi_wkup,                     // NMI Wakeup
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    per_dout,                     // Peripheral data output
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    wdtie,                        // Watchdog-timer interrupt enable
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    wdtifg_sw_clr,                // Watchdog-timer interrupt flag software clear
58
    wdtifg_sw_set,                // Watchdog-timer interrupt flag software set
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60
// INPUTs
61
    mclk,                         // Main system clock
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    nmi,                          // Non-maskable interrupt (asynchronous)
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    nmi_acc,                      // Non-Maskable interrupt request accepted
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    per_addr,                     // Peripheral address
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    per_din,                      // Peripheral data input
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    per_en,                       // Peripheral enable (high active)
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    per_we,                       // Peripheral write enable (high active)
68 111 olivier.gi
    puc_rst,                      // Main system reset
69 134 olivier.gi
    scan_mode,                    // Scan mode
70
    wdtifg,                       // Watchdog-timer interrupt flag
71
    wdtnmies                      // Watchdog-timer NMI edge selection
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);
73
 
74
// OUTPUTs
75
//=========
76 134 olivier.gi
output       [31:0] cpu_id;       // CPU ID
77
output              nmi_pnd;      // NMI Pending
78
output              nmi_wkup;     // NMI Wakeup
79 2 olivier.gi
output       [15:0] per_dout;     // Peripheral data output
80
output              wdtie;        // Watchdog-timer interrupt enable
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output              wdtifg_sw_clr;// Watchdog-timer interrupt flag software clear
82
output              wdtifg_sw_set;// Watchdog-timer interrupt flag software set
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84
// INPUTs
85
//=========
86
input               mclk;         // Main system clock
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input               nmi;          // Non-maskable interrupt (asynchronous)
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input               nmi_acc;      // Non-Maskable interrupt request accepted
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input        [13:0] per_addr;     // Peripheral address
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input        [15:0] per_din;      // Peripheral data input
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input               per_en;       // Peripheral enable (high active)
92 106 olivier.gi
input         [1:0] per_we;       // Peripheral write enable (high active)
93 111 olivier.gi
input               puc_rst;      // Main system reset
94 134 olivier.gi
input               scan_mode;    // Scan mode
95
input               wdtifg;       // Watchdog-timer interrupt flag
96
input               wdtnmies;     // Watchdog-timer NMI edge selection
97 2 olivier.gi
 
98
 
99
//=============================================================================
100
// 1)  PARAMETER DECLARATION
101
//=============================================================================
102
 
103 111 olivier.gi
// Register base address (must be aligned to decoder bit width)
104
parameter       [14:0] BASE_ADDR   = 15'h0000;
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106 111 olivier.gi
// Decoder bit width (defines how many bits are considered for address decoding)
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parameter              DEC_WD      =  3;
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109
// Register addresses offset
110
parameter [DEC_WD-1:0] IE1         =  'h0,
111 134 olivier.gi
                       IFG1        =  'h2,
112
                       CPU_ID_LO   =  'h4,
113
                       CPU_ID_HI   =  'h6;
114 111 olivier.gi
 
115
// Register one-hot decoder utilities
116 134 olivier.gi
parameter              DEC_SZ      =  (1 << DEC_WD);
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parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};
118
 
119 2 olivier.gi
// Register one-hot decoder
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parameter [DEC_SZ-1:0] IE1_D       = (BASE_REG << IE1),
121 134 olivier.gi
                       IFG1_D      = (BASE_REG << IFG1),
122
                       CPU_ID_LO_D = (BASE_REG << CPU_ID_LO),
123
                       CPU_ID_HI_D = (BASE_REG << CPU_ID_HI);
124 2 olivier.gi
 
125
 
126
//============================================================================
127
// 2)  REGISTER DECODER
128
//============================================================================
129
 
130 111 olivier.gi
// Local register selection
131
wire              reg_sel      =  per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
132
 
133
// Register local address
134
wire [DEC_WD-1:0] reg_addr     =  {1'b0, per_addr[DEC_WD-2:0]};
135
 
136 2 olivier.gi
// Register address decode
137 134 olivier.gi
wire [DEC_SZ-1:0] reg_dec      = (IE1_D        &  {DEC_SZ{(reg_addr==(IE1       >>1))}})  |
138
                                 (IFG1_D       &  {DEC_SZ{(reg_addr==(IFG1      >>1))}})  |
139
                                 (CPU_ID_LO_D  &  {DEC_SZ{(reg_addr==(CPU_ID_LO >>1))}})  |
140
                                 (CPU_ID_HI_D  &  {DEC_SZ{(reg_addr==(CPU_ID_HI >>1))}});
141 2 olivier.gi
 
142
// Read/Write probes
143 111 olivier.gi
wire              reg_lo_write =  per_we[0] & reg_sel;
144
wire              reg_hi_write =  per_we[1] & reg_sel;
145
wire              reg_read     = ~|per_we   & reg_sel;
146 2 olivier.gi
 
147
// Read/Write vectors
148 111 olivier.gi
wire [DEC_SZ-1:0] reg_hi_wr    = reg_dec & {DEC_SZ{reg_hi_write}};
149
wire [DEC_SZ-1:0] reg_lo_wr    = reg_dec & {DEC_SZ{reg_lo_write}};
150
wire [DEC_SZ-1:0] reg_rd       = reg_dec & {DEC_SZ{reg_read}};
151 2 olivier.gi
 
152
 
153
//============================================================================
154
// 3) REGISTERS
155
//============================================================================
156
 
157
// IE1 Register
158
//--------------
159
wire [7:0] ie1;
160 111 olivier.gi
wire       ie1_wr  = IE1[0] ? reg_hi_wr[IE1] : reg_lo_wr[IE1];
161
wire [7:0] ie1_nxt = IE1[0] ? per_din[15:8]  : per_din[7:0];
162 2 olivier.gi
 
163 134 olivier.gi
`ifdef NMI
164 2 olivier.gi
reg        nmie;
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always @ (posedge mclk or posedge puc_rst)
166
  if (puc_rst)      nmie  <=  1'b0;
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  else if (nmi_acc) nmie  <=  1'b0;
168
  else if (ie1_wr)  nmie  <=  ie1_nxt[4];
169 134 olivier.gi
`else
170
wire       nmie  =  1'b0;
171
`endif
172 2 olivier.gi
 
173 134 olivier.gi
`ifdef WATCHDOG
174 2 olivier.gi
reg        wdtie;
175 111 olivier.gi
always @ (posedge mclk or posedge puc_rst)
176
  if (puc_rst)      wdtie <=  1'b0;
177
  else if (ie1_wr)  wdtie <=  ie1_nxt[0];
178 134 olivier.gi
`else
179
wire       wdtie =  1'b0;
180
`endif
181 2 olivier.gi
 
182
assign  ie1 = {3'b000, nmie, 3'b000, wdtie};
183
 
184
 
185
// IFG1 Register
186
//---------------
187
wire [7:0] ifg1;
188 134 olivier.gi
 
189 111 olivier.gi
wire       ifg1_wr  = IFG1[0] ? reg_hi_wr[IFG1] : reg_lo_wr[IFG1];
190
wire [7:0] ifg1_nxt = IFG1[0] ? per_din[15:8]   : per_din[7:0];
191 2 olivier.gi
 
192 134 olivier.gi
`ifdef NMI
193 2 olivier.gi
reg        nmiifg;
194 134 olivier.gi
wire       nmi_edge;
195 111 olivier.gi
always @ (posedge mclk or posedge puc_rst)
196
  if (puc_rst)       nmiifg <=  1'b0;
197 134 olivier.gi
  else if (nmi_edge) nmiifg <=  1'b1;
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  else if (ifg1_wr)  nmiifg <=  ifg1_nxt[4];
199 134 olivier.gi
`else
200
wire       nmiifg = 1'b0;
201
`endif
202 2 olivier.gi
 
203 134 olivier.gi
`ifdef WATCHDOG
204
assign  wdtifg_sw_clr = ifg1_wr & ~ifg1_nxt[0];
205
assign  wdtifg_sw_set = ifg1_wr &  ifg1_nxt[0];
206
`else
207
assign  wdtifg_sw_clr = 1'b0;
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assign  wdtifg_sw_set = 1'b0;
209
`endif
210 2 olivier.gi
 
211
assign  ifg1 = {3'b000, nmiifg, 3'b000, wdtifg};
212
 
213
 
214 134 olivier.gi
// CPU_ID Register (READ ONLY)
215
//-----------------------------
216
//              -------------------------------------------------------------------
217
// CPU_ID_LO:  | 15  14  13  12  11  10  9  |  8  7  6  5  4  |  3   |   2  1  0   |
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//             |----------------------------+-----------------+------+-------------|
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//             |        PER_SPACE           |   USER_VERSION  | ASIC | CPU_VERSION |
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//              --------------------------------------------------------------------
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// CPU_ID_HI:  |   15  14  13  12  11  10   |   9  8  7  6  5  4  3  2  1   |   0  |
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//             |----------------------------+-------------------------------+------|
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//             |         PMEM_SIZE          |            DMEM_SIZE          |  MPY |
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//              -------------------------------------------------------------------
225
 
226
wire  [2:0] cpu_version  =  `CPU_VERSION;
227
`ifdef ASIC
228
wire        cpu_asic     =  1'b1;
229
`else
230
wire        cpu_asic     =  1'b0;
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`endif
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wire  [4:0] user_version =  `USER_VERSION;
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wire  [6:0] per_space    = (`PER_SIZE  >> 9);  // cpu_id_per  *  512 = peripheral space size
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`ifdef MULTIPLIER
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wire        mpy_info     =  1'b1;
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`else
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wire        mpy_info     =  1'b0;
238
`endif
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wire  [8:0] dmem_size    = (`DMEM_SIZE >> 7);  // cpu_id_dmem *  128 = data memory size
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wire  [5:0] pmem_size    = (`PMEM_SIZE >> 10); // cpu_id_pmem * 1024 = program memory size
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242
assign      cpu_id       = {pmem_size,
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                            dmem_size,
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                            mpy_info,
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                            per_space,
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                            user_version,
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                            cpu_asic,
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                            cpu_version};
249
 
250
 
251 2 olivier.gi
//============================================================================
252
// 4) DATA OUTPUT GENERATION
253
//============================================================================
254
 
255
// Data output mux
256 134 olivier.gi
wire [15:0] ie1_rd        = {8'h00, (ie1  &  {8{reg_rd[IE1]}})}  << (8 & {4{IE1[0]}});
257
wire [15:0] ifg1_rd       = {8'h00, (ifg1 &  {8{reg_rd[IFG1]}})} << (8 & {4{IFG1[0]}});
258
wire [15:0] cpu_id_lo_rd  = cpu_id[15:0]  & {16{reg_rd[CPU_ID_LO]}};
259
wire [15:0] cpu_id_hi_rd  = cpu_id[31:16] & {16{reg_rd[CPU_ID_HI]}};
260 2 olivier.gi
 
261 134 olivier.gi
wire [15:0] per_dout =  ie1_rd       |
262
                        ifg1_rd      |
263
                        cpu_id_lo_rd |
264
                        cpu_id_hi_rd;
265 2 olivier.gi
 
266
 
267
//=============================================================================
268 134 olivier.gi
// 5)  NMI GENERATION
269 2 olivier.gi
//=============================================================================
270 134 olivier.gi
// NOTE THAT THE NMI INPUT IS ASSUMED TO BE NON-GLITCHY
271
`ifdef NMI
272 2 olivier.gi
 
273 134 olivier.gi
//-----------------------------------
274
// Edge selection
275
//-----------------------------------
276
wire nmi_pol = nmi ^ wdtnmies;
277 2 olivier.gi
 
278 134 olivier.gi
//-----------------------------------
279
// Pulse capture and synchronization
280
//-----------------------------------
281
`ifdef SYNC_NMI
282
  `ifdef ASIC
283
   // Glitch free reset for the event capture
284
   reg    nmi_capture_rst;
285
   always @(posedge mclk or posedge puc_rst)
286
     if (puc_rst) nmi_capture_rst <= 1'b1;
287
     else         nmi_capture_rst <= ifg1_wr & ~ifg1_nxt[4];
288
 
289
   // NMI event capture
290
   wire   nmi_capture;
291
   omsp_wakeup_cell wakeup_cell_nmi (
292
                                     .wkup_out   (nmi_capture),     // Wakup signal (asynchronous)
293
                                     .scan_clk   (mclk),            // Scan clock
294
                                     .scan_mode  (scan_mode),       // Scan mode
295
                                     .scan_rst   (puc_rst),         // Scan reset
296
                                     .wkup_clear (nmi_capture_rst), // Glitch free wakeup event clear
297
                                     .wkup_event (nmi_pol)          // Glitch free asynchronous wakeup event
298
   );
299
  `else
300
   wire   nmi_capture = nmi_pol;
301
  `endif
302 2 olivier.gi
 
303 134 olivier.gi
   // Synchronization
304
   wire   nmi_s;
305
   omsp_sync_cell sync_cell_nmi (
306
       .data_out  (nmi_s),
307
       .data_in   (nmi_capture),
308
       .clk       (mclk),
309
       .rst       (puc_rst)
310
   );
311 2 olivier.gi
 
312 134 olivier.gi
`else
313
   wire   nmi_capture = nmi_pol;
314
   wire   nmi_s       = nmi_pol;
315
`endif
316 2 olivier.gi
 
317 134 olivier.gi
//-----------------------------------
318
// NMI Pending flag
319
//-----------------------------------
320
 
321
// Delay
322
reg  nmi_dly;
323
always @ (posedge mclk or posedge puc_rst)
324
  if (puc_rst) nmi_dly <= 1'b0;
325
  else         nmi_dly <= nmi_s;
326
 
327
// Edge detection
328
assign      nmi_edge  = ~nmi_dly & nmi_s;
329
 
330
// NMI pending
331
wire        nmi_pnd   = nmiifg & nmie;
332
 
333
// NMI wakeup
334
`ifdef ASIC
335
wire        nmi_wkup;
336
omsp_and_gate and_nmi_wkup (.y(nmi_wkup), .a(nmi_capture ^ nmi_dly), .b(nmie));
337
`else
338
wire        nmi_wkup  = 1'b0;
339
`endif
340
 
341
`else
342
 
343
wire        nmi_pnd   = 1'b0;
344
wire        nmi_wkup  = 1'b0;
345
 
346
`endif
347
 
348 34 olivier.gi
endmodule // omsp_sfr
349 33 olivier.gi
 
350 103 olivier.gi
`ifdef OMSP_NO_INCLUDE
351
`else
352 33 olivier.gi
`include "openMSP430_undefines.v"
353 103 olivier.gi
`endif

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