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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_watchdog.v] - Blame information for rev 34

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1 2 olivier.gi
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: omsp_watchdog.v
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// 
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// *Module Description:
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//                       Watchdog Timer
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 34 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Tue, 29 Dec 2009) $
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "openMSP430_defines.v"
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41 34 olivier.gi
module  omsp_watchdog (
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// OUTPUTs
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    nmi_evt,                        // NMI Event
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    per_dout,                       // Peripheral data output
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    wdtifg_set,                     // Set Watchdog-timer interrupt flag
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    wdtpw_error,                    // Watchdog-timer password error
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    wdttmsel,                       // Watchdog-timer mode select
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// INPUTs
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    aclk_en,                        // ACLK enable
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    dbg_freeze,                     // Freeze Watchdog counter
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    mclk,                           // Main system clock
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    nmi,                            // Non-maskable interrupt (asynchronous)
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    nmie,                           // Non-maskable interrupt enable
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    per_addr,                       // Peripheral address
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    per_din,                        // Peripheral data input
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    per_en,                         // Peripheral enable (high active)
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    per_wen,                        // Peripheral write enable (high active)
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    puc,                            // Main system reset
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    smclk_en,                       // SMCLK enable
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    wdtie                           // Watchdog timer interrupt enable
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);
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// OUTPUTs
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//=========
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output              nmi_evt;        // NMI Event
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output       [15:0] per_dout;       // Peripheral data output
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output              wdtifg_set;     // Set Watchdog-timer interrupt flag
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output              wdtpw_error;    // Watchdog-timer password error
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output              wdttmsel;       // Watchdog-timer mode select
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// INPUTs
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//=========
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input               aclk_en;        // ACLK enable
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input               dbg_freeze;     // Freeze Watchdog counter
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input               mclk;           // Main system clock
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input               nmi;            // Non-maskable interrupt (asynchronous)
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input               nmie;           // Non-maskable interrupt enable
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input         [7:0] per_addr;       // Peripheral address
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input        [15:0] per_din;        // Peripheral data input
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input               per_en;         // Peripheral enable (high active)
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input         [1:0] per_wen;        // Peripheral write enable (high active)
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input               puc;            // Main system reset
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input               smclk_en;       // SMCLK enable
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input               wdtie;          // Watchdog timer interrupt enable
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//=============================================================================
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// 1)  PARAMETER DECLARATION
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//=============================================================================
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// Register addresses
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parameter           WDTCTL     = 9'h120;
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// Register one-hot decoder
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parameter           WDTCTL_D   = (512'h1 << WDTCTL);
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//============================================================================
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// 2)  REGISTER DECODER
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//============================================================================
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// Register address decode
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reg  [511:0]  reg_dec;
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always @(per_addr)
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  case ({per_addr,1'b0})
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    WDTCTL :     reg_dec  =  WDTCTL_D;
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    default:     reg_dec  =  {512{1'b0}};
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  endcase
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// Read/Write probes
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wire reg_write =  |per_wen   & per_en;
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wire reg_read  = ~|per_wen   & per_en;
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// Read/Write vectors
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wire [511:0] reg_wr    = reg_dec & {512{reg_write}};
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wire [511:0] reg_rd    = reg_dec & {512{reg_read}};
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//============================================================================
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// 3) REGISTERS
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//============================================================================
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// WDTCTL Register
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//-----------------
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// WDTNMI & WDTSSEL are not implemented and therefore masked
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reg  [7:0] wdtctl;
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wire       wdtctl_wr = reg_wr[WDTCTL];
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always @ (posedge mclk or posedge puc)
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  if (puc)            wdtctl <=  8'h00;
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  else if (wdtctl_wr) wdtctl <=  per_din[7:0] & 8'hd7;
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wire       wdtpw_error = wdtctl_wr & (per_din[15:8]!=8'h5a);
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wire       wdttmsel    = wdtctl[4];
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//============================================================================
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// 3) REGISTERS
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//============================================================================
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// Data output mux
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wire [15:0] wdtctl_rd  = {8'h69, wdtctl}  & {16{reg_rd[WDTCTL]}};
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wire [15:0] per_dout   =  wdtctl_rd;
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//=============================================================================
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// 4)  NMI GENERATION
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//=============================================================================
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// Synchronization state
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reg [2:0] nmi_sync;
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always @ (posedge mclk or posedge puc)
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  if (puc)  nmi_sync <= 3'h0;
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  else      nmi_sync <= {nmi_sync[1:0], nmi};
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// Edge detection
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wire        nmi_re    = ~nmi_sync[2] &  nmi_sync[0] & nmie;
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wire        nmi_fe    =  nmi_sync[2] & ~nmi_sync[0] & nmie;
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// NMI event
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wire        nmi_evt   = wdtctl[6] ? nmi_fe : nmi_re;
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//=============================================================================
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// 5)  WATCHDOG TIMER
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//=============================================================================
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// Watchdog clock source selection
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//---------------------------------
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wire  clk_src_en = wdtctl[2] ? aclk_en : smclk_en;
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// Watchdog 16 bit counter
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//--------------------------
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reg [15:0] wdtcnt;
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wire       wdtcnt_clr = (wdtctl_wr & per_din[3]) | wdtifg_set;
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always @ (posedge mclk or posedge puc)
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  if (puc)                                        wdtcnt <= 16'h0000;
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  else if (wdtcnt_clr)                            wdtcnt <= 16'h0000;
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  else if (~wdtctl[7] & clk_src_en & ~dbg_freeze) wdtcnt <= wdtcnt+16'h0001;
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// Interval selection mux
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//--------------------------
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reg        wdtqn;
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always @(wdtctl or wdtcnt)
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    case(wdtctl[1:0])
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      2'b00  : wdtqn =  wdtcnt[15];
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      2'b01  : wdtqn =  wdtcnt[13];
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      2'b10  : wdtqn =  wdtcnt[9];
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      default: wdtqn =  wdtcnt[6];
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    endcase
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// Watchdog event detection
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//-----------------------------
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reg        wdtqn_dly;
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always @ (posedge mclk or posedge puc)
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  if (puc) wdtqn_dly <= 1'b0;
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  else     wdtqn_dly <= wdtqn;
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wire       wdtifg_set =  (~wdtqn_dly & wdtqn) | wdtpw_error;
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215 34 olivier.gi
endmodule // omsp_watchdog
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217 33 olivier.gi
`include "openMSP430_undefines.v"

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