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//----------------------------------------------------------------------------
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// Copyright (C) 2009 , Olivier Girard
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the authors nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: openMSP430.v
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//
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// *Module Description:
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// openMSP430 Top level file
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 117 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-06-23 21:30:51 +0200 (Thu, 23 Jun 2011) $
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`else
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`include "openMSP430_defines.v"
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`endif
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module openMSP430 (
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// OUTPUTs
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aclk_en, // ACLK enable
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dbg_freeze, // Freeze peripherals
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dbg_uart_txd, // Debug interface: UART TXD
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dmem_addr, // Data Memory address
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dmem_cen, // Data Memory chip enable (low active)
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dmem_din, // Data Memory data input
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dmem_wen, // Data Memory write enable (low active)
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irq_acc, // Interrupt request accepted (one-hot signal)
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mclk, // Main system clock
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_we, // Peripheral write enable (high active)
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per_en, // Peripheral enable (high active)
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pmem_addr, // Program Memory address
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pmem_cen, // Program Memory chip enable (low active)
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pmem_din, // Program Memory data input (optional)
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pmem_wen, // Program Memory write enable (low active) (optional)
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puc_rst, // Main system reset
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smclk_en, // SMCLK enable
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// INPUTs
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cpu_en, // Enable CPU code execution (asynchronous)
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dbg_en, // Debug interface enable (asynchronous)
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dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
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dco_clk, // Fast oscillator (fast clock)
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dmem_dout, // Data Memory data output
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irq, // Maskable interrupts
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lfxt_clk, // Low frequency oscillator (typ 32kHz)
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nmi, // Non-maskable interrupt (asynchronous)
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per_dout, // Peripheral data output
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pmem_dout, // Program Memory data output
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reset_n // Reset Pin (low active, asynchronous)
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);
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// OUTPUTs
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//=========
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output aclk_en; // ACLK enable
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output dbg_freeze; // Freeze peripherals
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output dbg_uart_txd; // Debug interface: UART TXD
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output [`DMEM_MSB:0] dmem_addr; // Data Memory address
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output dmem_cen; // Data Memory chip enable (low active)
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output [15:0] dmem_din; // Data Memory data input
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output [1:0] dmem_wen; // Data Memory write enable (low active)
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output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
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output mclk; // Main system clock
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output [13:0] per_addr; // Peripheral address
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output [15:0] per_din; // Peripheral data input
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output [1:0] per_we; // Peripheral write enable (high active)
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output per_en; // Peripheral enable (high active)
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output [`PMEM_MSB:0] pmem_addr; // Program Memory address
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output pmem_cen; // Program Memory chip enable (low active)
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output [15:0] pmem_din; // Program Memory data input (optional)
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output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
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output puc_rst; // Main system reset
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output smclk_en; // SMCLK enable
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// INPUTs
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//=========
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input cpu_en; // Enable CPU code execution (asynchronous)
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input dbg_en; // Debug interface enable (asynchronous)
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input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
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input dco_clk; // Fast oscillator (fast clock)
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input [15:0] dmem_dout; // Data Memory data output
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input [13:0] irq; // Maskable interrupts
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input lfxt_clk; // Low frequency oscillator (typ 32kHz)
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input nmi; // Non-maskable interrupt (asynchronous)
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input [15:0] per_dout; // Peripheral data output
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input [15:0] pmem_dout; // Program Memory data output
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input reset_n; // Reset Pin (active low, asynchronous)
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//=============================================================================
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// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
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//=============================================================================
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wire [7:0] inst_ad;
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wire [7:0] inst_as;
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wire [11:0] inst_alu;
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wire inst_bw;
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wire inst_irq_rst;
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wire inst_mov;
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wire [15:0] inst_dest;
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wire [15:0] inst_dext;
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wire [15:0] inst_sext;
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wire [7:0] inst_so;
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wire [15:0] inst_src;
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wire [2:0] inst_type;
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wire [7:0] inst_jmp;
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wire [3:0] e_state;
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wire exec_done;
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wire decode_noirq;
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wire cpu_en_s;
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wire cpuoff;
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wire oscoff;
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wire scg1;
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wire por;
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wire gie;
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wire [15:0] eu_mab;
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wire [15:0] eu_mdb_in;
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wire [15:0] eu_mdb_out;
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wire [1:0] eu_mb_wr;
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wire eu_mb_en;
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wire [15:0] fe_mab;
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wire [15:0] fe_mdb_in;
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wire fe_mb_en;
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wire fe_pmem_wait;
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wire pc_sw_wr;
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wire [15:0] pc_sw;
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wire [15:0] pc;
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wire [15:0] pc_nxt;
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wire nmie;
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wire nmi_acc;
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wire nmi_evt;
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wire wdtie;
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wire wdtifg_set;
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wire wdtpw_error;
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wire wdttmsel;
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wire wdt_irq;
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wire wdt_reset;
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wire dbg_clk;
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wire dbg_rst;
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wire dbg_en_s;
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wire dbg_halt_st;
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wire dbg_halt_cmd;
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wire dbg_mem_en;
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wire dbg_reg_wr;
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wire dbg_cpu_reset;
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wire [15:0] dbg_mem_addr;
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wire [15:0] dbg_mem_dout;
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wire [15:0] dbg_mem_din;
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wire [15:0] dbg_reg_din;
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wire [1:0] dbg_mem_wr;
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wire [15:0] per_dout_or;
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wire [15:0] per_dout_sfr;
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wire [15:0] per_dout_wdog;
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wire [15:0] per_dout_mpy;
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wire [15:0] per_dout_clk;
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//=============================================================================
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// 2) GLOBAL CLOCK & RESET MANAGEMENT
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//=============================================================================
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omsp_clock_module clock_module_0 (
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// OUTPUTs
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.aclk_en (aclk_en), // ACLK enablex
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.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
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.dbg_clk (dbg_clk), // Debug unit clock
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.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
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.dbg_rst (dbg_rst), // Debug unit reset
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.mclk (mclk), // Main system clock
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.per_dout (per_dout_clk), // Peripheral data output
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.por (por), // Power-on reset
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.puc_rst (puc_rst), // Main system reset
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.smclk_en (smclk_en), // SMCLK enable
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// INPUTs
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.cpu_en (cpu_en), // Enable CPU code execution (asynchronous)
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.dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
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.dbg_en (dbg_en), // Debug interface enable (asynchronous)
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
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.oscoff (oscoff), // Turns off LFXT1 clock input
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.reset_n (reset_n), // Reset Pin (low active, asynchronous)
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.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
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.wdt_reset (wdt_reset) // Watchdog-timer reset
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//=============================================================================
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// 3) FRONTEND (<=> FETCH & DECODE)
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//=============================================================================
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olivier.gi |
omsp_frontend frontend_0 (
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// OUTPUTs
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.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
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.decode_noirq (decode_noirq), // Frontend decode instruction
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.e_state (e_state), // Execution state
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.exec_done (exec_done), // Execution completed
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.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
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.inst_as (inst_as), // Decoded Inst: source addressing mode
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.inst_alu (inst_alu), // ALU control signals
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.inst_bw (inst_bw), // Decoded Inst: byte width
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.inst_dest (inst_dest), // Decoded Inst: destination (one hot)
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.inst_dext (inst_dext), // Decoded Inst: destination extended instruction word
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.inst_irq_rst (inst_irq_rst), // Decoded Inst: Reset interrupt
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.inst_jmp (inst_jmp), // Decoded Inst: Conditional jump
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.inst_mov (inst_mov), // Decoded Inst: mov instruction
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.inst_sext (inst_sext), // Decoded Inst: source extended instruction word
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.inst_so (inst_so), // Decoded Inst: Single-operand arithmetic
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.inst_src (inst_src), // Decoded Inst: source (one hot)
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.inst_type (inst_type), // Decoded Instruction type
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.irq_acc (irq_acc), // Interrupt request accepted
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.mab (fe_mab), // Frontend Memory address bus
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.mb_en (fe_mb_en), // Frontend Memory bus enable
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.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
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.pc (pc), // Program counter
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.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
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// INPUTs
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.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
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olivier.gi |
.cpuoff (cpuoff), // Turns off the CPU
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.dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
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.dbg_reg_sel (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
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.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
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2 |
olivier.gi |
.gie (gie), // General interrupt enable
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.irq (irq), // Maskable interrupts
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.mclk (mclk), // Main system clock
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.mdb_in (fe_mdb_in), // Frontend Memory data bus input
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.nmi_evt (nmi_evt), // Non-maskable interrupt event
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.pc_sw (pc_sw), // Program counter software value
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.pc_sw_wr (pc_sw_wr), // Program counter software write
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.puc_rst (puc_rst), // Main system reset
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2 |
olivier.gi |
.wdt_irq (wdt_irq) // Watchdog-timer interrupt
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);
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//=============================================================================
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// 4) EXECUTION UNIT
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//=============================================================================
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34 |
olivier.gi |
omsp_execution_unit execution_unit_0 (
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2 |
olivier.gi |
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// OUTPUTs
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.cpuoff (cpuoff), // Turns off the CPU
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.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
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.mab (eu_mab), // Memory address bus
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.mb_en (eu_mb_en), // Memory bus enable
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.mb_wr (eu_mb_wr), // Memory bus write transfer
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.mdb_out (eu_mdb_out), // Memory data bus output
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.oscoff (oscoff), // Turns off LFXT1 clock input
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.pc_sw (pc_sw), // Program counter software value
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.pc_sw_wr (pc_sw_wr), // Program counter software write
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.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
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// INPUTs
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.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
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.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
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.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
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.e_state (e_state), // Execution state
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305 |
|
|
.exec_done (exec_done), // Execution completed
|
306 |
|
|
.gie (gie), // General interrupt enable
|
307 |
|
|
.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
|
308 |
|
|
.inst_as (inst_as), // Decoded Inst: source addressing mode
|
309 |
|
|
.inst_alu (inst_alu), // ALU control signals
|
310 |
|
|
.inst_bw (inst_bw), // Decoded Inst: byte width
|
311 |
|
|
.inst_dest (inst_dest), // Decoded Inst: destination (one hot)
|
312 |
|
|
.inst_dext (inst_dext), // Decoded Inst: destination extended instruction word
|
313 |
|
|
.inst_irq_rst (inst_irq_rst), // Decoded Inst: reset interrupt
|
314 |
|
|
.inst_jmp (inst_jmp), // Decoded Inst: Conditional jump
|
315 |
105 |
olivier.gi |
.inst_mov (inst_mov), // Decoded Inst: mov instruction
|
316 |
2 |
olivier.gi |
.inst_sext (inst_sext), // Decoded Inst: source extended instruction word
|
317 |
|
|
.inst_so (inst_so), // Decoded Inst: Single-operand arithmetic
|
318 |
|
|
.inst_src (inst_src), // Decoded Inst: source (one hot)
|
319 |
|
|
.inst_type (inst_type), // Decoded Instruction type
|
320 |
|
|
.mclk (mclk), // Main system clock
|
321 |
|
|
.mdb_in (eu_mdb_in), // Memory data bus input
|
322 |
|
|
.pc (pc), // Program counter
|
323 |
|
|
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
|
324 |
111 |
olivier.gi |
.puc_rst (puc_rst) // Main system reset
|
325 |
2 |
olivier.gi |
);
|
326 |
|
|
|
327 |
|
|
|
328 |
|
|
//=============================================================================
|
329 |
|
|
// 5) MEMORY BACKBONE
|
330 |
|
|
//=============================================================================
|
331 |
|
|
|
332 |
34 |
olivier.gi |
omsp_mem_backbone mem_backbone_0 (
|
333 |
2 |
olivier.gi |
|
334 |
|
|
// OUTPUTs
|
335 |
|
|
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
|
336 |
33 |
olivier.gi |
.dmem_addr (dmem_addr), // Data Memory address
|
337 |
|
|
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
|
338 |
|
|
.dmem_din (dmem_din), // Data Memory data input
|
339 |
|
|
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
|
340 |
2 |
olivier.gi |
.eu_mdb_in (eu_mdb_in), // Execution Unit Memory data bus input
|
341 |
|
|
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
342 |
33 |
olivier.gi |
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
|
343 |
2 |
olivier.gi |
.per_addr (per_addr), // Peripheral address
|
344 |
|
|
.per_din (per_din), // Peripheral data input
|
345 |
106 |
olivier.gi |
.per_we (per_we), // Peripheral write enable (high active)
|
346 |
2 |
olivier.gi |
.per_en (per_en), // Peripheral enable (high active)
|
347 |
33 |
olivier.gi |
.pmem_addr (pmem_addr), // Program Memory address
|
348 |
|
|
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
|
349 |
|
|
.pmem_din (pmem_din), // Program Memory data input (optional)
|
350 |
|
|
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
|
351 |
2 |
olivier.gi |
|
352 |
|
|
// INPUTs
|
353 |
|
|
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
|
354 |
|
|
.dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access
|
355 |
|
|
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
|
356 |
|
|
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
|
357 |
|
|
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
|
358 |
33 |
olivier.gi |
.dmem_dout (dmem_dout), // Data Memory data output
|
359 |
2 |
olivier.gi |
.eu_mab (eu_mab[15:1]), // Execution Unit Memory address bus
|
360 |
|
|
.eu_mb_en (eu_mb_en), // Execution Unit Memory bus enable
|
361 |
|
|
.eu_mb_wr (eu_mb_wr), // Execution Unit Memory bus write transfer
|
362 |
|
|
.eu_mdb_out (eu_mdb_out), // Execution Unit Memory data bus output
|
363 |
|
|
.fe_mab (fe_mab[15:1]), // Frontend Memory address bus
|
364 |
|
|
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
365 |
|
|
.mclk (mclk), // Main system clock
|
366 |
|
|
.per_dout (per_dout_or), // Peripheral data output
|
367 |
33 |
olivier.gi |
.pmem_dout (pmem_dout), // Program Memory data output
|
368 |
111 |
olivier.gi |
.puc_rst (puc_rst) // Main system reset
|
369 |
2 |
olivier.gi |
);
|
370 |
|
|
|
371 |
|
|
|
372 |
|
|
//=============================================================================
|
373 |
|
|
// 6) SPECIAL FUNCTION REGISTERS
|
374 |
|
|
//=============================================================================
|
375 |
|
|
|
376 |
34 |
olivier.gi |
omsp_sfr sfr_0 (
|
377 |
2 |
olivier.gi |
|
378 |
|
|
// OUTPUTs
|
379 |
|
|
.nmie (nmie), // Non-maskable interrupt enable
|
380 |
|
|
.per_dout (per_dout_sfr), // Peripheral data output
|
381 |
|
|
.wdt_irq (wdt_irq), // Watchdog-timer interrupt
|
382 |
|
|
.wdt_reset (wdt_reset), // Watchdog-timer reset
|
383 |
|
|
.wdtie (wdtie), // Watchdog-timer interrupt enable
|
384 |
|
|
|
385 |
|
|
// INPUTs
|
386 |
|
|
.mclk (mclk), // Main system clock
|
387 |
|
|
.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
|
388 |
|
|
.per_addr (per_addr), // Peripheral address
|
389 |
|
|
.per_din (per_din), // Peripheral data input
|
390 |
|
|
.per_en (per_en), // Peripheral enable (high active)
|
391 |
106 |
olivier.gi |
.per_we (per_we), // Peripheral write enable (high active)
|
392 |
2 |
olivier.gi |
.por (por), // Power-on reset
|
393 |
111 |
olivier.gi |
.puc_rst (puc_rst), // Main system reset
|
394 |
2 |
olivier.gi |
.wdtifg_clr (irq_acc[10]), // Clear Watchdog-timer interrupt flag
|
395 |
|
|
.wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag
|
396 |
|
|
.wdtpw_error (wdtpw_error), // Watchdog-timer password error
|
397 |
|
|
.wdttmsel (wdttmsel) // Watchdog-timer mode select
|
398 |
|
|
);
|
399 |
|
|
|
400 |
|
|
|
401 |
|
|
//=============================================================================
|
402 |
|
|
// 7) WATCHDOG TIMER
|
403 |
|
|
//=============================================================================
|
404 |
|
|
|
405 |
34 |
olivier.gi |
omsp_watchdog watchdog_0 (
|
406 |
2 |
olivier.gi |
|
407 |
|
|
// OUTPUTs
|
408 |
|
|
.nmi_evt (nmi_evt), // NMI Event
|
409 |
|
|
.per_dout (per_dout_wdog), // Peripheral data output
|
410 |
|
|
.wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag
|
411 |
|
|
.wdtpw_error (wdtpw_error), // Watchdog-timer password error
|
412 |
|
|
.wdttmsel (wdttmsel), // Watchdog-timer mode select
|
413 |
|
|
|
414 |
|
|
// INPUTs
|
415 |
|
|
.aclk_en (aclk_en), // ACLK enable
|
416 |
|
|
.dbg_freeze (dbg_freeze), // Freeze Watchdog counter
|
417 |
|
|
.mclk (mclk), // Main system clock
|
418 |
|
|
.nmi (nmi), // Non-maskable interrupt (asynchronous)
|
419 |
|
|
.nmie (nmie), // Non-maskable interrupt enable
|
420 |
|
|
.per_addr (per_addr), // Peripheral address
|
421 |
|
|
.per_din (per_din), // Peripheral data input
|
422 |
|
|
.per_en (per_en), // Peripheral enable (high active)
|
423 |
106 |
olivier.gi |
.per_we (per_we), // Peripheral write enable (high active)
|
424 |
111 |
olivier.gi |
.puc_rst (puc_rst), // Main system reset
|
425 |
2 |
olivier.gi |
.smclk_en (smclk_en), // SMCLK enable
|
426 |
|
|
.wdtie (wdtie) // Watchdog-timer interrupt enable
|
427 |
|
|
);
|
428 |
|
|
|
429 |
|
|
|
430 |
|
|
//=============================================================================
|
431 |
67 |
olivier.gi |
// 8) HARDWARE MULTIPLIER
|
432 |
2 |
olivier.gi |
//=============================================================================
|
433 |
67 |
olivier.gi |
`ifdef MULTIPLIER
|
434 |
|
|
omsp_multiplier multiplier_0 (
|
435 |
2 |
olivier.gi |
|
436 |
67 |
olivier.gi |
// OUTPUTs
|
437 |
|
|
.per_dout (per_dout_mpy), // Peripheral data output
|
438 |
|
|
|
439 |
|
|
// INPUTs
|
440 |
|
|
.mclk (mclk), // Main system clock
|
441 |
|
|
.per_addr (per_addr), // Peripheral address
|
442 |
|
|
.per_din (per_din), // Peripheral data input
|
443 |
|
|
.per_en (per_en), // Peripheral enable (high active)
|
444 |
106 |
olivier.gi |
.per_we (per_we), // Peripheral write enable (high active)
|
445 |
111 |
olivier.gi |
.puc_rst (puc_rst) // Main system reset
|
446 |
67 |
olivier.gi |
);
|
447 |
|
|
`else
|
448 |
|
|
assign per_dout_mpy = 16'h0000;
|
449 |
|
|
`endif
|
450 |
|
|
|
451 |
|
|
//=============================================================================
|
452 |
|
|
// 9) PERIPHERALS' OUTPUT BUS
|
453 |
|
|
//=============================================================================
|
454 |
|
|
|
455 |
2 |
olivier.gi |
assign per_dout_or = per_dout |
|
456 |
|
|
per_dout_clk |
|
457 |
|
|
per_dout_sfr |
|
458 |
67 |
olivier.gi |
per_dout_wdog |
|
459 |
|
|
per_dout_mpy;
|
460 |
2 |
olivier.gi |
|
461 |
|
|
|
462 |
|
|
//=============================================================================
|
463 |
67 |
olivier.gi |
// 10) DEBUG INTERFACE
|
464 |
2 |
olivier.gi |
//=============================================================================
|
465 |
|
|
|
466 |
|
|
`ifdef DBG_EN
|
467 |
34 |
olivier.gi |
omsp_dbg dbg_0 (
|
468 |
2 |
olivier.gi |
|
469 |
|
|
// OUTPUTs
|
470 |
|
|
.dbg_freeze (dbg_freeze), // Freeze peripherals
|
471 |
|
|
.dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
|
472 |
|
|
.dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access
|
473 |
|
|
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
|
474 |
|
|
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
|
475 |
|
|
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
|
476 |
|
|
.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
|
477 |
106 |
olivier.gi |
.dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
|
478 |
2 |
olivier.gi |
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
|
479 |
|
|
|
480 |
|
|
// INPUTs
|
481 |
106 |
olivier.gi |
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
|
482 |
|
|
.dbg_clk (dbg_clk), // Debug unit clock
|
483 |
|
|
.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
|
484 |
2 |
olivier.gi |
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
|
485 |
|
|
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
|
486 |
|
|
.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
|
487 |
106 |
olivier.gi |
.dbg_rst (dbg_rst), // Debug unit reset
|
488 |
|
|
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
|
489 |
53 |
olivier.gi |
.decode_noirq (decode_noirq), // Frontend decode instruction
|
490 |
2 |
olivier.gi |
.eu_mab (eu_mab), // Execution-Unit Memory address bus
|
491 |
|
|
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
|
492 |
|
|
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
|
493 |
|
|
.eu_mdb_in (eu_mdb_in), // Memory data bus input
|
494 |
|
|
.eu_mdb_out (eu_mdb_out), // Memory data bus output
|
495 |
|
|
.exec_done (exec_done), // Execution completed
|
496 |
|
|
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
497 |
|
|
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
498 |
|
|
.pc (pc), // Program counter
|
499 |
111 |
olivier.gi |
.puc_rst (puc_rst) // Main system reset
|
500 |
2 |
olivier.gi |
);
|
501 |
|
|
|
502 |
|
|
`else
|
503 |
106 |
olivier.gi |
assign dbg_freeze = ~cpu_en_s;
|
504 |
|
|
assign dbg_halt_cmd = 1'b0;
|
505 |
|
|
assign dbg_mem_addr = 16'h0000;
|
506 |
|
|
assign dbg_mem_dout = 16'h0000;
|
507 |
|
|
assign dbg_mem_en = 1'b0;
|
508 |
|
|
assign dbg_mem_wr = 2'b00;
|
509 |
|
|
assign dbg_reg_wr = 1'b0;
|
510 |
|
|
assign dbg_cpu_reset = 1'b0;
|
511 |
|
|
assign dbg_uart_txd = 1'b0;
|
512 |
2 |
olivier.gi |
`endif
|
513 |
|
|
|
514 |
|
|
|
515 |
|
|
endmodule // openMSP430
|
516 |
|
|
|
517 |
103 |
olivier.gi |
`ifdef OMSP_NO_INCLUDE
|
518 |
|
|
`else
|
519 |
33 |
olivier.gi |
`include "openMSP430_undefines.v"
|
520 |
103 |
olivier.gi |
`endif
|