OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [openMSP430.v] - Blame information for rev 33

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi
//----------------------------------------------------------------------------
2
// Copyright (C) 2001 Authors
3
//
4
// This source file may be used and distributed without restriction provided
5
// that this copyright statement is not removed from the file and that any
6
// derivative work contains the original copyright notice and the associated
7
// disclaimer.
8
//
9
// This source file is free software; you can redistribute it and/or modify
10
// it under the terms of the GNU Lesser General Public License as published
11
// by the Free Software Foundation; either version 2.1 of the License, or
12
// (at your option) any later version.
13
//
14
// This source is distributed in the hope that it will be useful, but WITHOUT
15
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
17
// License for more details.
18
//
19
// You should have received a copy of the GNU Lesser General Public License
20
// along with this source; if not, write to the Free Software Foundation,
21
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
22
//
23
//----------------------------------------------------------------------------
24
//
25
// *File Name: openMSP430.v
26
// 
27
// *Module Description:
28
//                       openMSP430 Top level file
29
//
30
// *Author(s):
31
//              - Olivier Girard,    olgirard@gmail.com
32
//
33
//----------------------------------------------------------------------------
34 17 olivier.gi
// $Rev: 33 $
35
// $LastChangedBy: olivier.girard $
36
// $LastChangedDate: 2009-12-29 19:18:00 +0100 (Tue, 29 Dec 2009) $
37
//----------------------------------------------------------------------------
38 23 olivier.gi
`include "timescale.v"
39
`include "openMSP430_defines.v"
40 2 olivier.gi
 
41
module  openMSP430 (
42
 
43
// OUTPUTs
44 33 olivier.gi
    aclk_en,                       // ACLK enable
45
    dbg_freeze,                    // Freeze peripherals
46
    dbg_uart_txd,                  // Debug interface: UART TXD
47
    dmem_addr,                     // Data Memory address
48
    dmem_cen,                      // Data Memory chip enable (low active)
49
    dmem_din,                      // Data Memory data input
50
    dmem_wen,                      // Data Memory write enable (low active)
51
    irq_acc,                       // Interrupt request accepted (one-hot signal)
52
    mclk,                          // Main system clock
53
    per_addr,                      // Peripheral address
54
    per_din,                       // Peripheral data input
55
    per_wen,                       // Peripheral write enable (high active)
56
    per_en,                        // Peripheral enable (high active)
57
    pmem_addr,                     // Program Memory address
58
    pmem_cen,                      // Program Memory chip enable (low active)
59
    pmem_din,                      // Program Memory data input (optional)
60
    pmem_wen,                      // Program Memory write enable (low active) (optional)
61
    puc,                           // Main system reset
62
    smclk_en,                      // SMCLK enable
63 2 olivier.gi
 
64
// INPUTs
65 33 olivier.gi
    dbg_uart_rxd,                  // Debug interface: UART RXD
66
    dco_clk,                       // Fast oscillator (fast clock)
67
    dmem_dout,                     // Data Memory data output
68
    irq,                           // Maskable interrupts
69
    lfxt_clk,                      // Low frequency oscillator (typ 32kHz)
70
    nmi,                           // Non-maskable interrupt (asynchronous)
71
    per_dout,                      // Peripheral data output
72
    pmem_dout,                     // Program Memory data output
73
    reset_n                        // Reset Pin (low active)
74 2 olivier.gi
);
75
 
76
// OUTPUTs
77
//=========
78 33 olivier.gi
output               aclk_en;      // ACLK enable
79
output               dbg_freeze;   // Freeze peripherals
80
output               dbg_uart_txd; // Debug interface: UART TXD
81
output [`DMEM_MSB:0] dmem_addr;    // Data Memory address
82
output               dmem_cen;     // Data Memory chip enable (low active)
83
output        [15:0] dmem_din;     // Data Memory data input
84
output         [1:0] dmem_wen;     // Data Memory write enable (low active)
85
output        [13:0] irq_acc;      // Interrupt request accepted (one-hot signal)
86
output               mclk;         // Main system clock
87
output         [7:0] per_addr;     // Peripheral address
88
output        [15:0] per_din;      // Peripheral data input
89
output         [1:0] per_wen;      // Peripheral write enable (high active)
90
output               per_en;       // Peripheral enable (high active)
91
output [`PMEM_MSB:0] pmem_addr;    // Program Memory address
92
output               pmem_cen;     // Program Memory chip enable (low active)
93
output        [15:0] pmem_din;     // Program Memory data input (optional)
94
output         [1:0] pmem_wen;     // Program Memory write enable (low active) (optional)
95
output               puc;          // Main system reset
96
output               smclk_en;     // SMCLK enable
97 2 olivier.gi
 
98
 
99
// INPUTs
100
//=========
101 33 olivier.gi
input                dbg_uart_rxd; // Debug interface: UART RXD
102
input                dco_clk;      // Fast oscillator (fast clock)
103
input         [15:0] dmem_dout;    // Data Memory data output
104
input         [13:0] irq;          // Maskable interrupts
105
input                lfxt_clk;     // Low frequency oscillator (typ 32kHz)
106
input                nmi;          // Non-maskable interrupt (asynchronous)
107
input         [15:0] per_dout;     // Peripheral data output
108
input         [15:0] pmem_dout;    // Program Memory data output
109
input                reset_n;      // Reset Pin (active low)
110 2 olivier.gi
 
111
 
112
 
113
//=============================================================================
114
// 1)  INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
115
//=============================================================================
116
 
117
wire          [7:0] inst_ad;
118
wire          [7:0] inst_as;
119
wire         [11:0] inst_alu;
120
wire                inst_bw;
121
wire         [15:0] inst_dest;
122
wire         [15:0] inst_dext;
123
wire         [15:0] inst_sext;
124
wire          [7:0] inst_so;
125
wire         [15:0] inst_src;
126
wire          [2:0] inst_type;
127
wire          [3:0] e_state;
128
wire                exec_done;
129
 
130
wire         [15:0] eu_mab;
131
wire         [15:0] eu_mdb_in;
132
wire         [15:0] eu_mdb_out;
133
wire          [1:0] eu_mb_wr;
134
wire         [15:0] fe_mab;
135
wire         [15:0] fe_mdb_in;
136
 
137
wire         [15:0] pc_sw;
138
wire          [7:0] inst_jmp;
139
wire         [15:0] pc;
140
wire         [15:0] pc_nxt;
141
 
142
wire         [15:0] dbg_mem_addr;
143
wire         [15:0] dbg_mem_dout;
144
wire         [15:0] dbg_mem_din;
145
wire         [15:0] dbg_reg_din;
146
wire          [1:0] dbg_mem_wr;
147
 
148
wire         [15:0] per_dout_or;
149
wire         [15:0] per_dout_sfr;
150
wire         [15:0] per_dout_wdog;
151
wire         [15:0] per_dout_clk;
152
 
153
 
154
//=============================================================================
155
// 2)  GLOBAL CLOCK & RESET MANAGEMENT
156
//=============================================================================
157
 
158
clock_module clock_module_0 (
159
 
160
// OUTPUTs
161
    .aclk_en      (aclk_en),       // ACLK enablex
162
    .mclk         (mclk),          // Main system clock
163
    .per_dout     (per_dout_clk),  // Peripheral data output
164
    .por          (por),           // Power-on reset
165
    .puc          (puc),           // Main system reset
166
    .smclk_en     (smclk_en),      // SMCLK enable
167
 
168
// INPUTs
169
    .dbg_reset    (dbg_reset),     // Reset CPU from debug interface
170
    .dco_clk      (dco_clk),       // Fast oscillator (fast clock)
171
    .lfxt_clk     (lfxt_clk),      // Low frequency oscillator (typ 32kHz)
172
    .oscoff       (oscoff),        // Turns off LFXT1 clock input
173
    .per_addr     (per_addr),      // Peripheral address
174
    .per_din      (per_din),       // Peripheral data input
175
    .per_en       (per_en),        // Peripheral enable (high active)
176
    .per_wen      (per_wen),       // Peripheral write enable (high active)
177
    .reset_n      (reset_n),       // Reset Pin (low active)
178
    .scg1         (scg1),          // System clock generator 1. Turns off the SMCLK
179
    .wdt_reset    (wdt_reset)      // Watchdog-timer reset
180
);
181
 
182
 
183
//=============================================================================
184
// 3)  FRONTEND (<=> FETCH & DECODE)
185
//=============================================================================
186
 
187
frontend frontend_0 (
188
 
189
// OUTPUTs
190
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
191
    .decode       (decode),        // Frontend decode instruction
192
    .e_state      (e_state),       // Execution state
193
    .exec_done    (exec_done),     // Execution completed
194
    .inst_ad      (inst_ad),       // Decoded Inst: destination addressing mode
195
    .inst_as      (inst_as),       // Decoded Inst: source addressing mode
196
    .inst_alu     (inst_alu),      // ALU control signals
197
    .inst_bw      (inst_bw),       // Decoded Inst: byte width
198
    .inst_dest    (inst_dest),     // Decoded Inst: destination (one hot)
199
    .inst_dext    (inst_dext),     // Decoded Inst: destination extended instruction word
200
    .inst_irq_rst (inst_irq_rst),  // Decoded Inst: Reset interrupt
201
    .inst_jmp     (inst_jmp),      // Decoded Inst: Conditional jump
202
    .inst_sext    (inst_sext),     // Decoded Inst: source extended instruction word
203
    .inst_so      (inst_so),       // Decoded Inst: Single-operand arithmetic
204
    .inst_src     (inst_src),      // Decoded Inst: source (one hot)
205
    .inst_type    (inst_type),     // Decoded Instruction type
206
    .irq_acc      (irq_acc),       // Interrupt request accepted
207
    .mab          (fe_mab),        // Frontend Memory address bus
208
    .mb_en        (fe_mb_en),      // Frontend Memory bus enable
209
    .nmi_acc      (nmi_acc),       // Non-Maskable interrupt request accepted
210
    .pc           (pc),            // Program counter
211
    .pc_nxt       (pc_nxt),        // Next PC value (for CALL & IRQ)
212
 
213
// INPUTs
214
    .cpuoff       (cpuoff),        // Turns off the CPU
215
    .dbg_halt_cmd (dbg_halt_cmd),  // Halt CPU command
216
    .dbg_reg_sel  (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
217 33 olivier.gi
    .fe_pmem_wait (fe_pmem_wait),  // Frontend wait for Instruction fetch
218 2 olivier.gi
    .gie          (gie),           // General interrupt enable
219
    .irq          (irq),           // Maskable interrupts
220
    .mclk         (mclk),          // Main system clock
221
    .mdb_in       (fe_mdb_in),     // Frontend Memory data bus input
222
    .nmi_evt      (nmi_evt),       // Non-maskable interrupt event
223
    .pc_sw        (pc_sw),         // Program counter software value
224
    .pc_sw_wr     (pc_sw_wr),      // Program counter software write
225
    .puc          (puc),           // Main system reset
226
    .wdt_irq      (wdt_irq)        // Watchdog-timer interrupt
227
);
228
 
229
 
230
//=============================================================================
231
// 4)  EXECUTION UNIT
232
//=============================================================================
233
 
234
execution_unit execution_unit_0 (
235
 
236
// OUTPUTs
237
    .cpuoff       (cpuoff),        // Turns off the CPU
238
    .dbg_reg_din  (dbg_reg_din),   // Debug unit CPU register data input
239
    .mab          (eu_mab),        // Memory address bus
240
    .mb_en        (eu_mb_en),      // Memory bus enable
241
    .mb_wr        (eu_mb_wr),      // Memory bus write transfer
242
    .mdb_out      (eu_mdb_out),    // Memory data bus output
243
    .oscoff       (oscoff),        // Turns off LFXT1 clock input
244
    .pc_sw        (pc_sw),         // Program counter software value
245
    .pc_sw_wr     (pc_sw_wr),      // Program counter software write
246
    .scg1         (scg1),          // System clock generator 1. Turns off the SMCLK
247
 
248
// INPUTs
249
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
250
    .dbg_mem_dout (dbg_mem_dout),  // Debug unit data output
251
    .dbg_reg_wr   (dbg_reg_wr),    // Debug unit CPU register write
252
    .e_state      (e_state),       // Execution state
253
    .exec_done    (exec_done),     // Execution completed
254
    .gie          (gie),           // General interrupt enable
255
    .inst_ad      (inst_ad),       // Decoded Inst: destination addressing mode
256
    .inst_as      (inst_as),       // Decoded Inst: source addressing mode
257
    .inst_alu     (inst_alu),      // ALU control signals
258
    .inst_bw      (inst_bw),       // Decoded Inst: byte width
259
    .inst_dest    (inst_dest),     // Decoded Inst: destination (one hot)
260
    .inst_dext    (inst_dext),     // Decoded Inst: destination extended instruction word
261
    .inst_irq_rst (inst_irq_rst),  // Decoded Inst: reset interrupt
262
    .inst_jmp     (inst_jmp),      // Decoded Inst: Conditional jump
263
    .inst_sext    (inst_sext),     // Decoded Inst: source extended instruction word
264
    .inst_so      (inst_so),       // Decoded Inst: Single-operand arithmetic
265
    .inst_src     (inst_src),      // Decoded Inst: source (one hot)
266
    .inst_type    (inst_type),     // Decoded Instruction type
267
    .mclk         (mclk),          // Main system clock
268
    .mdb_in       (eu_mdb_in),     // Memory data bus input
269
    .pc           (pc),            // Program counter
270
    .pc_nxt       (pc_nxt),        // Next PC value (for CALL & IRQ)
271
    .puc          (puc)            // Main system reset
272
);
273
 
274
 
275
//=============================================================================
276
// 5)  MEMORY BACKBONE
277
//=============================================================================
278
 
279
mem_backbone mem_backbone_0 (
280
 
281
// OUTPUTs
282
    .dbg_mem_din  (dbg_mem_din),   // Debug unit Memory data input
283 33 olivier.gi
    .dmem_addr    (dmem_addr),     // Data Memory address
284
    .dmem_cen     (dmem_cen),      // Data Memory chip enable (low active)
285
    .dmem_din     (dmem_din),      // Data Memory data input
286
    .dmem_wen     (dmem_wen),      // Data Memory write enable (low active)
287 2 olivier.gi
    .eu_mdb_in    (eu_mdb_in),     // Execution Unit Memory data bus input
288
    .fe_mdb_in    (fe_mdb_in),     // Frontend Memory data bus input
289 33 olivier.gi
    .fe_pmem_wait (fe_pmem_wait),  // Frontend wait for Instruction fetch
290 2 olivier.gi
    .per_addr     (per_addr),      // Peripheral address
291
    .per_din      (per_din),       // Peripheral data input
292
    .per_wen      (per_wen),       // Peripheral write enable (high active)
293
    .per_en       (per_en),        // Peripheral enable (high active)
294 33 olivier.gi
    .pmem_addr    (pmem_addr),     // Program Memory address
295
    .pmem_cen     (pmem_cen),      // Program Memory chip enable (low active)
296
    .pmem_din     (pmem_din),      // Program Memory data input (optional)
297
    .pmem_wen     (pmem_wen),      // Program Memory write enable (low active) (optional)
298 2 olivier.gi
 
299
// INPUTs
300
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
301
    .dbg_mem_addr (dbg_mem_addr),  // Debug address for rd/wr access
302
    .dbg_mem_dout (dbg_mem_dout),  // Debug unit data output
303
    .dbg_mem_en   (dbg_mem_en),    // Debug unit memory enable
304
    .dbg_mem_wr   (dbg_mem_wr),    // Debug unit memory write
305 33 olivier.gi
    .dmem_dout    (dmem_dout),     // Data Memory data output
306 2 olivier.gi
    .eu_mab       (eu_mab[15:1]),  // Execution Unit Memory address bus
307
    .eu_mb_en     (eu_mb_en),      // Execution Unit Memory bus enable
308
    .eu_mb_wr     (eu_mb_wr),      // Execution Unit Memory bus write transfer
309
    .eu_mdb_out   (eu_mdb_out),    // Execution Unit Memory data bus output
310
    .fe_mab       (fe_mab[15:1]),  // Frontend Memory address bus
311
    .fe_mb_en     (fe_mb_en),      // Frontend Memory bus enable
312
    .mclk         (mclk),          // Main system clock
313
    .per_dout     (per_dout_or),   // Peripheral data output
314 33 olivier.gi
    .pmem_dout    (pmem_dout),     // Program Memory data output
315
    .puc          (puc)            // Main system reset
316 2 olivier.gi
);
317
 
318
 
319
//=============================================================================
320
// 6)  SPECIAL FUNCTION REGISTERS
321
//=============================================================================
322
 
323
sfr sfr_0 (
324
 
325
// OUTPUTs
326
    .nmie         (nmie),          // Non-maskable interrupt enable
327
    .per_dout     (per_dout_sfr),  // Peripheral data output
328
    .wdt_irq      (wdt_irq),       // Watchdog-timer interrupt
329
    .wdt_reset    (wdt_reset),     // Watchdog-timer reset
330
    .wdtie        (wdtie),         // Watchdog-timer interrupt enable
331
 
332
// INPUTs
333
    .mclk         (mclk),          // Main system clock
334
    .nmi_acc      (nmi_acc),       // Non-Maskable interrupt request accepted
335
    .per_addr     (per_addr),      // Peripheral address
336
    .per_din      (per_din),       // Peripheral data input
337
    .per_en       (per_en),        // Peripheral enable (high active)
338
    .per_wen      (per_wen),       // Peripheral write enable (high active)
339
    .por          (por),           // Power-on reset
340
    .puc          (puc),           // Main system reset
341
    .wdtifg_clr   (irq_acc[10]),   // Clear Watchdog-timer interrupt flag
342
    .wdtifg_set   (wdtifg_set),    // Set Watchdog-timer interrupt flag
343
    .wdtpw_error  (wdtpw_error),   // Watchdog-timer password error
344
    .wdttmsel     (wdttmsel)       // Watchdog-timer mode select
345
);
346
 
347
 
348
//=============================================================================
349
// 7)  WATCHDOG TIMER
350
//=============================================================================
351
 
352
watchdog watchdog_0 (
353
 
354
// OUTPUTs
355
    .nmi_evt      (nmi_evt),       // NMI Event
356
    .per_dout     (per_dout_wdog), // Peripheral data output
357
    .wdtifg_set   (wdtifg_set),    // Set Watchdog-timer interrupt flag
358
    .wdtpw_error  (wdtpw_error),   // Watchdog-timer password error
359
    .wdttmsel     (wdttmsel),      // Watchdog-timer mode select
360
 
361
// INPUTs
362
    .aclk_en      (aclk_en),       // ACLK enable
363
    .dbg_freeze   (dbg_freeze),    // Freeze Watchdog counter
364
    .mclk         (mclk),          // Main system clock
365
    .nmi          (nmi),           // Non-maskable interrupt (asynchronous)
366
    .nmie         (nmie),          // Non-maskable interrupt enable
367
    .per_addr     (per_addr),      // Peripheral address
368
    .per_din      (per_din),       // Peripheral data input
369
    .per_en       (per_en),        // Peripheral enable (high active)
370
    .per_wen      (per_wen),       // Peripheral write enable (high active)
371
    .puc          (puc),           // Main system reset
372
    .smclk_en     (smclk_en),      // SMCLK enable
373
    .wdtie        (wdtie)          // Watchdog-timer interrupt enable
374
);
375
 
376
 
377
//=============================================================================
378
// 8)  PERIPHERALS' OUTPUT BUS
379
//=============================================================================
380
 
381
assign  per_dout_or  =  per_dout      |
382
                        per_dout_clk  |
383
                        per_dout_sfr  |
384
                        per_dout_wdog;
385
 
386
 
387
//=============================================================================
388
// 9)  DEBUG INTERFACE
389
//=============================================================================
390
 
391
`ifdef DBG_EN
392
dbg dbg_0 (
393
 
394
// OUTPUTs
395
    .dbg_freeze   (dbg_freeze),    // Freeze peripherals
396
    .dbg_halt_cmd (dbg_halt_cmd),  // Halt CPU command
397
    .dbg_mem_addr (dbg_mem_addr),  // Debug address for rd/wr access
398
    .dbg_mem_dout (dbg_mem_dout),  // Debug unit data output
399
    .dbg_mem_en   (dbg_mem_en),    // Debug unit memory enable
400
    .dbg_mem_wr   (dbg_mem_wr),    // Debug unit memory write
401
    .dbg_reg_wr   (dbg_reg_wr),    // Debug unit CPU register write
402
    .dbg_reset    (dbg_reset),     // Reset CPU from debug interface
403
    .dbg_uart_txd (dbg_uart_txd),  // Debug interface: UART TXD
404
 
405
// INPUTs
406
    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
407
    .dbg_mem_din  (dbg_mem_din),   // Debug unit Memory data input
408
    .dbg_reg_din  (dbg_reg_din),   // Debug unit CPU register data input
409
    .dbg_uart_rxd (dbg_uart_rxd),  // Debug interface: UART RXD
410
    .decode       (decode),        // Frontend decode instruction
411
    .eu_mab       (eu_mab),        // Execution-Unit Memory address bus
412
    .eu_mb_en     (eu_mb_en),      // Execution-Unit Memory bus enable
413
    .eu_mb_wr     (eu_mb_wr),      // Execution-Unit Memory bus write transfer
414
    .eu_mdb_in    (eu_mdb_in),     // Memory data bus input
415
    .eu_mdb_out   (eu_mdb_out),    // Memory data bus output
416
    .exec_done    (exec_done),     // Execution completed
417
    .fe_mb_en     (fe_mb_en),      // Frontend Memory bus enable
418
    .fe_mdb_in    (fe_mdb_in),     // Frontend Memory data bus input
419
    .mclk         (mclk),          // Main system clock
420
    .pc           (pc),            // Program counter
421
    .por          (por),           // Power on reset
422
    .puc          (puc)            // Main system reset
423
);
424
 
425
`else
426
assign dbg_freeze   =  1'b0;
427
assign dbg_halt_cmd =  1'b0;
428
assign dbg_mem_addr = 16'h0000;
429
assign dbg_mem_dout = 16'h0000;
430
assign dbg_mem_en   =  1'b0;
431
assign dbg_mem_wr   =  2'b00;
432
assign dbg_reg_wr   =  1'b0;
433
assign dbg_reset    =  1'b0;
434
assign dbg_uart_txd =  1'b0;
435
`endif
436
 
437
 
438
endmodule // openMSP430
439
 
440 33 olivier.gi
`include "openMSP430_undefines.v"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.