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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [openMSP430_defines.v] - Blame information for rev 2

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//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
//
//----------------------------------------------------------------------------
// 
// *File Name: openMSP430.inc
// 
// *Module Description:
//                      openMSP430 Configuration file
//
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//
//----------------------------------------------------------------------------
 
 
//----------------------------------------------------------------------------
// SYSTEM CONFIGURATION
//----------------------------------------------------------------------------
 
// ROM Size:
//                    9 ->  1kB
//                   10 ->  2kB
//                   11 ->  4kB
//                   12 ->  8kB
//                   13 -> 16kB
`define ROM_AWIDTH   10
 
// RAM Size:
//                    6 ->  128 B
//                    7 ->  256 B
//                    8 ->  512 B
//                    9 ->    1 kB
//                   10 ->    2 kB
`define RAM_AWIDTH    6
 
//----------------------------------------------------------------------------
// REMOTE DEBUGGING INTERFACE CONFIGURATION
//----------------------------------------------------------------------------
 
// Include Debug interface
`define DBG_EN
 
// Debug interface selection
//             `define DBG_UART -> Enable UART (8N1) debug interface
//             `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED YET
//
`define DBG_UART
//`define DBG_JTAG
 
// Number of hardware breakpoints (each unit contains 2 hw address breakpoints)
//             `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0
//             `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1
//             `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2
//             `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3
//
`define  DBG_HWBRK_0
`define  DBG_HWBRK_1
`define  DBG_HWBRK_2
`define  DBG_HWBRK_3
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
 
// ROM and RAM sizes
`define ROM_SIZE  (2 << `ROM_AWIDTH)
`define RAM_SIZE  (2 << `RAM_AWIDTH)
 
// RAM Base Adresses
`define RAM_BASE      16'h0200  // RAM base address
 
// ROM & RAM most significant address bit (for 16 bit words)
`define ROM_MSB   `ROM_AWIDTH-1
`define RAM_MSB   `RAM_AWIDTH-1
 
 
// Instructions type
`define INST_SO  0
`define INST_JMP 1
`define INST_TO  2
 
// Single-operand arithmetic
`define RRC    0
`define SWPB   1
`define RRA    2
`define SXT    3
`define PUSH   4
`define CALL   5
`define RETI   6
`define IRQ    7
 
// Conditional jump
`define JNE    0
`define JEQ    1
`define JNC    2
`define JC     3
`define JN     4
`define JGE    5
`define JL     6
`define JMP    7
 
// Two-operand arithmetic
`define MOV    0
`define ADD    1
`define ADDC   2
`define SUBC   3
`define SUB    4
`define CMP    5
`define DADD   6
`define BIT    7
`define BIC    8
`define BIS    9
`define XOR   10
`define AND   11
 
// Addressing modes
`define DIR      0
`define IDX      1
`define INDIR    2
`define INDIR_I  3
`define SYMB     4
`define IMM      5
`define ABS      6
`define CONST    7
 
// Execution state machine
`define E_IRQ_0    4'h0
`define E_IRQ_1    4'h1
`define E_IRQ_2    4'h2
`define E_IRQ_3    4'h3
`define E_IRQ_4    4'h4
`define E_SRC_AD   4'h5
`define E_SRC_RD   4'h6
`define E_SRC_WR   4'h7
`define E_DST_AD   4'h8
`define E_DST_RD   4'h9
`define E_DST_WR   4'hA
`define E_EXEC     4'hB
`define E_JUMP     4'hC
`define E_IDLE     4'hD
 
// ALU control signals
`define ALU_SRC_INV   0
`define ALU_INC       1
`define ALU_INC_C     2
`define ALU_ADD       3
`define ALU_AND       4
`define ALU_OR        5
`define ALU_XOR       6
`define ALU_DADD      7
`define ALU_STAT_7    8
`define ALU_STAT_F    9
`define ALU_SHIFT    10
`define EXEC_NO_WR   11
 
// Debug interface
`define DBG_UART_WR   18
`define DBG_UART_BW   17
`define DBG_UART_ADDR 16:11
 
// Debug interface CPU_CTL register
`define HALT        0
`define RUN         1
`define ISTEP       2
`define SW_BRK_EN   3
`define FRZ_BRK_EN  4
`define RST_BRK_EN  5
`define CPU_RST     6
 
// Debug interface CPU_STAT register
`define HALT_RUN    0
`define PUC_PND     1
`define SWBRK_PND   3
`define HWBRK0_PND  4
`define HWBRK1_PND  5
 
// Debug interface BRKx_CTL register
`define BRK_MODE_RD 0
`define BRK_MODE_WR 1
`define BRK_MODE    1:0
`define BRK_EN      2
`define BRK_I_EN    3
`define BRK_RANGE   4
 
// Basic clock module: BCSCTL1 Control Register
`define DIVAx       5:4
 
// Basic clock module: BCSCTL2 Control Register
`define SELS        3
`define DIVSx       2:1
 
// Timer A: TACTL Control Register
`define TASSELx     9:8
`define TAIDx       7:6
`define TAMCx       5:4
`define TACLR       2
`define TAIE        1
`define TAIFG       0
 
// Timer A: TACCTLx Capture/Compare Control Register
`define TACMx      15:14
`define TACCISx    13:12
`define TASCS      11
`define TASCCI     10
`define TACAP       8
`define TAOUTMODx   7:5
`define TACCIE      4
`define TACCI       3
`define TAOUT       2
`define TACOV       1
`define TACCIFG     0
 
//
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
 
// Debug interface: Software breakpoint opcode
`define DBG_SWBRK_OP 16'h4343
 
// Debug interface ID
`define DBG_ID  24'h4D5350
 
// Debug UART interface auto data synchronization
// If the following define is commented out, then
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
// defined.
`define DBG_UART_AUTO_SYNC
 
// Debug UART interface data rate
//      In order to properly setup the UART debug interface, you
//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
//      the chosen BAUD rate from the UART interface.
//
//`define DBG_UART_BAUD    9600
//`define DBG_UART_BAUD   19200
//`define DBG_UART_BAUD   38400
//`define DBG_UART_BAUD   57600
//`define DBG_UART_BAUD  115200
//`define DBG_UART_BAUD  230400
//`define DBG_UART_BAUD  460800
//`define DBG_UART_BAUD  576000
//`define DBG_UART_BAUD  921600
`define DBG_UART_BAUD 2000000
`define DBG_DCO_FREQ  20000000
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
 
// Check configuration
`ifdef DBG_EN
 `ifdef DBG_UART
   `ifdef DBG_JTAG
CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED
   `endif
 `else
   `ifdef DBG_JTAG
CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED YET
   `else
CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED
   `endif
 `endif
`endif

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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [openMSP430_defines.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	olivier.gi	`//----------------------------------------------------------------------------`
2			`// Copyright (C) 2001 Authors`
3			`//`
4			`// This source file may be used and distributed without restriction provided`
5			`// that this copyright statement is not removed from the file and that any`
6			`// derivative work contains the original copyright notice and the associated`
7			`// disclaimer.`
8			`//`
9			`// This source file is free software; you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation; either version 2.1 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
16			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public`
17			`// License for more details.`
18			`//`
19			`// You should have received a copy of the GNU Lesser General Public License`
20			`// along with this source; if not, write to the Free Software Foundation,`
21			`// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA`
22			`//`
23			`//----------------------------------------------------------------------------`
24			`//`
25			`// *File Name: openMSP430.inc`
26			`//`
27			`// *Module Description:`
28			`// openMSP430 Configuration file`
29			`//`
30			`// *Author(s):`
31			`// - Olivier Girard, olgirard@gmail.com`
32			`//`
33			`//----------------------------------------------------------------------------`
34
35
36			`//----------------------------------------------------------------------------`
37			`// SYSTEM CONFIGURATION`
38			`//----------------------------------------------------------------------------`
39
40			`// ROM Size:`
41			`// 9 -> 1kB`
42			`// 10 -> 2kB`
43			`// 11 -> 4kB`
44			`// 12 -> 8kB`
45			`// 13 -> 16kB`
46			`define ROM_AWIDTH 10
47
48			`// RAM Size:`
49			`// 6 -> 128 B`
50			`// 7 -> 256 B`
51			`// 8 -> 512 B`
52			`// 9 -> 1 kB`
53			`// 10 -> 2 kB`
54			`define RAM_AWIDTH 6
55
56			`//----------------------------------------------------------------------------`
57			`// REMOTE DEBUGGING INTERFACE CONFIGURATION`
58			`//----------------------------------------------------------------------------`
59
60			`// Include Debug interface`
61			`define DBG_EN
62
63			`// Debug interface selection`
64			// `define DBG_UART -> Enable UART (8N1) debug interface
65			// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED YET
66			`//`
67			`define DBG_UART
68			//`define DBG_JTAG
69
70			`// Number of hardware breakpoints (each unit contains 2 hw address breakpoints)`
71			// `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0
72			// `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1
73			// `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2
74			// `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3
75			`//`
76			`define DBG_HWBRK_0
77			`define DBG_HWBRK_1
78			`define DBG_HWBRK_2
79			`define DBG_HWBRK_3
80
81
82			`//==========================================================================//`
83			`//==========================================================================//`
84			`//==========================================================================//`
85			`//==========================================================================//`
86			`//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//`
87			`//==========================================================================//`
88			`//==========================================================================//`
89			`//==========================================================================//`
90			`//==========================================================================//`
91
92			`// ROM and RAM sizes`
93			`define ROM_SIZE (2 << `ROM_AWIDTH)
94			`define RAM_SIZE (2 << `RAM_AWIDTH)
95
96			`// RAM Base Adresses`
97			`define RAM_BASE 16'h0200 // RAM base address
98
99			`// ROM & RAM most significant address bit (for 16 bit words)`
100			`define ROM_MSB `ROM_AWIDTH-1
101			`define RAM_MSB `RAM_AWIDTH-1
102
103
104			`// Instructions type`
105			`define INST_SO 0
106			`define INST_JMP 1
107			`define INST_TO 2
108
109			`// Single-operand arithmetic`
110			`define RRC 0
111			`define SWPB 1
112			`define RRA 2
113			`define SXT 3
114			`define PUSH 4
115			`define CALL 5
116			`define RETI 6
117			`define IRQ 7
118
119			`// Conditional jump`
120			`define JNE 0
121			`define JEQ 1
122			`define JNC 2
123			`define JC 3
124			`define JN 4
125			`define JGE 5
126			`define JL 6
127			`define JMP 7
128
129			`// Two-operand arithmetic`
130			`define MOV 0
131			`define ADD 1
132			`define ADDC 2
133			`define SUBC 3
134			`define SUB 4
135			`define CMP 5
136			`define DADD 6
137			`define BIT 7
138			`define BIC 8
139			`define BIS 9
140			`define XOR 10
141			`define AND 11
142
143			`// Addressing modes`
144			`define DIR 0
145			`define IDX 1
146			`define INDIR 2
147			`define INDIR_I 3
148			`define SYMB 4
149			`define IMM 5
150			`define ABS 6
151			`define CONST 7
152
153			`// Execution state machine`
154			`define E_IRQ_0 4'h0
155			`define E_IRQ_1 4'h1
156			`define E_IRQ_2 4'h2
157			`define E_IRQ_3 4'h3
158			`define E_IRQ_4 4'h4
159			`define E_SRC_AD 4'h5
160			`define E_SRC_RD 4'h6
161			`define E_SRC_WR 4'h7
162			`define E_DST_AD 4'h8
163			`define E_DST_RD 4'h9
164			`define E_DST_WR 4'hA
165			`define E_EXEC 4'hB
166			`define E_JUMP 4'hC
167			`define E_IDLE 4'hD
168
169			`// ALU control signals`
170			`define ALU_SRC_INV 0
171			`define ALU_INC 1
172			`define ALU_INC_C 2
173			`define ALU_ADD 3
174			`define ALU_AND 4
175			`define ALU_OR 5
176			`define ALU_XOR 6
177			`define ALU_DADD 7
178			`define ALU_STAT_7 8
179			`define ALU_STAT_F 9
180			`define ALU_SHIFT 10
181			`define EXEC_NO_WR 11
182
183			`// Debug interface`
184			`define DBG_UART_WR 18
185			`define DBG_UART_BW 17
186			`define DBG_UART_ADDR 16:11
187
188			`// Debug interface CPU_CTL register`
189			`define HALT 0
190			`define RUN 1
191			`define ISTEP 2
192			`define SW_BRK_EN 3
193			`define FRZ_BRK_EN 4
194			`define RST_BRK_EN 5
195			`define CPU_RST 6
196
197			`// Debug interface CPU_STAT register`
198			`define HALT_RUN 0
199			`define PUC_PND 1
200			`define SWBRK_PND 3
201			`define HWBRK0_PND 4
202			`define HWBRK1_PND 5
203
204			`// Debug interface BRKx_CTL register`
205			`define BRK_MODE_RD 0
206			`define BRK_MODE_WR 1
207			`define BRK_MODE 1:0
208			`define BRK_EN 2
209			`define BRK_I_EN 3
210			`define BRK_RANGE 4
211
212			`// Basic clock module: BCSCTL1 Control Register`
213			`define DIVAx 5:4
214
215			`// Basic clock module: BCSCTL2 Control Register`
216			`define SELS 3
217			`define DIVSx 2:1
218
219			`// Timer A: TACTL Control Register`
220			`define TASSELx 9:8
221			`define TAIDx 7:6
222			`define TAMCx 5:4
223			`define TACLR 2
224			`define TAIE 1
225			`define TAIFG 0
226
227			`// Timer A: TACCTLx Capture/Compare Control Register`
228			`define TACMx 15:14
229			`define TACCISx 13:12
230			`define TASCS 11
231			`define TASCCI 10
232			`define TACAP 8
233			`define TAOUTMODx 7:5
234			`define TACCIE 4
235			`define TACCI 3
236			`define TAOUT 2
237			`define TACOV 1
238			`define TACCIFG 0
239
240			`//`
241			`// DEBUG INTERFACE EXTRA CONFIGURATION`
242			`//======================================`
243
244			`// Debug interface: Software breakpoint opcode`
245			`define DBG_SWBRK_OP 16'h4343
246
247			`// Debug interface ID`
248			`define DBG_ID 24'h4D5350
249
250			`// Debug UART interface auto data synchronization`
251			`// If the following define is commented out, then`
252			`// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly`
253			`// defined.`
254			`define DBG_UART_AUTO_SYNC
255
256			`// Debug UART interface data rate`
257			`// In order to properly setup the UART debug interface, you`
258			`// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and`
259			`// the chosen BAUD rate from the UART interface.`
260			`//`
261			//`define DBG_UART_BAUD 9600
262			//`define DBG_UART_BAUD 19200
263			//`define DBG_UART_BAUD 38400
264			//`define DBG_UART_BAUD 57600
265			//`define DBG_UART_BAUD 115200
266			//`define DBG_UART_BAUD 230400
267			//`define DBG_UART_BAUD 460800
268			//`define DBG_UART_BAUD 576000
269			//`define DBG_UART_BAUD 921600
270			`define DBG_UART_BAUD 2000000
271			`define DBG_DCO_FREQ 20000000
272			`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
273
274			`// Check configuration`
275			`ifdef DBG_EN
276			`ifdef DBG_UART
277			`ifdef DBG_JTAG
278			`CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED`
279			`endif
280			`else
281			`ifdef DBG_JTAG
282			`CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED YET`
283			`else
284			`CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED`
285			`endif
286			`endif
287			`endif