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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [openMSP430_undefines.v] - Blame information for rev 67

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Line No. Rev Author Line
1 33 olivier.gi 
//----------------------------------------------------------------------------
2 
// Copyright (C) 2001 Authors
3 
//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: openMSP430_undefines.v
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//
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// *Module Description:
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//                      openMSP430 Verilog `undef file
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 23 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
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//----------------------------------------------------------------------------
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39 
//----------------------------------------------------------------------------
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// SYSTEM CONFIGURATION
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//----------------------------------------------------------------------------
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43 
// Program Memory Size:
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`ifdef PMEM_AWIDTH
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`undef PMEM_AWIDTH
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`endif
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// Data Memory Size:
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`ifdef DMEM_AWIDTH
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`undef DMEM_AWIDTH
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`endif
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53 67 olivier.gi 
// Include/Exclude Hardware Multiplier
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`ifdef MULTIPLIER
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`undef MULTIPLIER
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`endif
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58 33 olivier.gi 
//----------------------------------------------------------------------------
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// REMOTE DEBUGGING INTERFACE CONFIGURATION
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//----------------------------------------------------------------------------
61 
 
62 
// Include Debug interface
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`ifdef DBG_EN
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`undef DBG_EN
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`endif
66 
 
67 
// Debug interface selection
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`ifdef DBG_UART
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`undef DBG_UART
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`endif
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`ifdef DBG_JTAG
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`undef DBG_JTAG
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`endif
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// Number of hardware breakpoints
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`ifdef DBG_HWBRK_0
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`undef DBG_HWBRK_0
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`endif
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`ifdef DBG_HWBRK_1
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`undef DBG_HWBRK_1
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`endif
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`ifdef DBG_HWBRK_2
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`undef DBG_HWBRK_2
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`endif
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`ifdef DBG_HWBRK_3
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`undef DBG_HWBRK_3
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`endif
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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// Program and Data Memory sizes
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`ifdef PMEM_SIZE
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`undef PMEM_SIZE
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`endif
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`ifdef DMEM_SIZE
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`undef DMEM_SIZE
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`endif
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// Data Memory Base Adresses
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`ifdef DMEM_BASE
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`undef DMEM_BASE
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`endif
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// Program & Data Memory most significant address bit (for 16 bit words)
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`ifdef PMEM_MSB
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`undef PMEM_MSB
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`endif
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`ifdef DMEM_MSB
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`undef DMEM_MSB
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`endif
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121 
 
122 
// Instructions type
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`ifdef INST_SO
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`undef INST_SO
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`endif
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`ifdef INST_JMP
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`undef INST_JMP
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`endif
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`ifdef INST_TO
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`undef INST_TO
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`endif
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// Single-operand arithmetic
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`ifdef RRC
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`undef RRC
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`endif
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`ifdef SWPB
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`undef SWPB
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`endif
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`ifdef RRA
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`undef RRA
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`endif
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`ifdef SXT
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`undef SXT
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`endif
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`ifdef PUSH
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`undef PUSH
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`endif
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`ifdef CALL
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`undef CALL
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`endif
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`ifdef RETI
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`undef RETI
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`endif
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`ifdef IRQ
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`undef IRQ
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`endif
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// Conditional jump
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`ifdef JNE
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`undef JNE
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`endif
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`ifdef JEQ
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`undef JEQ
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`endif
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`ifdef JNC
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`undef JNC
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`endif
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`ifdef JC
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`undef JC
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`endif
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`ifdef JN
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`undef JN
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`endif
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`ifdef JGE
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`undef JGE
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`endif
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`ifdef JL
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`undef JL
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`endif
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`ifdef JMP
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`undef JMP
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`endif
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185 
// Two-operand arithmetic
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`ifdef MOV
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`undef MOV
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`endif
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`ifdef ADD
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`undef ADD
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`endif
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`ifdef ADDC
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`undef ADDC
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`endif
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`ifdef SUBC
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`undef SUBC
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`endif
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`ifdef SUB
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`undef SUB
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`endif
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`ifdef CMP
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`undef CMP
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`endif
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`ifdef DADD
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`undef DADD
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`endif
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`ifdef BIT
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`undef BIT
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`endif
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`ifdef BIC
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`undef BIC
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`endif
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`ifdef BIS
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`undef BIS
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`endif
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`ifdef XOR
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`undef XOR
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`endif
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`ifdef AND
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`undef AND
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`endif
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223 
// Addressing modes
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`ifdef DIR
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`undef DIR
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`endif
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`ifdef IDX
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`undef IDX
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`endif
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`ifdef INDIR
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`undef INDIR
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`endif
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`ifdef INDIR_I
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`undef INDIR_I
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`endif
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`ifdef SYMB
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`undef SYMB
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`endif
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`ifdef IMM
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`undef IMM
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`endif
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`ifdef ABS
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`undef ABS
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`endif
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`ifdef CONST
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`undef CONST
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`endif
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249 
// Execution state machine
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`ifdef E_IRQ_0
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`undef E_IRQ_0
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`endif
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`ifdef E_IRQ_1
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`undef E_IRQ_1
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`endif
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`ifdef E_IRQ_2
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`undef E_IRQ_2
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`endif
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`ifdef E_IRQ_3
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`undef E_IRQ_3
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`endif
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`ifdef E_IRQ_4
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`undef E_IRQ_4
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`endif
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`ifdef E_SRC_AD
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`undef E_SRC_AD
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`endif
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`ifdef E_SRC_RD
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`undef E_SRC_RD
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`endif
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`ifdef E_SRC_WR
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`undef E_SRC_WR
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`endif
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`ifdef E_DST_AD
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`undef E_DST_AD
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`endif
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`ifdef E_DST_RD
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`undef E_DST_RD
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`endif
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`ifdef E_DST_WR
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`undef E_DST_WR
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`endif
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`ifdef E_EXEC
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`undef E_EXEC
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`endif
286 
`ifdef E_JUMP
287 
`undef E_JUMP
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`endif
289 
`ifdef E_IDLE
290 
`undef E_IDLE
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`endif
292 
 
293 
// ALU control signals
294 
`ifdef ALU_SRC_INV
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`undef ALU_SRC_INV
296 
`endif
297 
`ifdef ALU_INC
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`undef ALU_INC
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`endif
300 
`ifdef ALU_INC_C
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`undef ALU_INC_C
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`endif
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`ifdef ALU_ADD
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`undef ALU_ADD
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`endif
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`ifdef ALU_AND
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`undef ALU_AND
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`endif
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`ifdef ALU_OR
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`undef ALU_OR
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`endif
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`ifdef ALU_XOR
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`undef ALU_XOR
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`endif
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`ifdef ALU_DADD
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`undef ALU_DADD
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`endif
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`ifdef ALU_STAT_7
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`undef ALU_STAT_7
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`endif
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`ifdef ALU_STAT_F
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`undef ALU_STAT_F
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`endif
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`ifdef ALU_SHIFT
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`undef ALU_SHIFT
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`endif
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`ifdef EXEC_NO_WR
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`undef EXEC_NO_WR
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`endif
330 
 
331 
// Debug interface
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`ifdef DBG_UART_WR
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`undef DBG_UART_WR
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`endif
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`ifdef DBG_UART_BW
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`undef DBG_UART_BW
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`endif
338 
`ifdef DBG_UART_ADDR
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`undef DBG_UART_ADDR
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`endif
341 
 
342 
// Debug interface CPU_CTL register
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`ifdef HALT
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`undef HALT
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`endif
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`ifdef RUN
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`undef RUN
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`endif
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`ifdef ISTEP
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`undef ISTEP
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`endif
352 
`ifdef SW_BRK_EN
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`undef SW_BRK_EN
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`endif
355 
`ifdef FRZ_BRK_EN
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`undef FRZ_BRK_EN
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`endif
358 
`ifdef RST_BRK_EN
359 
`undef RST_BRK_EN
360 
`endif
361 
`ifdef CPU_RST
362 
`undef CPU_RST
363 
`endif
364 
 
365 
// Debug interface CPU_STAT register
366 
`ifdef HALT_RUN
367 
`undef HALT_RUN
368 
`endif
369 
`ifdef PUC_PND
370 
`undef PUC_PND
371 
`endif
372 
`ifdef SWBRK_PND
373 
`undef SWBRK_PND
374 
`endif
375 
`ifdef HWBRK0_PND
376 
`undef HWBRK0_PND
377 
`endif
378 
`ifdef HWBRK1_PND
379 
`undef HWBRK1_PND
380 
`endif
381 
 
382 
// Debug interface BRKx_CTL register
383 
`ifdef BRK_MODE_RD
384 
`undef BRK_MODE_RD
385 
`endif
386 
`ifdef BRK_MODE_WR
387 
`undef BRK_MODE_WR
388 
`endif
389 
`ifdef BRK_MODE
390 
`undef BRK_MODE
391 
`endif
392 
`ifdef BRK_EN
393 
`undef BRK_EN
394 
`endif
395 
`ifdef BRK_I_EN
396 
`undef BRK_I_EN
397 
`endif
398 
`ifdef BRK_RANGE
399 
`undef BRK_RANGE
400 
`endif
401 
 
402 
// Basic clock module: BCSCTL1 Control Register
403 
`ifdef DIVAx
404 
`undef DIVAx
405 
`endif
406 
 
407 
// Basic clock module: BCSCTL2 Control Register
408 
`ifdef SELS
409 
`undef SELS
410 
`endif
411 
`ifdef DIVSx
412 
`undef DIVSx
413 
`endif
414 
 
415 
// Timer A: TACTL Control Register
416 
`ifdef TASSELx
417 
`undef TASSELx
418 
`endif
419 
`ifdef TAIDx
420 
`undef TAIDx
421 
`endif
422 
`ifdef TAMCx
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`undef TAMCx
424 
`endif
425 
`ifdef TACLR
426 
`undef TACLR
427 
`endif
428 
`ifdef TAIE
429 
`undef TAIE
430 
`endif
431 
`ifdef TAIFG
432 
`undef TAIFG
433 
`endif
434 
 
435 
// Timer A: TACCTLx Capture/Compare Control Register
436 
`ifdef TACMx
437 
`undef TACMx
438 
`endif
439 
`ifdef TACCISx
440 
`undef TACCISx
441 
`endif
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`ifdef TASCS
443 
`undef TASCS
444 
`endif
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`ifdef TASCCI
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`undef TASCCI
447 
`endif
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`ifdef TACAP
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`undef TACAP
450 
`endif
451 
`ifdef TAOUTMODx
452 
`undef TAOUTMODx
453 
`endif
454 
`ifdef TACCIE
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`undef TACCIE
456 
`endif
457 
`ifdef TACCI
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`undef TACCI
459 
`endif
460 
`ifdef TAOUT
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`undef TAOUT
462 
`endif
463 
`ifdef TACOV
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`undef TACOV
465 
`endif
466 
`ifdef TACCIFG
467 
`undef TACCIFG
468 
`endif
469 
 
470 
//
471 
// DEBUG INTERFACE EXTRA CONFIGURATION
472 
//======================================
473 
 
474 
// Debug interface: Software breakpoint opcode
475 
`ifdef DBG_SWBRK_OP
476 
`undef DBG_SWBRK_OP
477 
`endif
478 
 
479 
// Debug interface ID
480 
`ifdef DBG_ID
481 
`undef DBG_ID
482 
`endif
483 
 
484 
// Debug UART interface auto data synchronization
485 
`ifdef DBG_UART_AUTO_SYNC
486 
`undef DBG_UART_AUTO_SYNC
487 
`endif
488 
 
489 
// Debug UART interface data rate
490 
`ifdef DBG_UART_BAUD
491 
`undef DBG_UART_BAUD
492 
`endif
493 
`ifdef DBG_DCO_FREQ
494 
`undef DBG_DCO_FREQ
495 
`endif
496 
`ifdef DBG_UART_CNT
497 
`undef DBG_UART_CNT
498 
`endif
499 57 olivier.gi 
 
500 
// Enable/Disable the hardware breakpoint RANGE mode
501 
`ifdef HWBRK_RANGE
502 
`undef HWBRK_RANGE
503 67 olivier.gi 
`endif
504 
 
505 
//
506 
// MULTIPLIER CONFIGURATION
507 
//======================================
508 
 
509 
`ifdef MPY_16x16
510 
`undef MPY_16x16
511 
`endif

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