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olivier.gi |
#!/bin/sh
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#------------------------------------------------------------------------------
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# Copyright (C) 2001 Authors
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#
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# This source file may be used and distributed without restriction provided
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# that this copyright statement is not removed from the file and that any
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# derivative work contains the original copyright notice and the associated
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# disclaimer.
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#
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# This source file is free software; you can redistribute it and/or modify
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# it under the terms of the GNU Lesser General Public License as published
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# by the Free Software Foundation; either version 2.1 of the License, or
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# (at your option) any later version.
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#
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# This source is distributed in the hope that it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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# License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public License
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# along with this source; if not, write to the Free Software Foundation,
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# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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#
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#------------------------------------------------------------------------------
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#
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# File Name: rtlsim.sh
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#
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#------------------------------------------------------------------------------
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###############################################################################
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# Parameter Check #
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###############################################################################
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EXPECTED_ARGS=3
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if [ $# -ne $EXPECTED_ARGS ]; then
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echo "ERROR : wrong number of arguments"
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echo "USAGE : rtlsim.sh <verilog stimulus file> <rom file> <submit file>"
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echo "Example : rtlsim.sh ./stimulus.v rom.mem ../src/submit.f"
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exit 1
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fi
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###############################################################################
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# Check if the required files exist #
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###############################################################################
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if [ ! -e $1 ]; then
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echo "Verilog stimulus file $1 doesn't exist"
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exit 1
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fi
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if [ ! -e $2 ]; then
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echo "ROM memory file $2 doesn't exist"
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exit 1
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fi
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if [ ! -e $3 ]; then
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echo "Verilog submit file $3 doesn't exist"
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exit 1
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fi
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###############################################################################
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# Start verilog simulation #
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###############################################################################
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rm -rf simv
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iverilog -o simv -c $3
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./simv
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