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olivier.gi |
#!/bin/bash
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olivier.gi |
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olivier.gi |
# Disable waveform dumping
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OMSP_NODUMP=1
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export OMSP_NODUMP
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# Choose GCC toolchain prefix ('msp430' for MSPGCC / 'msp430-elf' for GCC RedHat/TI)
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# Note: default to MSPGCC until GCC RedHat/TI is mature enough
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if command -v msp430-gcc >/dev/null; then
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MSPGCC_PFX=msp430
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else
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MSPGCC_PFX=msp430-elf
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fi
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#MSPGCC_PFX=msp430
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export MSPGCC_PFX
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# Choose simulator:
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# - iverilog : Icarus Verilog (default)
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# - cver : CVer
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# - verilog : Verilog-XL
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# - ncverilog : NC-Verilog
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# - vcs : VCS
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# - vsim : Modelsim
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# - isim : Xilinx simulator
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OMSP_SIMULATOR=iverilog
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export OMSP_SIMULATOR
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# Argument specifies number of regression loops
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if [ $# -ne 1 ]; then
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LAST_REGRESSION=0
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else
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LAST_REGRESSION=$(($1-1))
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fi
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# Cleanup from previous regression
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LOG_DIR=./log
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rm -rf $LOG_DIR/*
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# Perform the regression runs
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for (( ii=0; ii<=$LAST_REGRESSION; ii++ ))
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do
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# Cleanup & log directory setup
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rm -rf ./cov_work
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LOG_DIR=./log/$ii
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mkdir -p $LOG_DIR
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# Two-Operand Arithmetic test patterns
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../bin/msp430sim two-op_mov | tee $LOG_DIR/two-op_mov.log
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../bin/msp430sim two-op_mov-b | tee $LOG_DIR/two-op_mov-b.log
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../bin/msp430sim two-op_add | tee $LOG_DIR/two-op_add.log
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../bin/msp430sim two-op_add-b | tee $LOG_DIR/two-op_add-b.log
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../bin/msp430sim two-op_addc | tee $LOG_DIR/two-op_addc.log
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../bin/msp430sim two-op_sub | tee $LOG_DIR/two-op_sub.log
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../bin/msp430sim two-op_subc | tee $LOG_DIR/two-op_subc.log
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../bin/msp430sim two-op_cmp | tee $LOG_DIR/two-op_cmp.log
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../bin/msp430sim two-op_bit | tee $LOG_DIR/two-op_bit.log
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../bin/msp430sim two-op_bic | tee $LOG_DIR/two-op_bic.log
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../bin/msp430sim two-op_bis | tee $LOG_DIR/two-op_bis.log
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../bin/msp430sim two-op_xor | tee $LOG_DIR/two-op_xor.log
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../bin/msp430sim two-op_and | tee $LOG_DIR/two-op_and.log
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../bin/msp430sim two-op_dadd | tee $LOG_DIR/two-op_dadd.log
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../bin/msp430sim two-op_autoincr | tee $LOG_DIR/two-op_autoincr.log
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../bin/msp430sim two-op_autoincr-b | tee $LOG_DIR/two-op_autoincr-b.log
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# Conditional Jump test patterns
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../bin/msp430sim c-jump_jeq | tee $LOG_DIR/c-jump_jeq.log
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../bin/msp430sim c-jump_jne | tee $LOG_DIR/c-jump_jne.log
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../bin/msp430sim c-jump_jc | tee $LOG_DIR/c-jump_jc.log
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../bin/msp430sim c-jump_jnc | tee $LOG_DIR/c-jump_jnc.log
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../bin/msp430sim c-jump_jn | tee $LOG_DIR/c-jump_jn.log
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../bin/msp430sim c-jump_jge | tee $LOG_DIR/c-jump_jge.log
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../bin/msp430sim c-jump_jl | tee $LOG_DIR/c-jump_jl.log
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../bin/msp430sim c-jump_jmp | tee $LOG_DIR/c-jump_jmp.log
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# Single-Operand Arithmetic test patterns
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../bin/msp430sim sing-op_rrc | tee $LOG_DIR/sing-op_rrc.log
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../bin/msp430sim sing-op_rra | tee $LOG_DIR/sing-op_rra.log
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../bin/msp430sim sing-op_swpb | tee $LOG_DIR/sing-op_swpb.log
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../bin/msp430sim sing-op_sxt | tee $LOG_DIR/sing-op_sxt.log
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../bin/msp430sim sing-op_push | tee $LOG_DIR/sing-op_push.log
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../bin/msp430sim sing-op_call | tee $LOG_DIR/sing-op_call.log
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# Interrupts & NMI
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../bin/msp430sim sing-op_reti | tee $LOG_DIR/sing-op_reti.log
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../bin/msp430sim nmi | tee $LOG_DIR/nmi.log
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../bin/msp430sim irq32 | tee $LOG_DIR/irq32.log
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../bin/msp430sim irq64 | tee $LOG_DIR/irq64.log
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# ROM Data Read access
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../bin/msp430sim two-op_add_rom-rd | tee $LOG_DIR/two-op_add_rom-rd.log
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../bin/msp430sim sing-op_push_rom-rd | tee $LOG_DIR/sing-op_push_rom-rd.log
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../bin/msp430sim sing-op_call_rom-rd | tee $LOG_DIR/sing-op_call_rom-rd.log
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# Power saving modes (CPUOFF, OSCOFF, SCG0, SCG1)
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../bin/msp430sim op_modes | tee $LOG_DIR/op_modes.log
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../bin/msp430sim op_modes_asic | tee $LOG_DIR/op_modes_asic.log
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../bin/msp430sim lp_modes_asic | tee $LOG_DIR/lp_modes_asic.log
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../bin/msp430sim lp_modes_dbg_asic | tee $LOG_DIR/lp_modes_dbg_asic.log
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# CPU startup conditions
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../bin/msp430sim cpu_startup_asic | tee $LOG_DIR/cpu_startup_asic.log
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# Basic clock module
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../bin/msp430sim clock_module | tee $LOG_DIR/clock_module.log
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../bin/msp430sim clock_module_asic | tee $LOG_DIR/clock_module_asic.log
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../bin/msp430sim clock_module_asic_mclk | tee $LOG_DIR/clock_module_asic_mclk.log
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../bin/msp430sim clock_module_asic_smclk | tee $LOG_DIR/clock_module_asic_smclk.log
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../bin/msp430sim clock_module_asic_lfxt | tee $LOG_DIR/clock_module_asic_lfxt.log
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# Serial Debug Interface (UART)
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../bin/msp430sim dbg_uart | tee $LOG_DIR/dbg_uart.log
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../bin/msp430sim dbg_uart_sync | tee $LOG_DIR/dbg_uart_sync.log
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../bin/msp430sim dbg_uart_cpu | tee $LOG_DIR/dbg_uart_cpu.log
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../bin/msp430sim dbg_uart_mem | tee $LOG_DIR/dbg_uart_mem.log
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../bin/msp430sim dbg_uart_hwbrk0 | tee $LOG_DIR/dbg_uart_hwbrk0.log
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../bin/msp430sim dbg_uart_hwbrk1 | tee $LOG_DIR/dbg_uart_hwbrk1.log
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../bin/msp430sim dbg_uart_hwbrk2 | tee $LOG_DIR/dbg_uart_hwbrk2.log
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../bin/msp430sim dbg_uart_hwbrk3 | tee $LOG_DIR/dbg_uart_hwbrk3.log
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../bin/msp430sim dbg_uart_rdwr | tee $LOG_DIR/dbg_uart_rdwr.log
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../bin/msp430sim dbg_uart_halt_irq | tee $LOG_DIR/dbg_uart_halt_irq.log
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../bin/msp430sim dbg_uart_onoff | tee $LOG_DIR/dbg_uart_onoff.log
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../bin/msp430sim dbg_uart_onoff_asic | tee $LOG_DIR/dbg_uart_onoff_asic.log
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# Serial Debug Interface (I2C)
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../bin/msp430sim dbg_i2c | tee $LOG_DIR/dbg_i2c.log
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../bin/msp430sim dbg_i2c_sync | tee $LOG_DIR/dbg_i2c_sync.log
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../bin/msp430sim dbg_i2c_cpu | tee $LOG_DIR/dbg_i2c_cpu.log
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../bin/msp430sim dbg_i2c_mem | tee $LOG_DIR/dbg_i2c_mem.log
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../bin/msp430sim dbg_i2c_hwbrk0 | tee $LOG_DIR/dbg_i2c_hwbrk0.log
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../bin/msp430sim dbg_i2c_hwbrk1 | tee $LOG_DIR/dbg_i2c_hwbrk1.log
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../bin/msp430sim dbg_i2c_hwbrk2 | tee $LOG_DIR/dbg_i2c_hwbrk2.log
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../bin/msp430sim dbg_i2c_hwbrk3 | tee $LOG_DIR/dbg_i2c_hwbrk3.log
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../bin/msp430sim dbg_i2c_rdwr | tee $LOG_DIR/dbg_i2c_rdwr.log
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../bin/msp430sim dbg_i2c_halt_irq | tee $LOG_DIR/dbg_i2c_halt_irq.log
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../bin/msp430sim dbg_i2c_onoff | tee $LOG_DIR/dbg_i2c_onoff.log
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../bin/msp430sim dbg_i2c_onoff_asic | tee $LOG_DIR/dbg_i2c_onoff_asic.log
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# SFR test patterns
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../bin/msp430sim sfr | tee $LOG_DIR/sfr.log
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# SCAN test patterns (only to increase coverage)
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../bin/msp430sim scan | tee $LOG_DIR/scan.log
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# Watchdog test patterns
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../bin/msp430sim wdt_interval | tee $LOG_DIR/wdt_interval.log
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../bin/msp430sim wdt_watchdog | tee $LOG_DIR/wdt_watchdog.log
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../bin/msp430sim wdt_clkmux | tee $LOG_DIR/wdt_clkmux.log
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../bin/msp430sim wdt_wkup | tee $LOG_DIR/wdt_wkup.log
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# GPIO test patterns
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../bin/msp430sim gpio_rdwr | tee $LOG_DIR/gpio_rdwr.log
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../bin/msp430sim gpio_irq | tee $LOG_DIR/gpio_irq.log
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# Peripheral templates test patterns
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../bin/msp430sim template_periph_8b | tee $LOG_DIR/template_periph_8b.log
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../bin/msp430sim template_periph_16b | tee $LOG_DIR/template_periph_16b.log
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# Timer A patterns
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../bin/msp430sim tA_modes | tee $LOG_DIR/tA_modes.log
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../bin/msp430sim tA_compare | tee $LOG_DIR/tA_compare.log
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../bin/msp430sim tA_output | tee $LOG_DIR/tA_output.log
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../bin/msp430sim tA_capture | tee $LOG_DIR/tA_capture.log
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../bin/msp430sim tA_clkmux | tee $LOG_DIR/tA_clkmux.log
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# DMA Interface
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../bin/msp430sim dma_rdwr_16b | tee $LOG_DIR/dma_rdwr_16b.log
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../bin/msp430sim dma_rdwr_8b | tee $LOG_DIR/dma_rdwr_8b.log
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../bin/msp430sim dma_resp | tee $LOG_DIR/dma_resp.log
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../bin/msp430sim dma_dbg_arbiter | tee $LOG_DIR/dma_dbg_arbiter.log
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../bin/msp430sim dma_lpm0_asic | tee $LOG_DIR/dma_lpm0_asic.log
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../bin/msp430sim dma_lpm1_asic | tee $LOG_DIR/dma_lpm1_asic.log
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../bin/msp430sim dma_lpm2_asic | tee $LOG_DIR/dma_lpm2_asic.log
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../bin/msp430sim dma_lpm3_asic | tee $LOG_DIR/dma_lpm3_asic.log
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../bin/msp430sim dma_lpm4_asic | tee $LOG_DIR/dma_lpm4_asic.log
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# Simple full duplex UART (8N1 protocol)
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#../bin/msp430sim uart | tee $LOG_DIR/uart.log
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# Hardware multiplier test patterns
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../bin/msp430sim mpy_basic | tee $LOG_DIR/mpy_basic.log
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# Report regression results
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../bin/parse_results $LOG_DIR | tee $LOG_DIR/../summary.$ii.log
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done
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if [ $LAST_REGRESSION != 0 ]; then
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../bin/parse_summaries | tee $LOG_DIR/../regressions_summary.log
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fi
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