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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                               CLOCK MODULE                                */
/*---------------------------------------------------------------------------*/
/* Test the clock module:                                                    */
/*                        - Check the ACLK and SMCLK clock generation.       */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 141 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2012-05-05 23:22:06 +0200 (Sat, 05 May 2012) $          */
/*===========================================================================*/
 
.include "pmem_defs.asm"
 
.global main
 
WAIT_FUNC:
        dec r14
        jnz WAIT_FUNC
        ret
 
main:
        mov #DMEM_250, r1       ; # Initialize stack pointer
        mov   #0x0000, &DMEM_200
        mov   #0x0000, r15
 
       /* --------------                ACLK GENERATION             ----------------- */
 
        mov.b  #0x00, &BCSCTL1  ; # Div /1
        mov    #0x0001, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x10, &BCSCTL1  ; # Div /2
        mov    #0x0002, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x20, &BCSCTL1  ; # Div /4
        mov    #0x0003, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x30, &BCSCTL1  ; # Div /8
        mov    #0x0004, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov  #0x1000, r15
 
 
       /* --------------      SMCLK GENERATION - LFXT_CLK INPUT    ----------------- */
 
        mov.b  #0x08, &BCSCTL2  ; # Div /1
        mov    #0x1001, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x0A, &BCSCTL2  ; # Div /2
        mov    #0x1002, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x0C, &BCSCTL2  ; # Div /4
        mov    #0x1003, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x0E, &BCSCTL2  ; # Div /8
        mov    #0x1004, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov  #0x2000, r15
 
 
       /* --------------      SMCLK GENERATION - DCO_CLK INPUT     ----------------- */
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1
        mov    #0x2001, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x02, &BCSCTL2  ; # Div /2
        mov    #0x2002, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x04, &BCSCTL2  ; # Div /4
        mov    #0x2003, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x06, &BCSCTL2  ; # Div /8
        mov    #0x2004, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov  #0x3000, r15
 
 
        /* --------------      CPU ENABLE - CPU_EN INPUT     ----------------- */
 
        mov    #0x0800, r14
        call   #WAIT_FUNC
 
        mov  #0x4000, r15
 
 
        /* --------------      RD/WR ACCESS TO REGISTERS     ----------------- */
 
        mov.b     #0x00, &BCSCTL1
        mov.b     #0x00, &BCSCTL2
        mov.b  &BCSCTL1, r4
        mov.b  &BCSCTL2, r5
 
        mov.b     #0xff, &BCSCTL1
        mov.b  &BCSCTL1, r6
        mov.b  &BCSCTL2, r7
 
        mov.b     #0x00, &BCSCTL1
        mov.b  &BCSCTL1, r8
        mov.b  &BCSCTL2, r9
 
        mov.b     #0xff, &BCSCTL2
        mov.b  &BCSCTL1, r10
        mov.b  &BCSCTL2, r11
 
        mov.b     #0x00, &BCSCTL2
        mov.b  &BCSCTL1, r12
        mov.b  &BCSCTL2, r13
 
 
        mov     #0x5000, r15
        mov     #0x0010, r14
        call    #WAIT_FUNC
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test        ; Interrupt  0 (lowest priority)    
.word end_of_test        ; Interrupt  1                      
.word end_of_test        ; Interrupt  2                      
.word end_of_test        ; Interrupt  3                      
.word end_of_test        ; Interrupt  4                      
.word end_of_test        ; Interrupt  5                      
.word end_of_test        ; Interrupt  6                      
.word end_of_test        ; Interrupt  7                      
.word end_of_test        ; Interrupt  8                      
.word end_of_test        ; Interrupt  9                      
.word end_of_test        ; Interrupt 10                      Watchdog timer
.word end_of_test        ; Interrupt 11                      
.word end_of_test        ; Interrupt 12                      
.word end_of_test        ; Interrupt 13                      
.word end_of_test        ; Interrupt 14                      NMI
.word main               ; Interrupt 15 (highest priority)   RESET

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* CLOCK MODULE */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the clock module: */`
27			`/* - Check the ACLK and SMCLK clock generation. */`
28	18	olivier.gi	`/* */`
29			`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32			`/---------------------------------------------------------------------------/`
33	19	olivier.gi	`/* $Rev: 141 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2012-05-05 23:22:06 +0200 (Sat, 05 May 2012) $ */`
36	2	olivier.gi	`/===========================================================================/`
37
38	141	olivier.gi	`.include "pmem_defs.asm"`
39
40	2	olivier.gi	`.global main`
41
42			`WAIT_FUNC:`
43			`dec r14`
44			`jnz WAIT_FUNC`
45			`ret`
46
47			`main:`
48	111	olivier.gi	`mov #DMEM_250, r1 ; # Initialize stack pointer`
49			`mov #0x0000, &DMEM_200`
50			`mov #0x0000, r15`
51	2	olivier.gi
52			`/* -------------- ACLK GENERATION ----------------- */`
53
54			`mov.b #0x00, &BCSCTL1 ; # Div /1`
55			`mov #0x0001, r15`
56			`mov #0x0130, r14`
57			`call #WAIT_FUNC`
58
59			`mov.b #0x10, &BCSCTL1 ; # Div /2`
60			`mov #0x0002, r15`
61			`mov #0x0130, r14`
62			`call #WAIT_FUNC`
63
64			`mov.b #0x20, &BCSCTL1 ; # Div /4`
65			`mov #0x0003, r15`
66			`mov #0x0130, r14`
67			`call #WAIT_FUNC`
68
69			`mov.b #0x30, &BCSCTL1 ; # Div /8`
70			`mov #0x0004, r15`
71			`mov #0x0130, r14`
72			`call #WAIT_FUNC`
73
74			`mov #0x1000, r15`
75
76
77			`/* -------------- SMCLK GENERATION - LFXT_CLK INPUT ----------------- */`
78
79			`mov.b #0x08, &BCSCTL2 ; # Div /1`
80			`mov #0x1001, r15`
81			`mov #0x0130, r14`
82			`call #WAIT_FUNC`
83
84			`mov.b #0x0A, &BCSCTL2 ; # Div /2`
85			`mov #0x1002, r15`
86			`mov #0x0130, r14`
87			`call #WAIT_FUNC`
88
89			`mov.b #0x0C, &BCSCTL2 ; # Div /4`
90			`mov #0x1003, r15`
91			`mov #0x0130, r14`
92			`call #WAIT_FUNC`
93
94			`mov.b #0x0E, &BCSCTL2 ; # Div /8`
95			`mov #0x1004, r15`
96			`mov #0x0130, r14`
97			`call #WAIT_FUNC`
98
99			`mov #0x2000, r15`
100
101
102			`/* -------------- SMCLK GENERATION - DCO_CLK INPUT ----------------- */`
103
104			`mov.b #0x00, &BCSCTL2 ; # Div /1`
105			`mov #0x2001, r15`
106			`mov #0x0130, r14`
107			`call #WAIT_FUNC`
108
109			`mov.b #0x02, &BCSCTL2 ; # Div /2`
110			`mov #0x2002, r15`
111			`mov #0x0130, r14`
112			`call #WAIT_FUNC`
113
114			`mov.b #0x04, &BCSCTL2 ; # Div /4`
115			`mov #0x2003, r15`
116			`mov #0x0130, r14`
117			`call #WAIT_FUNC`
118
119			`mov.b #0x06, &BCSCTL2 ; # Div /8`
120			`mov #0x2004, r15`
121			`mov #0x0130, r14`
122			`call #WAIT_FUNC`
123
124			`mov #0x3000, r15`
125
126	106	olivier.gi
127			`/* -------------- CPU ENABLE - CPU_EN INPUT ----------------- */`
128
129			`mov #0x0800, r14`
130			`call #WAIT_FUNC`
131
132			`mov #0x4000, r15`
133
134	111	olivier.gi
135			`/* -------------- RD/WR ACCESS TO REGISTERS ----------------- */`
136
137			`mov.b #0x00, &BCSCTL1`
138			`mov.b #0x00, &BCSCTL2`
139			`mov.b &BCSCTL1, r4`
140			`mov.b &BCSCTL2, r5`
141
142			`mov.b #0xff, &BCSCTL1`
143			`mov.b &BCSCTL1, r6`
144			`mov.b &BCSCTL2, r7`
145
146			`mov.b #0x00, &BCSCTL1`
147			`mov.b &BCSCTL1, r8`
148			`mov.b &BCSCTL2, r9`
149
150			`mov.b #0xff, &BCSCTL2`
151			`mov.b &BCSCTL1, r10`
152			`mov.b &BCSCTL2, r11`
153
154			`mov.b #0x00, &BCSCTL2`
155			`mov.b &BCSCTL1, r12`
156			`mov.b &BCSCTL2, r13`
157
158
159			`mov #0x5000, r15`
160			`mov #0x0010, r14`
161			`call #WAIT_FUNC`
162
163
164	2	olivier.gi	`/* ---------------------- END OF TEST --------------- */`
165			`end_of_test:`
166			`nop`
167			`br #0xffff`
168
169
170			`/* ---------------------- INTERRUPT VECTORS --------------- */`
171
172			`.section .vectors, "a"`
173			`.word end_of_test ; Interrupt 0 (lowest priority)`
174			`.word end_of_test ; Interrupt 1`
175			`.word end_of_test ; Interrupt 2`
176			`.word end_of_test ; Interrupt 3`
177			`.word end_of_test ; Interrupt 4`
178			`.word end_of_test ; Interrupt 5`
179			`.word end_of_test ; Interrupt 6`
180			`.word end_of_test ; Interrupt 7`
181			`.word end_of_test ; Interrupt 8`
182			`.word end_of_test ; Interrupt 9`
183			`.word end_of_test ; Interrupt 10 Watchdog timer`
184			`.word end_of_test ; Interrupt 11`
185			`.word end_of_test ; Interrupt 12`
186			`.word end_of_test ; Interrupt 13`
187			`.word end_of_test ; Interrupt 14 NMI`
188			`.word main ; Interrupt 15 (highest priority) RESET`

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module.s43] - Blame information for rev 204