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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module.v] - Blame information for rev 202

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1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                               CLOCK MODULE                                */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the clock module:                                                    */
27 
/*                        - Check the ACLK and SMCLK clock generation.       */
28 18 olivier.gi 
/*                                                                           */
29 
/* Author(s):                                                                */
30 
/*             - Olivier Girard,    olgirard@gmail.com                       */
31 
/*                                                                           */
32 
/*---------------------------------------------------------------------------*/
33 19 olivier.gi 
/* $Rev: 202 $                                                                */
34 
/* $LastChangedBy: olivier.girard $                                          */
35 
/* $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $          */
36 2 olivier.gi 
/*===========================================================================*/
37 
 
38 
`define LONG_TIMEOUT
39 
 
40 
integer mclk_counter;
41 
always @ (negedge mclk)
42 
  mclk_counter <=  mclk_counter+1;
43 
 
44 
integer aclk_counter;
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always @ (negedge mclk)
46 
  if (aclk_en) aclk_counter <=  aclk_counter+1;
47 
 
48 
integer smclk_counter;
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always @ (negedge mclk)
50 
  if (smclk_en) smclk_counter <=  smclk_counter+1;
51 
 
52 106 olivier.gi 
reg [15:0] reg_val;
53 202 olivier.gi 
 
54 2 olivier.gi 
initial
55 
   begin
56 
      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
58 
      $display(" ===============================================");
59 
      repeat(5) @(posedge mclk);
60 
      stimulus_done = 0;
61 
 
62 180 olivier.gi 
`ifdef ASIC_CLOCKING
63 202 olivier.gi 
      tb_skip_finish("|   (this test is not supported in ASIC mode)   |");
64 134 olivier.gi 
`else
65 2 olivier.gi 
 
66 
      // ACLK GENERATION
67 
      //--------------------------------------------------------
68 
 
69 
                                // ------- Divider /1 ----------
70 
      @(r15 === 16'h0001);
71 
      @(negedge aclk_en);
72 
      mclk_counter = 0;
73 
      aclk_counter = 0;
74 
      repeat(735) @(posedge mclk);
75 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) =====");
76 
      if (aclk_counter !== 24)  tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) =====");
77 
 
78 202 olivier.gi 
 
79 2 olivier.gi 
                                // ------- Divider /2 ----------
80 
      @(r15 === 16'h0002);
81 
      @(negedge aclk_en);
82 
      mclk_counter = 0;
83 
      aclk_counter = 0;
84 
      repeat(735) @(posedge mclk);
85 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) =====");
86 
      if (aclk_counter !== 12)  tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) =====");
87 
 
88 202 olivier.gi 
 
89 2 olivier.gi 
                                // ------- Divider /4 ----------
90 
      @(r15 === 16'h0003);
91 
      @(negedge aclk_en);
92 
      mclk_counter = 0;
93 
      aclk_counter = 0;
94 
      repeat(735) @(posedge mclk);
95 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) =====");
96 
      if (aclk_counter !== 6)   tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) =====");
97 202 olivier.gi 
 
98 
 
99 2 olivier.gi 
                                // ------- Divider /8 ----------
100 
      @(r15 === 16'h0004);
101 
      @(negedge aclk_en);
102 
      mclk_counter = 0;
103 
      aclk_counter = 0;
104 
      repeat(735) @(posedge mclk);
105 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) =====");
106 
      if (aclk_counter !== 3)   tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) =====");
107 202 olivier.gi 
 
108 
 
109 2 olivier.gi 
      // SMCLK GENERATION - LFXT_CLK INPUT
110 
      //--------------------------------------------------------
111 
 
112 
                                // ------- Divider /1 ----------
113 
      @(r15 === 16'h1001);
114 
      @(negedge smclk_en);
115 
      mclk_counter = 0;
116 
      smclk_counter = 0;
117 
      repeat(735) @(posedge mclk);
118 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /1) =====");
119 
      if (smclk_counter !== 24) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /1) =====");
120 
 
121 202 olivier.gi 
 
122 2 olivier.gi 
                                // ------- Divider /2 ----------
123 
      @(r15 === 16'h1002);
124 
      @(negedge smclk_en);
125 
      mclk_counter = 0;
126 
      smclk_counter = 0;
127 
      repeat(735) @(posedge mclk);
128 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /2) =====");
129 
      if (smclk_counter !== 12) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /2) =====");
130 
 
131 202 olivier.gi 
 
132 2 olivier.gi 
                                // ------- Divider /4 ----------
133 
      @(r15 === 16'h1003);
134 
      @(negedge smclk_en);
135 
      mclk_counter = 0;
136 
      smclk_counter = 0;
137 
      repeat(735) @(posedge mclk);
138 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /4) =====");
139 
      if (smclk_counter !== 6)  tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /4) =====");
140 202 olivier.gi 
 
141 
 
142 2 olivier.gi 
                                // ------- Divider /8 ----------
143 
      @(r15 === 16'h1004);
144 
      @(negedge smclk_en);
145 
      mclk_counter = 0;
146 
      smclk_counter = 0;
147 
      repeat(735) @(posedge mclk);
148 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /8) =====");
149 
      if (smclk_counter !== 3)  tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /8) =====");
150 
 
151 202 olivier.gi 
 
152 2 olivier.gi 
      // SMCLK GENERATION - DCO_CLK INPUT
153 
      //--------------------------------------------------------
154 
 
155 
                                // ------- Divider /1 ----------
156 
      @(r15 === 16'h2001);
157 
      mclk_counter = 0;
158 
      smclk_counter = 0;
159 
      repeat(600) @(posedge mclk);
160 
      if (mclk_counter !== 600)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) =====");
161 
      if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) =====");
162 
 
163 
                                // ------- Divider /2 ----------
164 
      @(r15 === 16'h2002);
165 
      @(negedge smclk_en);
166 
      mclk_counter = 0;
167 
      smclk_counter = 0;
168 
      repeat(600) @(posedge mclk);
169 
      if (mclk_counter !== 600)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) =====");
170 
      if (smclk_counter !== 300) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) =====");
171 
 
172 202 olivier.gi 
 
173 2 olivier.gi 
                                // ------- Divider /4 ----------
174 
      @(r15 === 16'h2003);
175 
      @(negedge smclk_en);
176 
      mclk_counter = 0;
177 
      smclk_counter = 0;
178 
      repeat(600) @(posedge mclk);
179 
      if (mclk_counter !== 600)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) =====");
180 
      if (smclk_counter !== 150) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) =====");
181 202 olivier.gi 
 
182 
 
183 2 olivier.gi 
                                // ------- Divider /8 ----------
184 
      @(r15 === 16'h2004);
185 
      @(negedge smclk_en);
186 
      mclk_counter = 0;
187 
      smclk_counter = 0;
188 
      repeat(600) @(posedge mclk);
189 
      if (mclk_counter !== 600)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) =====");
190 
      if (smclk_counter !== 75)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) =====");
191 106 olivier.gi 
 
192 202 olivier.gi 
 
193 111 olivier.gi 
      // CPU ENABLE - CPU_EN INPUT
194 106 olivier.gi 
      //--------------------------------------------------------
195 
 
196 
      @(r15 === 16'h3000);
197 
      repeat(50) @(posedge mclk);
198 
      if (dbg_freeze    == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");
199 
      cpu_en        = 1'b0;
200 
      repeat(3)   @(posedge mclk);
201 
      reg_val       = r14;           // Read R14 register & initialize aclk/smclk counters
202 
      aclk_counter  = 0;
203 
      smclk_counter = 0;
204 134 olivier.gi 
      repeat(3)   @(posedge mclk);
205 106 olivier.gi 
      if (dbg_freeze    !== 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 2) =====");
206 
 
207 
      repeat(500) @(posedge mclk);   // Make sure that the CPU is stopped
208 
      if (reg_val       !== r14)  tb_error("====== CPU is not stopped (test 3) =====");
209 
      if (aclk_counter  !== 0)    tb_error("====== ACLK is not stopped (test 4) =====");
210 
      if (smclk_counter !== 0)    tb_error("====== SMCLK is not stopped (test 5) =====");
211 
      if (dbg_freeze    !== 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 6) =====");
212 
      cpu_en = 1'b1;
213 
 
214 
      repeat(500) @(posedge mclk);  // Make sure that the CPU runs again
215 
      if (reg_val       == r14)  tb_error("====== CPU is not running (test 7) =====");
216 
      if (aclk_counter  == 0)    tb_error("====== ACLK is not running (test 8) =====");
217 
      if (smclk_counter == 0)    tb_error("====== SMCLK is not running (test 9) =====");
218 
      if (dbg_freeze    == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 10) =====");
219 
 
220 111 olivier.gi 
 
221 
      // RD/WR ACCESS TO REGISTERS
222 
      //--------------------------------------------------------
223 
 
224 
      @(r15 === 16'h5000);
225 
      if (r4  !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 1) =====");
226 
      if (r5  !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 1) =====");
227 
 
228 202 olivier.gi 
  `ifdef DMA_IF_EN
229 
      if (r6  !== 16'h003A) tb_error("====== BCSCTL1 rd/wr access error (test 2) =====");
230 
  `else
231 111 olivier.gi 
      if (r6  !== 16'h0030) tb_error("====== BCSCTL1 rd/wr access error (test 2) =====");
232 202 olivier.gi 
  `endif
233 111 olivier.gi 
      if (r7  !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 2) =====");
234 
 
235 
      if (r8  !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 3) =====");
236 
      if (r9  !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 3) =====");
237 
 
238 
      if (r10 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 4) =====");
239 
      if (r11 !== 16'h000e) tb_error("====== BCSCTL2 rd/wr access error (test 4) =====");
240 
 
241 
      if (r12 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");
242 
      if (r13 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");
243 202 olivier.gi 
 
244 134 olivier.gi 
`endif
245 111 olivier.gi 
 
246 2 olivier.gi 
      stimulus_done = 1;
247 
   end

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