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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module.v] - Blame information for rev 111

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1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
24 
/*                               CLOCK MODULE                                */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the clock module:                                                    */
27 
/*                        - Check the ACLK and SMCLK clock generation.       */
28 18 olivier.gi 
/*                                                                           */
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/* Author(s):                                                                */
30 
/*             - Olivier Girard,    olgirard@gmail.com                       */
31 
/*                                                                           */
32 
/*---------------------------------------------------------------------------*/
33 19 olivier.gi 
/* $Rev: 111 $                                                                */
34 
/* $LastChangedBy: olivier.girard $                                          */
35 
/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $          */
36 2 olivier.gi 
/*===========================================================================*/
37 
 
38 
`define LONG_TIMEOUT
39 
 
40 
integer mclk_counter;
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always @ (negedge mclk)
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  mclk_counter <=  mclk_counter+1;
43 
 
44 
integer aclk_counter;
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always @ (negedge mclk)
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  if (aclk_en) aclk_counter <=  aclk_counter+1;
47 
 
48 
integer smclk_counter;
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always @ (negedge mclk)
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  if (smclk_en) smclk_counter <=  smclk_counter+1;
51 
 
52 106 olivier.gi 
reg [15:0] reg_val;
53 
 
54 2 olivier.gi 
initial
55 
   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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      repeat(5) @(posedge mclk);
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      stimulus_done = 0;
61 
 
62 
 
63 
      // ACLK GENERATION
64 
      //--------------------------------------------------------
65 
 
66 
                                // ------- Divider /1 ----------
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      @(r15 === 16'h0001);
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      @(negedge aclk_en);
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      mclk_counter = 0;
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      aclk_counter = 0;
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      repeat(735) @(posedge mclk);
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      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) =====");
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      if (aclk_counter !== 24)  tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) =====");
74 
 
75 
 
76 
                                // ------- Divider /2 ----------
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      @(r15 === 16'h0002);
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      @(negedge aclk_en);
79 
      mclk_counter = 0;
80 
      aclk_counter = 0;
81 
      repeat(735) @(posedge mclk);
82 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) =====");
83 
      if (aclk_counter !== 12)  tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) =====");
84 
 
85 
 
86 
                                // ------- Divider /4 ----------
87 
      @(r15 === 16'h0003);
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      @(negedge aclk_en);
89 
      mclk_counter = 0;
90 
      aclk_counter = 0;
91 
      repeat(735) @(posedge mclk);
92 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) =====");
93 
      if (aclk_counter !== 6)   tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) =====");
94 
 
95 
 
96 
                                // ------- Divider /8 ----------
97 
      @(r15 === 16'h0004);
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      @(negedge aclk_en);
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      mclk_counter = 0;
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      aclk_counter = 0;
101 
      repeat(735) @(posedge mclk);
102 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) =====");
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      if (aclk_counter !== 3)   tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) =====");
104 
 
105 
 
106 
      // SMCLK GENERATION - LFXT_CLK INPUT
107 
      //--------------------------------------------------------
108 
 
109 
                                // ------- Divider /1 ----------
110 
      @(r15 === 16'h1001);
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      @(negedge smclk_en);
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      mclk_counter = 0;
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      smclk_counter = 0;
114 
      repeat(735) @(posedge mclk);
115 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /1) =====");
116 
      if (smclk_counter !== 24) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /1) =====");
117 
 
118 
 
119 
                                // ------- Divider /2 ----------
120 
      @(r15 === 16'h1002);
121 
      @(negedge smclk_en);
122 
      mclk_counter = 0;
123 
      smclk_counter = 0;
124 
      repeat(735) @(posedge mclk);
125 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /2) =====");
126 
      if (smclk_counter !== 12) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /2) =====");
127 
 
128 
 
129 
                                // ------- Divider /4 ----------
130 
      @(r15 === 16'h1003);
131 
      @(negedge smclk_en);
132 
      mclk_counter = 0;
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      smclk_counter = 0;
134 
      repeat(735) @(posedge mclk);
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      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /4) =====");
136 
      if (smclk_counter !== 6)  tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /4) =====");
137 
 
138 
 
139 
                                // ------- Divider /8 ----------
140 
      @(r15 === 16'h1004);
141 
      @(negedge smclk_en);
142 
      mclk_counter = 0;
143 
      smclk_counter = 0;
144 
      repeat(735) @(posedge mclk);
145 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /8) =====");
146 
      if (smclk_counter !== 3)  tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /8) =====");
147 
 
148 
 
149 
      // SMCLK GENERATION - DCO_CLK INPUT
150 
      //--------------------------------------------------------
151 
 
152 
                                // ------- Divider /1 ----------
153 
      @(r15 === 16'h2001);
154 
      mclk_counter = 0;
155 
      smclk_counter = 0;
156 
      repeat(600) @(posedge mclk);
157 
      if (mclk_counter !== 600)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) =====");
158 
      if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) =====");
159 
 
160 
                                // ------- Divider /2 ----------
161 
      @(r15 === 16'h2002);
162 
      @(negedge smclk_en);
163 
      mclk_counter = 0;
164 
      smclk_counter = 0;
165 
      repeat(600) @(posedge mclk);
166 
      if (mclk_counter !== 600)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) =====");
167 
      if (smclk_counter !== 300) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) =====");
168 
 
169 
 
170 
                                // ------- Divider /4 ----------
171 
      @(r15 === 16'h2003);
172 
      @(negedge smclk_en);
173 
      mclk_counter = 0;
174 
      smclk_counter = 0;
175 
      repeat(600) @(posedge mclk);
176 
      if (mclk_counter !== 600)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) =====");
177 
      if (smclk_counter !== 150) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) =====");
178 
 
179 
 
180 
                                // ------- Divider /8 ----------
181 
      @(r15 === 16'h2004);
182 
      @(negedge smclk_en);
183 
      mclk_counter = 0;
184 
      smclk_counter = 0;
185 
      repeat(600) @(posedge mclk);
186 
      if (mclk_counter !== 600)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) =====");
187 
      if (smclk_counter !== 75)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) =====");
188 
 
189 106 olivier.gi 
 
190 111 olivier.gi 
      // CPU ENABLE - CPU_EN INPUT
191 106 olivier.gi 
      //--------------------------------------------------------
192 
 
193 
      @(r15 === 16'h3000);
194 
      repeat(50) @(posedge mclk);
195 
      if (dbg_freeze    == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");
196 
      cpu_en        = 1'b0;
197 
      repeat(3)   @(posedge mclk);
198 
      reg_val       = r14;           // Read R14 register & initialize aclk/smclk counters
199 
      aclk_counter  = 0;
200 
      smclk_counter = 0;
201 
      if (dbg_freeze    !== 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 2) =====");
202 
 
203 
      repeat(500) @(posedge mclk);   // Make sure that the CPU is stopped
204 
      if (reg_val       !== r14)  tb_error("====== CPU is not stopped (test 3) =====");
205 
      if (aclk_counter  !== 0)    tb_error("====== ACLK is not stopped (test 4) =====");
206 
      if (smclk_counter !== 0)    tb_error("====== SMCLK is not stopped (test 5) =====");
207 
      if (dbg_freeze    !== 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 6) =====");
208 
      cpu_en = 1'b1;
209 
 
210 
      repeat(500) @(posedge mclk);  // Make sure that the CPU runs again
211 
      if (reg_val       == r14)  tb_error("====== CPU is not running (test 7) =====");
212 
      if (aclk_counter  == 0)    tb_error("====== ACLK is not running (test 8) =====");
213 
      if (smclk_counter == 0)    tb_error("====== SMCLK is not running (test 9) =====");
214 
      if (dbg_freeze    == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 10) =====");
215 
 
216 111 olivier.gi 
 
217 
      // RD/WR ACCESS TO REGISTERS
218 
      //--------------------------------------------------------
219 
 
220 
      @(r15 === 16'h5000);
221 
      if (r4  !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 1) =====");
222 
      if (r5  !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 1) =====");
223 
 
224 
      if (r6  !== 16'h0030) tb_error("====== BCSCTL1 rd/wr access error (test 2) =====");
225 
      if (r7  !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 2) =====");
226 
 
227 
      if (r8  !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 3) =====");
228 
      if (r9  !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 3) =====");
229 
 
230 
      if (r10 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 4) =====");
231 
      if (r11 !== 16'h000e) tb_error("====== BCSCTL2 rd/wr access error (test 4) =====");
232 
 
233 
      if (r12 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");
234 
      if (r13 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");
235 106 olivier.gi 
 
236 111 olivier.gi 
 
237 2 olivier.gi 
      stimulus_done = 1;
238 
   end
239 
 

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