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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module.v] - Blame information for rev 142

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1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
24 
/*                               CLOCK MODULE                                */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the clock module:                                                    */
27 
/*                        - Check the ACLK and SMCLK clock generation.       */
28 18 olivier.gi 
/*                                                                           */
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/* Author(s):                                                                */
30 
/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
32 
/*---------------------------------------------------------------------------*/
33 19 olivier.gi 
/* $Rev: 134 $                                                                */
34 
/* $LastChangedBy: olivier.girard $                                          */
35 
/* $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $          */
36 2 olivier.gi 
/*===========================================================================*/
37 
 
38 
`define LONG_TIMEOUT
39 
 
40 
integer mclk_counter;
41 
always @ (negedge mclk)
42 
  mclk_counter <=  mclk_counter+1;
43 
 
44 
integer aclk_counter;
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always @ (negedge mclk)
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  if (aclk_en) aclk_counter <=  aclk_counter+1;
47 
 
48 
integer smclk_counter;
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always @ (negedge mclk)
50 
  if (smclk_en) smclk_counter <=  smclk_counter+1;
51 
 
52 106 olivier.gi 
reg [15:0] reg_val;
53 
 
54 2 olivier.gi 
initial
55 
   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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      repeat(5) @(posedge mclk);
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      stimulus_done = 0;
61 
 
62 134 olivier.gi 
`ifdef ASIC
63 
      $display(" ===============================================");
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      $display("|               SIMULATION SKIPPED              |");
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      $display("|   (this test is not supported in ASIC mode)   |");
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      $display(" ===============================================");
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      $finish;
68 
`else
69 2 olivier.gi 
 
70 
      // ACLK GENERATION
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      //--------------------------------------------------------
72 
 
73 
                                // ------- Divider /1 ----------
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      @(r15 === 16'h0001);
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      @(negedge aclk_en);
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      mclk_counter = 0;
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      aclk_counter = 0;
78 
      repeat(735) @(posedge mclk);
79 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) =====");
80 
      if (aclk_counter !== 24)  tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) =====");
81 
 
82 
 
83 
                                // ------- Divider /2 ----------
84 
      @(r15 === 16'h0002);
85 
      @(negedge aclk_en);
86 
      mclk_counter = 0;
87 
      aclk_counter = 0;
88 
      repeat(735) @(posedge mclk);
89 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) =====");
90 
      if (aclk_counter !== 12)  tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) =====");
91 
 
92 
 
93 
                                // ------- Divider /4 ----------
94 
      @(r15 === 16'h0003);
95 
      @(negedge aclk_en);
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      mclk_counter = 0;
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      aclk_counter = 0;
98 
      repeat(735) @(posedge mclk);
99 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) =====");
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      if (aclk_counter !== 6)   tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) =====");
101 
 
102 
 
103 
                                // ------- Divider /8 ----------
104 
      @(r15 === 16'h0004);
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      @(negedge aclk_en);
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      mclk_counter = 0;
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      aclk_counter = 0;
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      repeat(735) @(posedge mclk);
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      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) =====");
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      if (aclk_counter !== 3)   tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) =====");
111 
 
112 
 
113 
      // SMCLK GENERATION - LFXT_CLK INPUT
114 
      //--------------------------------------------------------
115 
 
116 
                                // ------- Divider /1 ----------
117 
      @(r15 === 16'h1001);
118 
      @(negedge smclk_en);
119 
      mclk_counter = 0;
120 
      smclk_counter = 0;
121 
      repeat(735) @(posedge mclk);
122 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /1) =====");
123 
      if (smclk_counter !== 24) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /1) =====");
124 
 
125 
 
126 
                                // ------- Divider /2 ----------
127 
      @(r15 === 16'h1002);
128 
      @(negedge smclk_en);
129 
      mclk_counter = 0;
130 
      smclk_counter = 0;
131 
      repeat(735) @(posedge mclk);
132 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /2) =====");
133 
      if (smclk_counter !== 12) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /2) =====");
134 
 
135 
 
136 
                                // ------- Divider /4 ----------
137 
      @(r15 === 16'h1003);
138 
      @(negedge smclk_en);
139 
      mclk_counter = 0;
140 
      smclk_counter = 0;
141 
      repeat(735) @(posedge mclk);
142 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /4) =====");
143 
      if (smclk_counter !== 6)  tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /4) =====");
144 
 
145 
 
146 
                                // ------- Divider /8 ----------
147 
      @(r15 === 16'h1004);
148 
      @(negedge smclk_en);
149 
      mclk_counter = 0;
150 
      smclk_counter = 0;
151 
      repeat(735) @(posedge mclk);
152 
      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /8) =====");
153 
      if (smclk_counter !== 3)  tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /8) =====");
154 
 
155 
 
156 
      // SMCLK GENERATION - DCO_CLK INPUT
157 
      //--------------------------------------------------------
158 
 
159 
                                // ------- Divider /1 ----------
160 
      @(r15 === 16'h2001);
161 
      mclk_counter = 0;
162 
      smclk_counter = 0;
163 
      repeat(600) @(posedge mclk);
164 
      if (mclk_counter !== 600)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) =====");
165 
      if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) =====");
166 
 
167 
                                // ------- Divider /2 ----------
168 
      @(r15 === 16'h2002);
169 
      @(negedge smclk_en);
170 
      mclk_counter = 0;
171 
      smclk_counter = 0;
172 
      repeat(600) @(posedge mclk);
173 
      if (mclk_counter !== 600)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) =====");
174 
      if (smclk_counter !== 300) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) =====");
175 
 
176 
 
177 
                                // ------- Divider /4 ----------
178 
      @(r15 === 16'h2003);
179 
      @(negedge smclk_en);
180 
      mclk_counter = 0;
181 
      smclk_counter = 0;
182 
      repeat(600) @(posedge mclk);
183 
      if (mclk_counter !== 600)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) =====");
184 
      if (smclk_counter !== 150) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) =====");
185 
 
186 
 
187 
                                // ------- Divider /8 ----------
188 
      @(r15 === 16'h2004);
189 
      @(negedge smclk_en);
190 
      mclk_counter = 0;
191 
      smclk_counter = 0;
192 
      repeat(600) @(posedge mclk);
193 
      if (mclk_counter !== 600)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) =====");
194 
      if (smclk_counter !== 75)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) =====");
195 
 
196 106 olivier.gi 
 
197 111 olivier.gi 
      // CPU ENABLE - CPU_EN INPUT
198 106 olivier.gi 
      //--------------------------------------------------------
199 
 
200 
      @(r15 === 16'h3000);
201 
      repeat(50) @(posedge mclk);
202 
      if (dbg_freeze    == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");
203 
      cpu_en        = 1'b0;
204 
      repeat(3)   @(posedge mclk);
205 
      reg_val       = r14;           // Read R14 register & initialize aclk/smclk counters
206 
      aclk_counter  = 0;
207 
      smclk_counter = 0;
208 134 olivier.gi 
      repeat(3)   @(posedge mclk);
209 106 olivier.gi 
      if (dbg_freeze    !== 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 2) =====");
210 
 
211 
      repeat(500) @(posedge mclk);   // Make sure that the CPU is stopped
212 
      if (reg_val       !== r14)  tb_error("====== CPU is not stopped (test 3) =====");
213 
      if (aclk_counter  !== 0)    tb_error("====== ACLK is not stopped (test 4) =====");
214 
      if (smclk_counter !== 0)    tb_error("====== SMCLK is not stopped (test 5) =====");
215 
      if (dbg_freeze    !== 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 6) =====");
216 
      cpu_en = 1'b1;
217 
 
218 
      repeat(500) @(posedge mclk);  // Make sure that the CPU runs again
219 
      if (reg_val       == r14)  tb_error("====== CPU is not running (test 7) =====");
220 
      if (aclk_counter  == 0)    tb_error("====== ACLK is not running (test 8) =====");
221 
      if (smclk_counter == 0)    tb_error("====== SMCLK is not running (test 9) =====");
222 
      if (dbg_freeze    == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 10) =====");
223 
 
224 111 olivier.gi 
 
225 
      // RD/WR ACCESS TO REGISTERS
226 
      //--------------------------------------------------------
227 
 
228 
      @(r15 === 16'h5000);
229 
      if (r4  !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 1) =====");
230 
      if (r5  !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 1) =====");
231 
 
232 
      if (r6  !== 16'h0030) tb_error("====== BCSCTL1 rd/wr access error (test 2) =====");
233 
      if (r7  !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 2) =====");
234 
 
235 
      if (r8  !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 3) =====");
236 
      if (r9  !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 3) =====");
237 
 
238 
      if (r10 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 4) =====");
239 
      if (r11 !== 16'h000e) tb_error("====== BCSCTL2 rd/wr access error (test 4) =====");
240 
 
241 
      if (r12 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");
242 
      if (r13 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");
243 106 olivier.gi 
 
244 134 olivier.gi 
`endif
245 111 olivier.gi 
 
246 2 olivier.gi 
      stimulus_done = 1;
247 
   end
248 
 

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