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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module_asic.s43] - Blame information for rev 202

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                               CLOCK MODULE                                */
/*---------------------------------------------------------------------------*/
/* Test the clock module:                                                    */
/*                        - Check the ACLK and SMCLK clock generation.       */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
/*===========================================================================*/
 
.include "pmem_defs.asm"
 
.global main
 
WAIT_FUNC:
        dec r14
        jnz WAIT_FUNC
        ret
 
main:
        mov #DMEM_250, r1       ; # Initialize stack pointer
        mov   #0x0000, &DMEM_200
        mov   #0x0000, r15
 
 
       /* --------------                MCLK GENERATION  - DCO_CLK INPUT   ----------------- */
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1
        mov    #0x0001, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x10, &BCSCTL2  ; # Div /2
        mov    #0x0002, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x20, &BCSCTL2  ; # Div /4
        mov    #0x0003, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x30, &BCSCTL2  ; # Div /8
        mov    #0x0004, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1
        mov    #0x1000, r15
 
 
       /* --------------                MCLK GENERATION  - LFXT_CLK INPUT ----------------- */
 
#       mov.b  #0x80, &BCSCTL2  ; # Div /1
#       mov    #0x1001, r15
#       mov    #0x0130, r14
#        call   #WAIT_FUNC
 
#       mov.b  #0x90, &BCSCTL2  ; # Div /2
#       mov    #0x1002, r15
#       mov    #0x0130, r14
#        call   #WAIT_FUNC
 
#       mov.b  #0xA0, &BCSCTL2  ; # Div /4
#       mov    #0x1003, r15
#       mov    #0x0130, r14
#        call   #WAIT_FUNC
 
#       mov.b  #0xB0, &BCSCTL2  ; # Div /8
#       mov    #0x1004, r15
#       mov    #0x0130, r14
#        call   #WAIT_FUNC
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1
        mov    #0x2000, r15
 
 
       /* --------------                ACLK GENERATION             ----------------- */
 
        mov.b  #0x00, &BCSCTL1  ; # Div /1
        mov    #0x2001, r15
        mov    #0x0230, r14
        call   #WAIT_FUNC
 
        mov.b  #0x10, &BCSCTL1  ; # Div /2
        mov    #0x2002, r15
        mov    #0x0230, r14
        call   #WAIT_FUNC
 
        mov.b  #0x20, &BCSCTL1  ; # Div /4
        mov    #0x2003, r15
        mov    #0x0230, r14
        call   #WAIT_FUNC
 
        mov.b  #0x30, &BCSCTL1  ; # Div /8
        mov    #0x2004, r15
        mov    #0x0230, r14
        call   #WAIT_FUNC
 
        mov.b  #0x00, &BCSCTL1  ; # Div /1
        mov    #0x3000, r15
 
 
       /* --------------      SMCLK GENERATION - DCO_CLK INPUT     ----------------- */
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1
        mov    #0x3001, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x02, &BCSCTL2  ; # Div /2
        mov    #0x3002, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x04, &BCSCTL2  ; # Div /4
        mov    #0x3003, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x06, &BCSCTL2  ; # Div /8
        mov    #0x3004, r15
        mov    #0x0130, r14
        call   #WAIT_FUNC
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1
        mov    #0x4000, r15
 
 
       /* --------------      SMCLK GENERATION - LFXT_CLK INPUT    ----------------- */
 
#       mov.b  #0x08, &BCSCTL2  ; # Div /1
#       mov    #0x4001, r15
#       mov    #0x0130, r14
#        call   #WAIT_FUNC
 
#       mov.b  #0x0A, &BCSCTL2  ; # Div /2
#       mov    #0x4002, r15
#       mov    #0x0130, r14
#        call   #WAIT_FUNC
 
#       mov.b  #0x0C, &BCSCTL2  ; # Div /4
#       mov    #0x4003, r15
#       mov    #0x0130, r14
#        call   #WAIT_FUNC
 
#       mov.b  #0x0E, &BCSCTL2  ; # Div /8
#       mov    #0x4004, r15
#       mov    #0x0130, r14
#        call   #WAIT_FUNC
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1
        mov    #0x5000, r15
 
 
        /* --------------  CPU ENABLE - CPU_EN INPUT / DBG ENABLE - DBG_EN INPUT  ----------------- */
 
        mov    #0x0800, r14     ; CPU ENABLE
        mov    #0x5001, r15
        call   #WAIT_FUNC
 
        mov    #0x0800, r14     ; DBG ENABLE
        mov    #0x5002, r15
        call   #WAIT_FUNC
 
        mov    #0x6000, r15
 
 
        /* --------------      RD/WR ACCESS TO REGISTERS     ----------------- */
 
        mov.b     #0x00, &BCSCTL1
        mov.b     #0x00, &BCSCTL2
        mov.b  &BCSCTL1, r4
        mov.b  &BCSCTL2, r5
 
        mov.b     #0xff, &BCSCTL1
        mov.b  &BCSCTL1, r6
        mov.b  &BCSCTL2, r7
 
        mov.b     #0x00, &BCSCTL1
        mov.b  &BCSCTL1, r8
        mov.b  &BCSCTL2, r9
 
        mov.b     #0xff, &BCSCTL2
        mov.b  &BCSCTL1, r10
        mov.b  &BCSCTL2, r11
 
        mov.b     #0x00, &BCSCTL2
        mov.b  &BCSCTL1, r12
        mov.b  &BCSCTL2, r13
 
 
        mov     #0x7000, r15
        mov     #0x0010, r14
        call    #WAIT_FUNC
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test        ; Interrupt  0 (lowest priority)    
.word end_of_test        ; Interrupt  1                      
.word end_of_test        ; Interrupt  2                      
.word end_of_test        ; Interrupt  3                      
.word end_of_test        ; Interrupt  4                      
.word end_of_test        ; Interrupt  5                      
.word end_of_test        ; Interrupt  6                      
.word end_of_test        ; Interrupt  7                      
.word end_of_test        ; Interrupt  8                      
.word end_of_test        ; Interrupt  9                      
.word end_of_test        ; Interrupt 10                      Watchdog timer
.word end_of_test        ; Interrupt 11                      
.word end_of_test        ; Interrupt 12                      
.word end_of_test        ; Interrupt 13                      
.word end_of_test        ; Interrupt 14                      NMI
.word main               ; Interrupt 15 (highest priority)   RESET

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module_asic.s43] - Blame information for rev 202

Line No.	Rev	Author	Line
1	134	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* CLOCK MODULE */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the clock module: */`
27			`/* - Check the ACLK and SMCLK clock generation. */`
28			`/* */`
29			`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32			`/---------------------------------------------------------------------------/`
33			`/* $Rev: 19 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */`
36			`/===========================================================================/`
37
38	141	olivier.gi	`.include "pmem_defs.asm"`
39
40	134	olivier.gi	`.global main`
41
42			`WAIT_FUNC:`
43			`dec r14`
44			`jnz WAIT_FUNC`
45			`ret`
46
47			`main:`
48			`mov #DMEM_250, r1 ; # Initialize stack pointer`
49			`mov #0x0000, &DMEM_200`
50			`mov #0x0000, r15`
51
52
53			`/* -------------- MCLK GENERATION - DCO_CLK INPUT ----------------- */`
54
55			`mov.b #0x00, &BCSCTL2 ; # Div /1`
56			`mov #0x0001, r15`
57			`mov #0x0130, r14`
58			`call #WAIT_FUNC`
59
60			`mov.b #0x10, &BCSCTL2 ; # Div /2`
61			`mov #0x0002, r15`
62			`mov #0x0130, r14`
63			`call #WAIT_FUNC`
64
65			`mov.b #0x20, &BCSCTL2 ; # Div /4`
66			`mov #0x0003, r15`
67			`mov #0x0130, r14`
68			`call #WAIT_FUNC`
69
70			`mov.b #0x30, &BCSCTL2 ; # Div /8`
71			`mov #0x0004, r15`
72			`mov #0x0130, r14`
73			`call #WAIT_FUNC`
74
75			`mov.b #0x00, &BCSCTL2 ; # Div /1`
76			`mov #0x1000, r15`
77
78
79			`/* -------------- MCLK GENERATION - LFXT_CLK INPUT ----------------- */`
80
81			`# mov.b #0x80, &BCSCTL2 ; # Div /1`
82			`# mov #0x1001, r15`
83			`# mov #0x0130, r14`
84			`# call #WAIT_FUNC`
85
86			`# mov.b #0x90, &BCSCTL2 ; # Div /2`
87			`# mov #0x1002, r15`
88			`# mov #0x0130, r14`
89			`# call #WAIT_FUNC`
90
91			`# mov.b #0xA0, &BCSCTL2 ; # Div /4`
92			`# mov #0x1003, r15`
93			`# mov #0x0130, r14`
94			`# call #WAIT_FUNC`
95
96			`# mov.b #0xB0, &BCSCTL2 ; # Div /8`
97			`# mov #0x1004, r15`
98			`# mov #0x0130, r14`
99			`# call #WAIT_FUNC`
100
101			`mov.b #0x00, &BCSCTL2 ; # Div /1`
102			`mov #0x2000, r15`
103
104
105			`/* -------------- ACLK GENERATION ----------------- */`
106
107			`mov.b #0x00, &BCSCTL1 ; # Div /1`
108			`mov #0x2001, r15`
109			`mov #0x0230, r14`
110			`call #WAIT_FUNC`
111
112			`mov.b #0x10, &BCSCTL1 ; # Div /2`
113			`mov #0x2002, r15`
114			`mov #0x0230, r14`
115			`call #WAIT_FUNC`
116
117			`mov.b #0x20, &BCSCTL1 ; # Div /4`
118			`mov #0x2003, r15`
119			`mov #0x0230, r14`
120			`call #WAIT_FUNC`
121
122			`mov.b #0x30, &BCSCTL1 ; # Div /8`
123			`mov #0x2004, r15`
124			`mov #0x0230, r14`
125			`call #WAIT_FUNC`
126
127			`mov.b #0x00, &BCSCTL1 ; # Div /1`
128			`mov #0x3000, r15`
129
130
131			`/* -------------- SMCLK GENERATION - DCO_CLK INPUT ----------------- */`
132
133			`mov.b #0x00, &BCSCTL2 ; # Div /1`
134			`mov #0x3001, r15`
135			`mov #0x0130, r14`
136			`call #WAIT_FUNC`
137
138			`mov.b #0x02, &BCSCTL2 ; # Div /2`
139			`mov #0x3002, r15`
140			`mov #0x0130, r14`
141			`call #WAIT_FUNC`
142
143			`mov.b #0x04, &BCSCTL2 ; # Div /4`
144			`mov #0x3003, r15`
145			`mov #0x0130, r14`
146			`call #WAIT_FUNC`
147
148			`mov.b #0x06, &BCSCTL2 ; # Div /8`
149			`mov #0x3004, r15`
150			`mov #0x0130, r14`
151			`call #WAIT_FUNC`
152
153			`mov.b #0x00, &BCSCTL2 ; # Div /1`
154			`mov #0x4000, r15`
155
156
157			`/* -------------- SMCLK GENERATION - LFXT_CLK INPUT ----------------- */`
158
159			`# mov.b #0x08, &BCSCTL2 ; # Div /1`
160			`# mov #0x4001, r15`
161			`# mov #0x0130, r14`
162			`# call #WAIT_FUNC`
163
164			`# mov.b #0x0A, &BCSCTL2 ; # Div /2`
165			`# mov #0x4002, r15`
166			`# mov #0x0130, r14`
167			`# call #WAIT_FUNC`
168
169			`# mov.b #0x0C, &BCSCTL2 ; # Div /4`
170			`# mov #0x4003, r15`
171			`# mov #0x0130, r14`
172			`# call #WAIT_FUNC`
173
174			`# mov.b #0x0E, &BCSCTL2 ; # Div /8`
175			`# mov #0x4004, r15`
176			`# mov #0x0130, r14`
177			`# call #WAIT_FUNC`
178
179			`mov.b #0x00, &BCSCTL2 ; # Div /1`
180			`mov #0x5000, r15`
181
182
183			`/* -------------- CPU ENABLE - CPU_EN INPUT / DBG ENABLE - DBG_EN INPUT ----------------- */`
184
185			`mov #0x0800, r14 ; CPU ENABLE`
186			`mov #0x5001, r15`
187			`call #WAIT_FUNC`
188
189			`mov #0x0800, r14 ; DBG ENABLE`
190			`mov #0x5002, r15`
191			`call #WAIT_FUNC`
192
193			`mov #0x6000, r15`
194
195
196			`/* -------------- RD/WR ACCESS TO REGISTERS ----------------- */`
197
198			`mov.b #0x00, &BCSCTL1`
199			`mov.b #0x00, &BCSCTL2`
200			`mov.b &BCSCTL1, r4`
201			`mov.b &BCSCTL2, r5`
202
203			`mov.b #0xff, &BCSCTL1`
204			`mov.b &BCSCTL1, r6`
205			`mov.b &BCSCTL2, r7`
206
207			`mov.b #0x00, &BCSCTL1`
208			`mov.b &BCSCTL1, r8`
209			`mov.b &BCSCTL2, r9`
210
211			`mov.b #0xff, &BCSCTL2`
212			`mov.b &BCSCTL1, r10`
213			`mov.b &BCSCTL2, r11`
214
215			`mov.b #0x00, &BCSCTL2`
216			`mov.b &BCSCTL1, r12`
217			`mov.b &BCSCTL2, r13`
218
219
220			`mov #0x7000, r15`
221			`mov #0x0010, r14`
222			`call #WAIT_FUNC`
223
224
225			`/* ---------------------- END OF TEST --------------- */`
226			`end_of_test:`
227			`nop`
228			`br #0xffff`
229
230
231			`/* ---------------------- INTERRUPT VECTORS --------------- */`
232
233			`.section .vectors, "a"`
234			`.word end_of_test ; Interrupt 0 (lowest priority)`
235			`.word end_of_test ; Interrupt 1`
236			`.word end_of_test ; Interrupt 2`
237			`.word end_of_test ; Interrupt 3`
238			`.word end_of_test ; Interrupt 4`
239			`.word end_of_test ; Interrupt 5`
240			`.word end_of_test ; Interrupt 6`
241			`.word end_of_test ; Interrupt 7`
242			`.word end_of_test ; Interrupt 8`
243			`.word end_of_test ; Interrupt 9`
244			`.word end_of_test ; Interrupt 10 Watchdog timer`
245			`.word end_of_test ; Interrupt 11`
246			`.word end_of_test ; Interrupt 12`
247			`.word end_of_test ; Interrupt 13`
248			`.word end_of_test ; Interrupt 14 NMI`
249			`.word main ; Interrupt 15 (highest priority) RESET`