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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module_asic.s43] - Blame information for rev 219

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Line No. Rev Author Line
1 134 olivier.gi
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                               CLOCK MODULE                                */
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/*---------------------------------------------------------------------------*/
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/* Test the clock module:                                                    */
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/*                        - Check the ACLK and SMCLK clock generation.       */
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/*                                                                           */
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/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 19 $                                                                */
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/* $LastChangedBy: olivier.girard $                                          */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
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/*===========================================================================*/
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38 141 olivier.gi
.include "pmem_defs.asm"
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40 134 olivier.gi
.global main
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WAIT_FUNC:
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        dec r14
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        jnz WAIT_FUNC
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        ret
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47
main:
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        mov #DMEM_250, r1       ; # Initialize stack pointer
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        mov   #0x0000, &DMEM_200
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        mov   #0x0000, r15
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52
 
53
       /* --------------                MCLK GENERATION  - DCO_CLK INPUT   ----------------- */
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        mov.b  #0x00, &BCSCTL2  ; # Div /1
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        mov    #0x0001, r15
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        mov    #0x0130, r14
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        call   #WAIT_FUNC
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60
        mov.b  #0x10, &BCSCTL2  ; # Div /2
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        mov    #0x0002, r15
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        mov    #0x0130, r14
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        call   #WAIT_FUNC
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65
        mov.b  #0x20, &BCSCTL2  ; # Div /4
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        mov    #0x0003, r15
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        mov    #0x0130, r14
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        call   #WAIT_FUNC
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        mov.b  #0x30, &BCSCTL2  ; # Div /8
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        mov    #0x0004, r15
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        mov    #0x0130, r14
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        call   #WAIT_FUNC
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        mov.b  #0x00, &BCSCTL2  ; # Div /1
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        mov    #0x1000, r15
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       /* --------------                MCLK GENERATION  - LFXT_CLK INPUT ----------------- */
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#       mov.b  #0x80, &BCSCTL2  ; # Div /1
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#       mov    #0x1001, r15
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#       mov    #0x0130, r14
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#        call   #WAIT_FUNC
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#       mov.b  #0x90, &BCSCTL2  ; # Div /2
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#       mov    #0x1002, r15
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#       mov    #0x0130, r14
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#        call   #WAIT_FUNC
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#       mov.b  #0xA0, &BCSCTL2  ; # Div /4
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#       mov    #0x1003, r15
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#       mov    #0x0130, r14
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#        call   #WAIT_FUNC
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#       mov.b  #0xB0, &BCSCTL2  ; # Div /8
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#       mov    #0x1004, r15
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#       mov    #0x0130, r14
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#        call   #WAIT_FUNC
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        mov.b  #0x00, &BCSCTL2  ; # Div /1
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        mov    #0x2000, r15
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       /* --------------                ACLK GENERATION             ----------------- */
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        mov.b  #0x00, &BCSCTL1  ; # Div /1
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        mov    #0x2001, r15
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        mov    #0x0230, r14
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        call   #WAIT_FUNC
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        mov.b  #0x10, &BCSCTL1  ; # Div /2
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        mov    #0x2002, r15
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        mov    #0x0230, r14
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        call   #WAIT_FUNC
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        mov.b  #0x20, &BCSCTL1  ; # Div /4
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        mov    #0x2003, r15
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        mov    #0x0230, r14
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        call   #WAIT_FUNC
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        mov.b  #0x30, &BCSCTL1  ; # Div /8
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        mov    #0x2004, r15
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        mov    #0x0230, r14
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        call   #WAIT_FUNC
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        mov.b  #0x00, &BCSCTL1  ; # Div /1
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        mov    #0x3000, r15
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       /* --------------      SMCLK GENERATION - DCO_CLK INPUT     ----------------- */
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        mov.b  #0x00, &BCSCTL2  ; # Div /1
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        mov    #0x3001, r15
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        mov    #0x0130, r14
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        call   #WAIT_FUNC
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        mov.b  #0x02, &BCSCTL2  ; # Div /2
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        mov    #0x3002, r15
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        mov    #0x0130, r14
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        call   #WAIT_FUNC
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        mov.b  #0x04, &BCSCTL2  ; # Div /4
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        mov    #0x3003, r15
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        mov    #0x0130, r14
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        call   #WAIT_FUNC
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        mov.b  #0x06, &BCSCTL2  ; # Div /8
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        mov    #0x3004, r15
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        mov    #0x0130, r14
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        call   #WAIT_FUNC
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        mov.b  #0x00, &BCSCTL2  ; # Div /1
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        mov    #0x4000, r15
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       /* --------------      SMCLK GENERATION - LFXT_CLK INPUT    ----------------- */
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#       mov.b  #0x08, &BCSCTL2  ; # Div /1
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#       mov    #0x4001, r15
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#       mov    #0x0130, r14
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#        call   #WAIT_FUNC
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#       mov.b  #0x0A, &BCSCTL2  ; # Div /2
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#       mov    #0x4002, r15
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#       mov    #0x0130, r14
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#        call   #WAIT_FUNC
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#       mov.b  #0x0C, &BCSCTL2  ; # Div /4
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#       mov    #0x4003, r15
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#       mov    #0x0130, r14
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#        call   #WAIT_FUNC
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#       mov.b  #0x0E, &BCSCTL2  ; # Div /8
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#       mov    #0x4004, r15
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#       mov    #0x0130, r14
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#        call   #WAIT_FUNC
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        mov.b  #0x00, &BCSCTL2  ; # Div /1
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        mov    #0x5000, r15
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        /* --------------  CPU ENABLE - CPU_EN INPUT / DBG ENABLE - DBG_EN INPUT  ----------------- */
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        mov    #0x0800, r14     ; CPU ENABLE
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        mov    #0x5001, r15
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        call   #WAIT_FUNC
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        mov    #0x0800, r14     ; DBG ENABLE
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        mov    #0x5002, r15
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        call   #WAIT_FUNC
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        mov    #0x6000, r15
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        /* --------------      RD/WR ACCESS TO REGISTERS     ----------------- */
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        mov.b     #0x00, &BCSCTL1
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        mov.b     #0x00, &BCSCTL2
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        mov.b  &BCSCTL1, r4
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        mov.b  &BCSCTL2, r5
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        mov.b     #0xff, &BCSCTL1
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        mov.b  &BCSCTL1, r6
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        mov.b  &BCSCTL2, r7
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        mov.b     #0x00, &BCSCTL1
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        mov.b  &BCSCTL1, r8
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        mov.b  &BCSCTL2, r9
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        mov.b     #0xff, &BCSCTL2
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        mov.b  &BCSCTL1, r10
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        mov.b  &BCSCTL2, r11
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        mov.b     #0x00, &BCSCTL2
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        mov.b  &BCSCTL1, r12
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        mov.b  &BCSCTL2, r13
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219
 
220
        mov     #0x7000, r15
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        mov     #0x0010, r14
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        call    #WAIT_FUNC
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        /* ----------------------         END OF TEST        --------------- */
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end_of_test:
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        nop
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        br #0xffff
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        /* ----------------------         INTERRUPT VECTORS  --------------- */
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.section .vectors, "a"
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.word end_of_test        ; Interrupt  0 (lowest priority)    
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.word end_of_test        ; Interrupt  1                      
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.word end_of_test        ; Interrupt  2                      
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.word end_of_test        ; Interrupt  3                      
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.word end_of_test        ; Interrupt  4                      
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.word end_of_test        ; Interrupt  5                      
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.word end_of_test        ; Interrupt  6                      
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.word end_of_test        ; Interrupt  7                      
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.word end_of_test        ; Interrupt  8                      
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.word end_of_test        ; Interrupt  9                      
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.word end_of_test        ; Interrupt 10                      Watchdog timer
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.word end_of_test        ; Interrupt 11                      
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.word end_of_test        ; Interrupt 12                      
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.word end_of_test        ; Interrupt 13                      
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.word end_of_test        ; Interrupt 14                      NMI
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.word main               ; Interrupt 15 (highest priority)   RESET

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