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olivier.gi |
/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/*===========================================================================*/
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/* CLOCK MODULE */
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/*---------------------------------------------------------------------------*/
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/* Test the clock module: */
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/* - Check the ACLK and SMCLK clock generation. */
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/* */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 19 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
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/*===========================================================================*/
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`define LONG_TIMEOUT
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integer dco_clk_counter;
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always @ (negedge dco_clk)
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dco_clk_counter <= dco_clk_counter+1;
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integer lfxt_clk_counter;
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always @ (negedge lfxt_clk)
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lfxt_clk_counter <= lfxt_clk_counter+1;
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integer mclk_counter;
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always @ (posedge mclk)
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mclk_counter <= mclk_counter+1;
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integer aclk_counter;
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always @ (negedge aclk)
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aclk_counter <= aclk_counter+1;
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integer smclk_counter;
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always @ (negedge smclk)
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smclk_counter <= smclk_counter+1;
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integer dbg_clk_counter;
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always @ (negedge dbg_clk)
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dbg_clk_counter <= dbg_clk_counter+1;
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reg [15:0] reg_val;
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reg [15:0] bcsctl1_mask;
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reg [15:0] bcsctl2_mask;
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olivier.gi |
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olivier.gi |
initial
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begin
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$display(" ===============================================");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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repeat(5) @(posedge mclk);
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stimulus_done = 0;
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force tb_openMSP430.dut.wdt_reset = 1'b0;
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olivier.gi |
`ifdef ASIC_CLOCKING
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olivier.gi |
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// MCLK GENERATION: SELECTING DCO_CLK
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//--------------------------------------------------------
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// ------- Divider /1 ----------
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@(r15 === 16'h0001);
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@(posedge mclk);
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#1;
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dco_clk_counter = 0;
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mclk_counter = 0;
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repeat(735) @(posedge dco_clk);
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#1;
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if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
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if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
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olivier.gi |
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`ifdef MCLK_DIVIDER
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// ------- Divider /2 ----------
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@(r15 === 16'h0002);
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@(posedge mclk);
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#1;
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dco_clk_counter = 0;
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mclk_counter = 0;
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repeat(735) @(posedge dco_clk);
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#1;
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if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
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if (mclk_counter !== 367) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
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olivier.gi |
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olivier.gi |
// ------- Divider /4 ----------
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@(r15 === 16'h0003);
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@(posedge mclk);
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#1;
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dco_clk_counter = 0;
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mclk_counter = 0;
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repeat(735) @(posedge dco_clk);
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#1;
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if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
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if (mclk_counter !== 183) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
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olivier.gi |
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olivier.gi |
// ------- Divider /8 ----------
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@(r15 === 16'h0004);
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@(posedge mclk);
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#1;
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dco_clk_counter = 0;
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mclk_counter = 0;
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repeat(735) @(posedge dco_clk);
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#1;
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if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
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if (mclk_counter !== 91) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
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`else
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// ------- Divider /2 ----------
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@(r15 === 16'h0002);
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@(posedge dco_clk);
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#1;
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dco_clk_counter = 0;
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mclk_counter = 0;
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repeat(735) @(posedge dco_clk);
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#1;
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if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
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if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
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olivier.gi |
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olivier.gi |
// ------- Divider /4 ----------
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@(r15 === 16'h0003);
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@(posedge dco_clk);
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#1;
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dco_clk_counter = 0;
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mclk_counter = 0;
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repeat(735) @(posedge dco_clk);
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#1;
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if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
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if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
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olivier.gi |
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olivier.gi |
// ------- Divider /8 ----------
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@(r15 === 16'h0004);
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@(posedge dco_clk);
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#1;
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dco_clk_counter = 0;
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mclk_counter = 0;
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repeat(735) @(posedge dco_clk);
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#1;
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if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
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if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
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`endif
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@(r15 === 16'h1000);
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olivier.gi |
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olivier.gi |
// MCLK GENERATION: SELECTING LFXT_CLK
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//--------------------------------------------------------
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// VERIFICATION DONE IN THE "CLOC_MODULE_ASIC_MCLK" PATTERN
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@(r15 === 16'h2000);
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olivier.gi |
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olivier.gi |
// ACLK GENERATION
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//--------------------------------------------------------
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// ------- Divider /1 ----------
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@(r15 === 16'h2001);
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`ifdef LFXT_DOMAIN
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@(posedge lfxt_clk);
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`else
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@(posedge dco_clk);
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`endif
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#1;
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dco_clk_counter = 0;
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lfxt_clk_counter = 0;
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aclk_counter = 0;
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`ifdef LFXT_DOMAIN
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repeat(54) @(posedge lfxt_clk);
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if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 1 =====");
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if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 2 =====");
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`else
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repeat(54) @(posedge dco_clk);
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#1;
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if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 1 =====");
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if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 2 =====");
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`endif
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olivier.gi |
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olivier.gi |
`ifdef ACLK_DIVIDER
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// ------- Divider /2 ----------
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@(r15 === 16'h2002);
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`ifdef LFXT_DOMAIN
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@(posedge lfxt_clk);
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`else
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@(posedge dco_clk);
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`endif
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#1;
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dco_clk_counter = 0;
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lfxt_clk_counter = 0;
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aclk_counter = 0;
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`ifdef LFXT_DOMAIN
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repeat(54) @(posedge lfxt_clk);
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#1;
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if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
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if (aclk_counter !== 28) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
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`else
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repeat(54) @(posedge dco_clk);
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#1;
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if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
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if (aclk_counter !== 27) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
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`endif
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olivier.gi |
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olivier.gi |
// ------- Divider /4 ----------
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@(r15 === 16'h2003);
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`ifdef LFXT_DOMAIN
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@(posedge lfxt_clk);
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`else
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@(posedge dco_clk);
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`endif
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#1;
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dco_clk_counter = 0;
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lfxt_clk_counter = 0;
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aclk_counter = 0;
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`ifdef LFXT_DOMAIN
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repeat(54) @(posedge lfxt_clk);
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if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
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if (aclk_counter !== 14) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
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`else
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repeat(54) @(posedge dco_clk);
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if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
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if (aclk_counter !== 14) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
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`endif
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202 |
olivier.gi |
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134 |
olivier.gi |
// ------- Divider /8 ----------
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@(r15 === 16'h2004);
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`ifdef LFXT_DOMAIN
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@(posedge lfxt_clk);
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`else
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@(posedge dco_clk);
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`endif
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260 |
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#1;
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dco_clk_counter = 0;
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lfxt_clk_counter = 0;
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aclk_counter = 0;
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`ifdef LFXT_DOMAIN
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repeat(54) @(posedge lfxt_clk);
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if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
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if (aclk_counter !== 7) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
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`else
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269 |
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repeat(54) @(posedge dco_clk);
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if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
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if (aclk_counter !== 7) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
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`endif
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olivier.gi |
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olivier.gi |
`else
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// ------- Divider /2 ----------
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@(r15 === 16'h2002);
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`ifdef LFXT_DOMAIN
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@(posedge lfxt_clk);
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`else
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@(posedge dco_clk);
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`endif
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282 |
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#1;
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dco_clk_counter = 0;
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lfxt_clk_counter = 0;
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285 |
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aclk_counter = 0;
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`ifdef LFXT_DOMAIN
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287 |
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repeat(54) @(posedge lfxt_clk);
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#1;
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if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
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if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
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`else
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292 |
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repeat(54) @(posedge dco_clk);
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#1;
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if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
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if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
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`endif
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297 |
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298 |
202 |
olivier.gi |
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299 |
134 |
olivier.gi |
// ------- Divider /4 ----------
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@(r15 === 16'h2003);
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301 |
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`ifdef LFXT_DOMAIN
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@(posedge lfxt_clk);
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`else
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304 |
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@(posedge dco_clk);
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305 |
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`endif
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306 |
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#1;
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dco_clk_counter = 0;
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308 |
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lfxt_clk_counter = 0;
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309 |
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aclk_counter = 0;
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310 |
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`ifdef LFXT_DOMAIN
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311 |
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repeat(54) @(posedge lfxt_clk);
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312 |
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#1;
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313 |
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if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
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314 |
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if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
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315 |
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`else
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316 |
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repeat(54) @(posedge dco_clk);
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317 |
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#1;
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318 |
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if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
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319 |
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if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
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320 |
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`endif
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321 |
202 |
olivier.gi |
|
322 |
|
|
|
323 |
134 |
olivier.gi |
// ------- Divider /8 ----------
|
324 |
|
|
@(r15 === 16'h2004);
|
325 |
|
|
`ifdef LFXT_DOMAIN
|
326 |
|
|
@(posedge lfxt_clk);
|
327 |
|
|
`else
|
328 |
|
|
@(posedge dco_clk);
|
329 |
|
|
`endif
|
330 |
|
|
#1;
|
331 |
|
|
dco_clk_counter = 0;
|
332 |
|
|
lfxt_clk_counter = 0;
|
333 |
|
|
aclk_counter = 0;
|
334 |
|
|
`ifdef LFXT_DOMAIN
|
335 |
|
|
repeat(54) @(posedge lfxt_clk);
|
336 |
|
|
#1;
|
337 |
|
|
if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
|
338 |
|
|
if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
|
339 |
|
|
`else
|
340 |
|
|
repeat(54) @(posedge dco_clk);
|
341 |
|
|
#1;
|
342 |
|
|
if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
|
343 |
|
|
if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
|
344 |
|
|
`endif
|
345 |
202 |
olivier.gi |
|
346 |
134 |
olivier.gi |
`endif
|
347 |
|
|
|
348 |
|
|
@(r15 === 16'h3000);
|
349 |
|
|
|
350 |
202 |
olivier.gi |
|
351 |
134 |
olivier.gi |
// SMCLK GENERATION - DCO_CLK INPUT
|
352 |
|
|
//--------------------------------------------------------
|
353 |
|
|
|
354 |
|
|
// ------- Divider /1 ----------
|
355 |
|
|
@(r15 === 16'h3001);
|
356 |
|
|
@(posedge dco_clk);
|
357 |
|
|
#1;
|
358 |
|
|
dco_clk_counter = 0;
|
359 |
|
|
smclk_counter = 0;
|
360 |
|
|
repeat(600) @(posedge dco_clk);
|
361 |
|
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
|
362 |
|
|
if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
|
363 |
|
|
|
364 |
|
|
`ifdef SMCLK_DIVIDER
|
365 |
|
|
// ------- Divider /2 ----------
|
366 |
|
|
@(r15 === 16'h3002);
|
367 |
|
|
@(posedge dco_clk);
|
368 |
|
|
#1;
|
369 |
|
|
dco_clk_counter = 0;
|
370 |
|
|
smclk_counter = 0;
|
371 |
|
|
repeat(600) @(posedge dco_clk);
|
372 |
|
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
|
373 |
|
|
if (smclk_counter !== 300) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
|
374 |
|
|
|
375 |
202 |
olivier.gi |
|
376 |
134 |
olivier.gi |
// ------- Divider /4 ----------
|
377 |
|
|
@(r15 === 16'h3003);
|
378 |
|
|
@(posedge dco_clk);
|
379 |
|
|
#1;
|
380 |
|
|
dco_clk_counter = 0;
|
381 |
|
|
smclk_counter = 0;
|
382 |
|
|
repeat(600) @(posedge dco_clk);
|
383 |
|
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
|
384 |
|
|
if (smclk_counter !== 150) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
|
385 |
202 |
olivier.gi |
|
386 |
|
|
|
387 |
134 |
olivier.gi |
// ------- Divider /8 ----------
|
388 |
|
|
@(r15 === 16'h3004);
|
389 |
|
|
@(posedge dco_clk);
|
390 |
|
|
#1;
|
391 |
|
|
dco_clk_counter = 0;
|
392 |
|
|
smclk_counter = 0;
|
393 |
|
|
repeat(600) @(posedge dco_clk);
|
394 |
|
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
|
395 |
|
|
if (smclk_counter !== 75) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
|
396 |
|
|
|
397 |
|
|
`else
|
398 |
|
|
// ------- Divider /2 ----------
|
399 |
|
|
@(r15 === 16'h3002);
|
400 |
|
|
@(posedge dco_clk);
|
401 |
|
|
#1;
|
402 |
|
|
dco_clk_counter = 0;
|
403 |
|
|
smclk_counter = 0;
|
404 |
|
|
repeat(600) @(posedge dco_clk);
|
405 |
|
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
|
406 |
|
|
if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
|
407 |
|
|
|
408 |
202 |
olivier.gi |
|
409 |
134 |
olivier.gi |
// ------- Divider /4 ----------
|
410 |
|
|
@(r15 === 16'h3003);
|
411 |
|
|
@(posedge dco_clk);
|
412 |
|
|
#1;
|
413 |
|
|
dco_clk_counter = 0;
|
414 |
|
|
smclk_counter = 0;
|
415 |
|
|
repeat(600) @(posedge dco_clk);
|
416 |
|
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
|
417 |
|
|
if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
|
418 |
202 |
olivier.gi |
|
419 |
|
|
|
420 |
134 |
olivier.gi |
// ------- Divider /8 ----------
|
421 |
|
|
@(r15 === 16'h3004);
|
422 |
|
|
@(posedge dco_clk);
|
423 |
|
|
#1;
|
424 |
|
|
dco_clk_counter = 0;
|
425 |
|
|
smclk_counter = 0;
|
426 |
|
|
repeat(600) @(posedge dco_clk);
|
427 |
|
|
if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
|
428 |
|
|
if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
|
429 |
|
|
|
430 |
|
|
`endif
|
431 |
|
|
|
432 |
|
|
@(r15 === 16'h4000);
|
433 |
|
|
|
434 |
|
|
|
435 |
|
|
// SMCLK GENERATION - LFXT_CLK INPUT
|
436 |
|
|
//--------------------------------------------------------
|
437 |
|
|
// VERIFICATION DONE IN THE "CLOC_MODULE_ASIC_SMCLK" PATTERN
|
438 |
|
|
@(r15 === 16'h5000);
|
439 |
|
|
|
440 |
|
|
|
441 |
|
|
// CPU ENABLE - CPU_EN INPUT / DBG ENABLE - DBG_EN INPUT
|
442 |
|
|
//--------------------------------------------------------
|
443 |
|
|
|
444 |
|
|
@(r15 === 16'h5001);
|
445 |
|
|
repeat(50) @(negedge dco_clk);
|
446 |
|
|
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");
|
447 |
|
|
cpu_en = 1'b0;
|
448 |
|
|
#(3*763*2);
|
449 |
|
|
reg_val = r14; // Read R14 register & initialize mclk/smclk/aclk counters
|
450 |
|
|
mclk_counter = 0;
|
451 |
|
|
aclk_counter = 0;
|
452 |
|
|
smclk_counter = 0;
|
453 |
|
|
|
454 |
|
|
#(50*500); // Make sure that the CPU is stopped
|
455 |
|
|
if (reg_val !== r14) tb_error("====== CPU is not stopped (test 3) =====");
|
456 |
|
|
if (mclk_counter !== 0) tb_error("====== MCLK is not stopped (test 4) =====");
|
457 |
|
|
`ifdef OSCOFF_EN
|
458 |
|
|
if (aclk_counter !== 0) tb_error("====== ACLK is not stopped (test 5) =====");
|
459 |
|
|
`else
|
460 |
|
|
`ifdef LFXT_DOMAIN
|
461 |
|
|
`ifdef ACLK_DIVIDER
|
462 |
|
|
if (aclk_counter !== 0) tb_error("====== ACLK is running (test 5) =====");
|
463 |
|
|
`else
|
464 |
|
|
if (aclk_counter !== 17) tb_error("====== ACLK is not running (test 5) =====");
|
465 |
|
|
`endif
|
466 |
|
|
`else
|
467 |
|
|
if (aclk_counter !== 0) tb_error("====== ACLK is running (test 5) =====");
|
468 |
|
|
`endif
|
469 |
|
|
`endif
|
470 |
|
|
if (smclk_counter !== 0) tb_error("====== SMCLK is not stopped (test 6) =====");
|
471 |
|
|
cpu_en = 1'b1;
|
472 |
|
|
|
473 |
|
|
#(50*500); // Make sure that the CPU runs again
|
474 |
|
|
if (reg_val == r14) tb_error("====== CPU is not running (test 7) =====");
|
475 |
|
|
if (mclk_counter == 0) tb_error("====== MCLK is not running (test 8) =====");
|
476 |
|
|
if (aclk_counter == 0) tb_error("====== ACLK is not running (test 9) =====");
|
477 |
|
|
if (smclk_counter == 0) tb_error("====== SMCLK is not running (test 10) =====");
|
478 |
|
|
|
479 |
202 |
olivier.gi |
|
480 |
134 |
olivier.gi |
@(r15 === 16'h5002);
|
481 |
|
|
`ifdef DBG_EN
|
482 |
|
|
repeat(50) @(posedge dco_clk);
|
483 |
|
|
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");
|
484 |
|
|
if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 2) =====");
|
485 |
|
|
|
486 |
|
|
dbg_en = 1'b1;
|
487 |
|
|
repeat(6) @(posedge mclk);
|
488 |
|
|
reg_val = r14; // Read R14 register & initialize mclk/smclk/aclk/dbg_clk counters
|
489 |
|
|
mclk_counter = 0;
|
490 |
|
|
aclk_counter = 0;
|
491 |
|
|
smclk_counter = 0;
|
492 |
|
|
dbg_clk_counter = 0;
|
493 |
|
|
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 3) =====");
|
494 |
|
|
if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 4) =====");
|
495 |
|
|
|
496 |
|
|
repeat(500) @(posedge dco_clk); // Make sure that the DBG interface runs
|
497 |
|
|
if (reg_val == r14) tb_error("====== CPU is stopped (test 5) =====");
|
498 |
|
|
if (mclk_counter == 0) tb_error("====== MCLK is stopped (test 6) =====");
|
499 |
|
|
if (aclk_counter == 0) tb_error("====== ACLK is stopped (test 7) =====");
|
500 |
|
|
if (smclk_counter == 0) tb_error("====== SMCLK is stopped (test 8) =====");
|
501 |
|
|
if (dbg_clk_counter == 0) tb_error("====== DBG_CLK is stopped (test 9) =====");
|
502 |
|
|
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 10) =====");
|
503 |
|
|
if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 11) =====");
|
504 |
|
|
|
505 |
|
|
dbg_en = 1'b0;
|
506 |
|
|
repeat(6) @(posedge mclk);
|
507 |
|
|
reg_val = r14; // Read R14 register & initialize mclk/smclk/aclk/dbg_clk counters
|
508 |
|
|
mclk_counter = 0;
|
509 |
|
|
aclk_counter = 0;
|
510 |
|
|
smclk_counter = 0;
|
511 |
|
|
dbg_clk_counter = 0;
|
512 |
|
|
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 12) =====");
|
513 |
|
|
if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 13) =====");
|
514 |
|
|
|
515 |
|
|
repeat(500) @(posedge dco_clk); // Make sure that the DBG interface is stopped
|
516 |
|
|
if (reg_val == r14) tb_error("====== CPU is not running (test 14) =====");
|
517 |
|
|
if (mclk_counter == 0) tb_error("====== MCLK is not running (test 15) =====");
|
518 |
|
|
if (aclk_counter == 0) tb_error("====== ACLK is not running (test 16) =====");
|
519 |
|
|
if (smclk_counter == 0) tb_error("====== SMCLK is not running (test 17) =====");
|
520 |
|
|
if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not stopped (test 18) =====");
|
521 |
|
|
if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 19) =====");
|
522 |
|
|
if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 20) =====");
|
523 |
|
|
|
524 |
|
|
if (r15 !== 16'h5002) tb_error("====== DBG_EN did generate a PUC reset (test 21) =====");
|
525 |
|
|
`endif
|
526 |
|
|
|
527 |
|
|
@(r15 === 16'h6000);
|
528 |
|
|
|
529 |
|
|
|
530 |
|
|
// RD/WR ACCESS TO REGISTERS
|
531 |
|
|
//--------------------------------------------------------
|
532 |
|
|
|
533 |
|
|
bcsctl1_mask = 16'h0000;
|
534 |
|
|
bcsctl2_mask = 16'h0000;
|
535 |
|
|
|
536 |
180 |
olivier.gi |
`ifdef ASIC_CLOCKING
|
537 |
134 |
olivier.gi |
`ifdef ACLK_DIVIDER
|
538 |
|
|
bcsctl1_mask = bcsctl1_mask | 16'h0030;
|
539 |
202 |
olivier.gi |
`endif
|
540 |
|
|
`ifdef DMA_IF_EN
|
541 |
|
|
`ifdef CPUOFF_EN
|
542 |
|
|
bcsctl1_mask = bcsctl1_mask | 16'h0001;
|
543 |
|
|
`endif
|
544 |
|
|
`ifdef OSCOFF_EN
|
545 |
|
|
bcsctl1_mask = bcsctl1_mask | 16'h0002;
|
546 |
|
|
`endif
|
547 |
|
|
`ifdef SCG0_EN
|
548 |
|
|
bcsctl1_mask = bcsctl1_mask | 16'h0004;
|
549 |
|
|
`endif
|
550 |
|
|
`ifdef SCG1_EN
|
551 |
|
|
bcsctl1_mask = bcsctl1_mask | 16'h0008;
|
552 |
|
|
`endif
|
553 |
|
|
`endif
|
554 |
134 |
olivier.gi |
`else
|
555 |
|
|
bcsctl1_mask = bcsctl1_mask | 16'h0030;
|
556 |
|
|
`endif
|
557 |
202 |
olivier.gi |
|
558 |
134 |
olivier.gi |
`ifdef MCLK_MUX
|
559 |
|
|
bcsctl2_mask = bcsctl2_mask | 16'h0080;
|
560 |
|
|
`endif
|
561 |
|
|
`ifdef MCLK_DIVIDER
|
562 |
|
|
bcsctl2_mask = bcsctl2_mask | 16'h0030;
|
563 |
|
|
`endif
|
564 |
180 |
olivier.gi |
`ifdef ASIC_CLOCKING
|
565 |
134 |
olivier.gi |
`ifdef SMCLK_MUX
|
566 |
|
|
bcsctl2_mask = bcsctl2_mask | 16'h0008;
|
567 |
|
|
`endif
|
568 |
|
|
`ifdef SMCLK_DIVIDER
|
569 |
|
|
bcsctl2_mask = bcsctl2_mask | 16'h0006;
|
570 |
|
|
`endif
|
571 |
|
|
`else
|
572 |
|
|
bcsctl2_mask = bcsctl2_mask | 16'h0008;
|
573 |
|
|
bcsctl2_mask = bcsctl2_mask | 16'h0006;
|
574 |
|
|
`endif
|
575 |
|
|
|
576 |
|
|
@(r15 === 16'h7000);
|
577 |
|
|
if (r4 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 1) =====");
|
578 |
|
|
if (r5 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 1) =====");
|
579 |
|
|
|
580 |
|
|
if (r6 !== bcsctl1_mask) tb_error("====== BCSCTL1 rd/wr access error (test 2) =====");
|
581 |
|
|
if (r7 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 2) =====");
|
582 |
|
|
|
583 |
|
|
if (r8 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 3) =====");
|
584 |
|
|
if (r9 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 3) =====");
|
585 |
|
|
|
586 |
|
|
if (r10 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 4) =====");
|
587 |
|
|
if (r11 !== bcsctl2_mask) tb_error("====== BCSCTL2 rd/wr access error (test 4) =====");
|
588 |
|
|
|
589 |
|
|
if (r12 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");
|
590 |
|
|
if (r13 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");
|
591 |
|
|
|
592 |
202 |
olivier.gi |
|
593 |
134 |
olivier.gi |
`else
|
594 |
202 |
olivier.gi |
tb_skip_finish("| (this test is not supported in FPGA mode) |");
|
595 |
134 |
olivier.gi |
`endif
|
596 |
|
|
|
597 |
|
|
stimulus_done = 1;
|
598 |
|
|
end
|