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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module_asic_lfxt.v] - Blame information for rev 178

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                               CLOCK MODULE                                */
/*---------------------------------------------------------------------------*/
/* Test the clock module:                                                    */
/*                        - Check the LFXT wakeup when selected sa MCLK.     */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
/*===========================================================================*/
 
`define LONG_TIMEOUT
 
integer mclk_counter;
always @ (negedge mclk)
  mclk_counter     <=  mclk_counter+1;
 
integer lfxt_clk_counter;
always @ (negedge lfxt_clk)
  lfxt_clk_counter <=  lfxt_clk_counter+1;
 
reg [15:0] reg_val;
 
initial
   begin
      $display(" ===============================================");
      $display("|                 START SIMULATION              |");
      $display(" ===============================================");
      repeat(5) @(posedge mclk);
      stimulus_done = 0;
 
`ifdef ASIC
  `ifdef OSCOFF_EN
     `ifdef MCLK_MUX
 
      //--------------------------------------------------------
      // First make sure CPU runs with LFXT_CLK
      //--------------------------------------------------------
 
      @(r15 === 16'h0001);
      #10;
      mclk_counter     = 0;
      lfxt_clk_counter = 0;
      @(r15 === 16'h0002);
      #10;
      if (mclk_counter     !==  40) tb_error("====== CLOCK GENERATOR: TEST 1 =====");
      if (lfxt_clk_counter !==  40) tb_error("====== CLOCK GENERATOR: TEST 2 =====");
      if (r10              !==  0)  tb_error("====== CLOCK GENERATOR: TEST 3 =====");
 
 
      //--------------------------------------------------------
      // Make sure the CPU stops and LFXT oscillator too
      //--------------------------------------------------------
 
      #10000;
      mclk_counter     = 0;
      lfxt_clk_counter = 0;
      #10000;
      if (mclk_counter     !==  0)  tb_error("====== CLOCK GENERATOR: TEST 4 =====");
      if (lfxt_clk_counter !==  0)  tb_error("====== CLOCK GENERATOR: TEST 5 =====");
      if (r10              !==  0)  tb_error("====== CLOCK GENERATOR: TEST 6 =====");
      #10000;
 
 
      //--------------------------------------------------------
      // Generate IRQ and make sure CPU re-runs with LFXT_CLK
      //--------------------------------------------------------
 
      wkup[0]   = 1'b1;
      @(negedge mclk);
      irq[0]    = 1'b1;
      @(negedge irq_acc[0])
      @(negedge mclk);
      wkup[0]   = 1'b0;
      irq[0]    = 1'b0;
 
      @(r15 === 16'h0003);
      #10;
      mclk_counter     = 0;
      lfxt_clk_counter = 0;
      @(r15 === 16'h0004);
      #10;
      if (mclk_counter     !==  40)        tb_error("====== CLOCK GENERATOR: TEST 7 =====");
      if (lfxt_clk_counter !==  40)        tb_error("====== CLOCK GENERATOR: TEST 8 =====");
      if (r10              !==  16'h5678)  tb_error("====== CLOCK GENERATOR: TEST 9 =====");
 
 
     `else
      $display(" ===============================================");
      $display("|               SIMULATION SKIPPED              |");
      $display("|   (this test requires the MCLK clock mux)     |");
      $display(" ===============================================");
      $finish;
     `endif
  `else
      $display(" ===============================================");
      $display("|               SIMULATION SKIPPED              |");
      $display("|   (this test requires the OSCOFF option)      |");
      $display(" ===============================================");
      $finish;
  `endif
`else
      $display(" ===============================================");
      $display("|               SIMULATION SKIPPED              |");
      $display("|   (this test is not supported in FPGA mode)   |");
      $display(" ===============================================");
      $finish;
`endif
 
      stimulus_done = 1;
   end
 

Line No.	Rev	Author	Line
1	134	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* CLOCK MODULE */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the clock module: */`
27			`/* - Check the LFXT wakeup when selected sa MCLK. */`
28			`/* */`
29			`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32			`/---------------------------------------------------------------------------/`
33			`/* $Rev: 19 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */`
36			`/===========================================================================/`
37
38			`define LONG_TIMEOUT
39
40			`integer mclk_counter;`
41			`always @ (negedge mclk)`
42			`mclk_counter <= mclk_counter+1;`
43
44			`integer lfxt_clk_counter;`
45			`always @ (negedge lfxt_clk)`
46			`lfxt_clk_counter <= lfxt_clk_counter+1;`
47
48			`reg [15:0] reg_val;`
49
50			`initial`
51			`begin`
52			`$display(" ===============================================");`
53			`$display("\| START SIMULATION \|");`
54			`$display(" ===============================================");`
55			`repeat(5) @(posedge mclk);`
56			`stimulus_done = 0;`
57
58			`ifdef ASIC
59			`ifdef OSCOFF_EN
60			`ifdef MCLK_MUX
61
62			`//--------------------------------------------------------`
63			`// First make sure CPU runs with LFXT_CLK`
64			`//--------------------------------------------------------`
65
66			`@(r15 === 16'h0001);`
67			`#10;`
68			`mclk_counter = 0;`
69			`lfxt_clk_counter = 0;`
70			`@(r15 === 16'h0002);`
71			`#10;`
72			`if (mclk_counter !== 40) tb_error("====== CLOCK GENERATOR: TEST 1 =====");`
73			`if (lfxt_clk_counter !== 40) tb_error("====== CLOCK GENERATOR: TEST 2 =====");`
74			`if (r10 !== 0) tb_error("====== CLOCK GENERATOR: TEST 3 =====");`
75
76
77			`//--------------------------------------------------------`
78			`// Make sure the CPU stops and LFXT oscillator too`
79			`//--------------------------------------------------------`
80
81			`#10000;`
82			`mclk_counter = 0;`
83			`lfxt_clk_counter = 0;`
84			`#10000;`
85			`if (mclk_counter !== 0) tb_error("====== CLOCK GENERATOR: TEST 4 =====");`
86			`if (lfxt_clk_counter !== 0) tb_error("====== CLOCK GENERATOR: TEST 5 =====");`
87			`if (r10 !== 0) tb_error("====== CLOCK GENERATOR: TEST 6 =====");`
88			`#10000;`
89
90
91			`//--------------------------------------------------------`
92			`// Generate IRQ and make sure CPU re-runs with LFXT_CLK`
93			`//--------------------------------------------------------`
94
95			`wkup[0] = 1'b1;`
96			`@(negedge mclk);`
97			`irq[0] = 1'b1;`
98			`@(negedge irq_acc[0])`
99			`@(negedge mclk);`
100			`wkup[0] = 1'b0;`
101			`irq[0] = 1'b0;`
102
103			`@(r15 === 16'h0003);`
104			`#10;`
105			`mclk_counter = 0;`
106			`lfxt_clk_counter = 0;`
107			`@(r15 === 16'h0004);`
108			`#10;`
109			`if (mclk_counter !== 40) tb_error("====== CLOCK GENERATOR: TEST 7 =====");`
110			`if (lfxt_clk_counter !== 40) tb_error("====== CLOCK GENERATOR: TEST 8 =====");`
111			`if (r10 !== 16'h5678) tb_error("====== CLOCK GENERATOR: TEST 9 =====");`
112
113
114			`else
115			`$display(" ===============================================");`
116			`$display("\| SIMULATION SKIPPED \|");`
117			`$display("\| (this test requires the MCLK clock mux) \|");`
118			`$display(" ===============================================");`
119			`$finish;`
120			`endif
121			`else
122			`$display(" ===============================================");`
123			`$display("\| SIMULATION SKIPPED \|");`
124			`$display("\| (this test requires the OSCOFF option) \|");`
125			`$display(" ===============================================");`
126			`$finish;`
127			`endif
128			`else
129			`$display(" ===============================================");`
130			`$display("\| SIMULATION SKIPPED \|");`
131			`$display("\| (this test is not supported in FPGA mode) \|");`
132			`$display(" ===============================================");`
133			`$finish;`
134			`endif
135
136			`stimulus_done = 1;`
137			`end`
138

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module_asic_lfxt.v] - Blame information for rev 178