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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module_asic_lfxt.v] - Blame information for rev 219

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Line No. Rev Author Line
1 134 olivier.gi
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                               CLOCK MODULE                                */
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/*---------------------------------------------------------------------------*/
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/* Test the clock module:                                                    */
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/*                        - Check the LFXT wakeup when selected sa MCLK.     */
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/*                                                                           */
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/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 19 $                                                                */
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/* $LastChangedBy: olivier.girard $                                          */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
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/*===========================================================================*/
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`define LONG_TIMEOUT
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integer mclk_counter;
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always @ (negedge mclk)
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  mclk_counter     <=  mclk_counter+1;
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integer lfxt_clk_counter;
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always @ (negedge lfxt_clk)
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  lfxt_clk_counter <=  lfxt_clk_counter+1;
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reg [15:0] reg_val;
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50 134 olivier.gi
initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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      repeat(5) @(posedge mclk);
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      stimulus_done = 0;
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58 180 olivier.gi
`ifdef ASIC_CLOCKING
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  `ifdef OSCOFF_EN
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     `ifdef MCLK_MUX
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62 134 olivier.gi
      //--------------------------------------------------------
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      // First make sure CPU runs with LFXT_CLK
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      //--------------------------------------------------------
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      @(r15 === 16'h0001);
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      #10;
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      mclk_counter     = 0;
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      lfxt_clk_counter = 0;
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      @(r15 === 16'h0002);
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      #10;
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      if (mclk_counter     !==  40) tb_error("====== CLOCK GENERATOR: TEST 1 =====");
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      if (lfxt_clk_counter !==  40) tb_error("====== CLOCK GENERATOR: TEST 2 =====");
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      if (r10              !==  0)  tb_error("====== CLOCK GENERATOR: TEST 3 =====");
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      //--------------------------------------------------------
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      // Make sure the CPU stops and LFXT oscillator too
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      //--------------------------------------------------------
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      #10000;
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      mclk_counter     = 0;
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      lfxt_clk_counter = 0;
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      #10000;
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      if (mclk_counter     !==  0)  tb_error("====== CLOCK GENERATOR: TEST 4 =====");
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      if (lfxt_clk_counter !==  0)  tb_error("====== CLOCK GENERATOR: TEST 5 =====");
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      if (r10              !==  0)  tb_error("====== CLOCK GENERATOR: TEST 6 =====");
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      #10000;
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      //--------------------------------------------------------
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      // Generate IRQ and make sure CPU re-runs with LFXT_CLK
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      //--------------------------------------------------------
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95 200 olivier.gi
      wkup[0]          = 1'b1;
96 134 olivier.gi
      @(negedge mclk);
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      irq[`IRQ_NR-16]  = 1'b1;
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      @(negedge irq_acc[`IRQ_NR-16])
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      @(negedge mclk);
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      wkup[0]          = 1'b0;
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      irq[`IRQ_NR-16]    = 1'b0;
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      @(r15 === 16'h0003);
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      #10;
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      mclk_counter     = 0;
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      lfxt_clk_counter = 0;
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      @(r15 === 16'h0004);
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      #10;
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      if (mclk_counter     !==  40)        tb_error("====== CLOCK GENERATOR: TEST 7 =====");
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      if (lfxt_clk_counter !==  40)        tb_error("====== CLOCK GENERATOR: TEST 8 =====");
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      if (r10              !==  16'h5678)  tb_error("====== CLOCK GENERATOR: TEST 9 =====");
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     `else
115 202 olivier.gi
      tb_skip_finish("|   (this test requires the MCLK clock mux)     |");
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     `endif
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  `else
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      tb_skip_finish("|   (this test requires the OSCOFF option)      |");
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  `endif
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`else
121 202 olivier.gi
      tb_skip_finish("|   (this test is not supported in FPGA mode)   |");
122 134 olivier.gi
`endif
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      stimulus_done = 1;
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   end

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