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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module_asic_mclk.v] - Blame information for rev 219

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1 134 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                               CLOCK MODULE                                */
25
/*---------------------------------------------------------------------------*/
26
/* Test the clock module:                                                    */
27
/*                        - Check the MCLK clock generation.                 */
28
/*                                                                           */
29
/* Author(s):                                                                */
30
/*             - Olivier Girard,    olgirard@gmail.com                       */
31
/*                                                                           */
32
/*---------------------------------------------------------------------------*/
33
/* $Rev: 19 $                                                                */
34
/* $LastChangedBy: olivier.girard $                                          */
35
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
36
/*===========================================================================*/
37
 
38
`define LONG_TIMEOUT
39
 
40
integer mclk_counter;
41
always @ (negedge mclk)
42
  mclk_counter     <=  mclk_counter+1;
43
 
44
integer dco_clk_counter;
45
always @ (negedge dco_clk)
46
  dco_clk_counter  <=  dco_clk_counter+1;
47
 
48
integer lfxt_clk_counter;
49
always @ (negedge lfxt_clk)
50
  lfxt_clk_counter <=  lfxt_clk_counter+1;
51
 
52
reg [15:0] reg_val;
53 202 olivier.gi
 
54 134 olivier.gi
initial
55
   begin
56
      $display(" ===============================================");
57
      $display("|                 START SIMULATION              |");
58
      $display(" ===============================================");
59
      repeat(5) @(posedge mclk);
60
      stimulus_done = 0;
61
 
62
      force tb_openMSP430.dut.wdt_reset = 1'b0;
63
 
64 180 olivier.gi
`ifdef ASIC_CLOCKING
65 202 olivier.gi
 
66 134 olivier.gi
      //--------------------------------------------------------
67
      // MCLK GENERATION - LFXT_CLK INPUT
68
      //--------------------------------------------------------
69
 
70
                                // ------- Divider /1 ----------
71
      @(r15 === 16'h0001);
72
      repeat(2) @(posedge mclk);
73
      mclk_counter     = 0;
74
      lfxt_clk_counter = 0;
75
      dco_clk_counter  = 0;
76
      repeat(15) @(posedge mclk);
77
      if (mclk_counter     !==  15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /1) - TEST 1 =====");
78
  `ifdef MCLK_MUX
79
      if (lfxt_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /1) - TEST 2 =====");
80
  `else
81
      if (dco_clk_counter  !==  15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /1) - TEST 3 =====");
82
  `endif
83
 
84
                                // ------- Divider /2 ----------
85
      @(r15 === 16'h0002);
86
      repeat(2) @(posedge mclk);
87
      mclk_counter     = 0;
88
      lfxt_clk_counter = 0;
89
      dco_clk_counter  = 0;
90
      repeat(15) @(posedge mclk);
91
      if (mclk_counter     !==  15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 1 =====");
92
  `ifdef MCLK_DIVIDER
93
    `ifdef MCLK_MUX
94
      if (lfxt_clk_counter !==  30) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 2 =====");
95
    `else
96
      if (dco_clk_counter  !==  30) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 3 =====");
97
    `endif
98
  `else
99
    `ifdef MCLK_MUX
100
      if (lfxt_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 4 =====");
101
    `else
102
      if (dco_clk_counter  !==  15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 5 =====");
103
    `endif
104
  `endif
105 202 olivier.gi
 
106 134 olivier.gi
                                // ------- Divider /4 ----------
107
      @(r15 === 16'h0003);
108
      repeat(2) @(posedge mclk);
109
      mclk_counter     = 0;
110
      lfxt_clk_counter = 0;
111
      dco_clk_counter  = 0;
112
      repeat(15) @(posedge mclk);
113
      if (mclk_counter     !==  15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 1 =====");
114
  `ifdef MCLK_DIVIDER
115
    `ifdef MCLK_MUX
116
      if (lfxt_clk_counter !==  60) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 2 =====");
117
    `else
118
      if (dco_clk_counter  !==  60) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 3 =====");
119
    `endif
120
  `else
121
    `ifdef MCLK_MUX
122
      if (lfxt_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 4 =====");
123
    `else
124
      if (dco_clk_counter  !==  15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 5 =====");
125
    `endif
126
  `endif
127 202 olivier.gi
 
128 134 olivier.gi
                                // ------- Divider /8 ----------
129
      @(r15 === 16'h0004);
130
      repeat(2) @(posedge mclk);
131
      mclk_counter     = 0;
132
      lfxt_clk_counter = 0;
133
      dco_clk_counter  = 0;
134
      repeat(15) @(posedge mclk);
135
      if (mclk_counter     !==  15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 1 =====");
136
  `ifdef MCLK_DIVIDER
137
    `ifdef MCLK_MUX
138
      if (lfxt_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 2 =====");
139
    `else
140
      if (dco_clk_counter  !== 120) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 3 =====");
141
    `endif
142
  `else
143
    `ifdef MCLK_MUX
144
      if (lfxt_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 4 =====");
145
    `else
146
      if (dco_clk_counter  !==  15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 5 =====");
147
    `endif
148
  `endif
149
 
150 202 olivier.gi
 
151 134 olivier.gi
      //--------------------------------------------------------
152
      // SMCLK GENERATION - DCO_CLK INPUT
153
      //--------------------------------------------------------
154
 
155
                                // ------- Divider /1 ----------
156
      @(r15 === 16'h1001);
157
      repeat(2) @(posedge mclk);
158
      mclk_counter     = 0;
159
      lfxt_clk_counter = 0;
160
      dco_clk_counter  = 0;
161
      repeat(15) @(posedge mclk);
162
      if (mclk_counter    !==  15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
163
      if (dco_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
164
 
165
                                // ------- Divider /2 ----------
166
      @(r15 === 16'h1002);
167
      repeat(2) @(posedge mclk);
168
      mclk_counter     = 0;
169
      lfxt_clk_counter = 0;
170
      dco_clk_counter  = 0;
171
      repeat(15) @(posedge mclk);
172
      if (mclk_counter    !==  15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
173
  `ifdef MCLK_DIVIDER
174
      if (dco_clk_counter !==  30) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
175
  `else
176
      if (dco_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /2) - TEST 3 =====");
177
  `endif
178 202 olivier.gi
 
179 134 olivier.gi
                                // ------- Divider /4 ----------
180
      @(r15 === 16'h1003);
181
      repeat(2) @(posedge mclk);
182
      mclk_counter     = 0;
183
      lfxt_clk_counter = 0;
184
      dco_clk_counter  = 0;
185
      repeat(15) @(posedge mclk);
186
      if (mclk_counter    !==  15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
187
  `ifdef MCLK_DIVIDER
188
      if (dco_clk_counter !==  60) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
189
  `else
190
      if (dco_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /4) - TEST 3 =====");
191
  `endif
192 202 olivier.gi
 
193 134 olivier.gi
                                // ------- Divider /8 ----------
194
      @(r15 === 16'h1004);
195
      repeat(2) @(posedge mclk);
196
      mclk_counter     = 0;
197
      lfxt_clk_counter = 0;
198
      dco_clk_counter  = 0;
199
      repeat(15) @(posedge mclk);
200
      if (mclk_counter    !==  15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
201
  `ifdef MCLK_DIVIDER
202
      if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
203
  `else
204
      if (dco_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /8) - TEST 3 =====");
205
  `endif
206
 
207
 
208
      //--------------------------------------------------------
209
      // MCLK GENERATION - LFXT_CLK INPUT
210
      //--------------------------------------------------------
211
 
212
                                // ------- Divider /1 ----------
213
      @(r15 === 16'h2001);
214
      repeat(2) @(posedge mclk);
215
      mclk_counter     = 0;
216
      lfxt_clk_counter = 0;
217
      dco_clk_counter  = 0;
218
      repeat(15) @(posedge mclk);
219
      if (mclk_counter     !==  15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /1) - TEST 1 =====");
220
  `ifdef MCLK_MUX
221
      if (lfxt_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /1) - TEST 2 =====");
222
  `else
223
      if (dco_clk_counter  !==  15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /1) - TEST 3 =====");
224
  `endif
225
 
226
                                // ------- Divider /2 ----------
227
      @(r15 === 16'h2002);
228
      repeat(2) @(posedge mclk);
229
      mclk_counter     = 0;
230
      lfxt_clk_counter = 0;
231
      dco_clk_counter  = 0;
232
      repeat(15) @(posedge mclk);
233
      if (mclk_counter     !==  15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 1 =====");
234
  `ifdef MCLK_DIVIDER
235
    `ifdef MCLK_MUX
236
      if (lfxt_clk_counter !==  30) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 2 =====");
237
    `else
238
      if (dco_clk_counter  !==  30) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 3 =====");
239
    `endif
240
  `else
241
    `ifdef MCLK_MUX
242
      if (lfxt_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 4 =====");
243
    `else
244
      if (dco_clk_counter  !==  15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 5 =====");
245
    `endif
246
  `endif
247 202 olivier.gi
 
248 134 olivier.gi
                                // ------- Divider /4 ----------
249
      @(r15 === 16'h2003);
250
      repeat(2) @(posedge mclk);
251
      mclk_counter     = 0;
252
      lfxt_clk_counter = 0;
253
      dco_clk_counter  = 0;
254
      repeat(15) @(posedge mclk);
255
      if (mclk_counter     !==  15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 1 =====");
256
  `ifdef MCLK_DIVIDER
257
    `ifdef MCLK_MUX
258
      if (lfxt_clk_counter !==  60) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 2 =====");
259
    `else
260
      if (dco_clk_counter  !==  60) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 3 =====");
261
    `endif
262
  `else
263
    `ifdef MCLK_MUX
264
      if (lfxt_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 4 =====");
265
    `else
266
      if (dco_clk_counter  !==  15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 5 =====");
267
    `endif
268
  `endif
269 202 olivier.gi
 
270 134 olivier.gi
                                // ------- Divider /8 ----------
271
      @(r15 === 16'h2004);
272
      repeat(2) @(posedge mclk);
273
      mclk_counter     = 0;
274
      lfxt_clk_counter = 0;
275
      dco_clk_counter  = 0;
276
      repeat(15) @(posedge mclk);
277
      if (mclk_counter     !==  15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 1 =====");
278
  `ifdef MCLK_DIVIDER
279
    `ifdef MCLK_MUX
280
      if (lfxt_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 2 =====");
281
    `else
282
      if (dco_clk_counter  !== 120) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 3 =====");
283
    `endif
284
  `else
285
    `ifdef MCLK_MUX
286
      if (lfxt_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 4 =====");
287
    `else
288
      if (dco_clk_counter  !==  15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 5 =====");
289
    `endif
290
  `endif
291
 
292 202 olivier.gi
 
293 134 olivier.gi
      //--------------------------------------------------------
294
      // SMCLK GENERATION - DCO_CLK INPUT
295
      //--------------------------------------------------------
296
 
297
                                // ------- Divider /1 ----------
298
      @(r15 === 16'h3001);
299
      repeat(2) @(posedge mclk);
300
      mclk_counter     = 0;
301
      lfxt_clk_counter = 0;
302
      dco_clk_counter  = 0;
303
      repeat(15) @(posedge mclk);
304
      if (mclk_counter    !==  15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
305
      if (dco_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
306
 
307
                                // ------- Divider /2 ----------
308
      @(r15 === 16'h3002);
309
      repeat(2) @(posedge mclk);
310
      mclk_counter     = 0;
311
      lfxt_clk_counter = 0;
312
      dco_clk_counter  = 0;
313
      repeat(15) @(posedge mclk);
314
      if (mclk_counter    !==  15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
315
  `ifdef MCLK_DIVIDER
316
      if (dco_clk_counter !==  30) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
317
  `else
318
      if (dco_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /2) - TEST 3 =====");
319
  `endif
320 202 olivier.gi
 
321 134 olivier.gi
                                // ------- Divider /4 ----------
322
      @(r15 === 16'h3003);
323
      repeat(2) @(posedge mclk);
324
      mclk_counter     = 0;
325
      lfxt_clk_counter = 0;
326
      dco_clk_counter  = 0;
327
      repeat(15) @(posedge mclk);
328
      if (mclk_counter    !==  15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
329
  `ifdef MCLK_DIVIDER
330
      if (dco_clk_counter !==  60) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
331
  `else
332
      if (dco_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /4) - TEST 3 =====");
333
  `endif
334 202 olivier.gi
 
335 134 olivier.gi
                                // ------- Divider /8 ----------
336
      @(r15 === 16'h3004);
337
      repeat(2) @(posedge mclk);
338
      mclk_counter     = 0;
339
      lfxt_clk_counter = 0;
340
      dco_clk_counter  = 0;
341
      repeat(15) @(posedge mclk);
342
      if (mclk_counter    !==  15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
343
  `ifdef MCLK_DIVIDER
344
      if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
345
  `else
346
      if (dco_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /8) - TEST 3 =====");
347
  `endif
348
 
349
 
350
`else
351 202 olivier.gi
      tb_skip_finish("|   (this test is not supported in FPGA mode)   |");
352 134 olivier.gi
`endif
353
 
354
      stimulus_done = 1;
355
   end

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