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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module_asic_smclk.s43] - Blame information for rev 145

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                               CLOCK MODULE                                */
/*---------------------------------------------------------------------------*/
/* Test the clock module:                                                    */
/*                        - Check the SMCLK clock generation.                */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
/*===========================================================================*/
 
.include "pmem_defs.asm"
 
.global main
 
WAIT_FUNC:
        dec r14
        jnz WAIT_FUNC
        ret
 
main:
        mov #DMEM_250, r1       ; # Initialize stack pointer
        mov   #0x0000, &DMEM_200
        mov   #0x0000, r15
 
 
      /* --------------      SMCLK GENERATION - LFXT_CLK INPUT    ----------------- */
 
        mov.b  #0x08, &BCSCTL2  ; # Div /1
        mov    #0x0001, r15
        mov    #0x00F0, r14
        call   #WAIT_FUNC
 
        mov.b  #0x0A, &BCSCTL2  ; # Div /2
        mov    #0x0002, r15
        mov    #0x01E0, r14
        call   #WAIT_FUNC
 
        mov.b  #0x0C, &BCSCTL2  ; # Div /4
        mov    #0x0003, r15
        mov    #0x03C0, r14
        call   #WAIT_FUNC
 
        mov.b  #0x0E, &BCSCTL2  ; # Div /8
        mov    #0x0004, r15
        mov    #0x0780, r14
        call   #WAIT_FUNC
 
        mov    #0x1000, r15
 
       /* --------------      SMCLK GENERATION - DCO_CLK INPUT     ----------------- */
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1
        mov    #0x1001, r15
        mov    #0x0050, r14
        call   #WAIT_FUNC
 
        mov.b  #0x02, &BCSCTL2  ; # Div /2
        mov    #0x1002, r15
        mov    #0x0050, r14
        call   #WAIT_FUNC
 
        mov.b  #0x04, &BCSCTL2  ; # Div /4
        mov    #0x1003, r15
        mov    #0x0050, r14
        call   #WAIT_FUNC
 
        mov.b  #0x06, &BCSCTL2  ; # Div /8
        mov    #0x1004, r15
        mov    #0x0050, r14
        call   #WAIT_FUNC
 
        mov    #0x2000, r15
 
 
      /* --------------      SMCLK GENERATION - LFXT_CLK INPUT    ----------------- */
 
        mov.b  #0x08, &BCSCTL2  ; # Div /1
        mov    #0x2001, r15
        mov    #0x00F0, r14
        call   #WAIT_FUNC
 
        mov.b  #0x0A, &BCSCTL2  ; # Div /2
        mov    #0x2002, r15
        mov    #0x01E0, r14
        call   #WAIT_FUNC
 
        mov.b  #0x0C, &BCSCTL2  ; # Div /4
        mov    #0x2003, r15
        mov    #0x03C0, r14
        call   #WAIT_FUNC
 
        mov.b  #0x0E, &BCSCTL2  ; # Div /8
        mov    #0x2004, r15
        mov    #0x0780, r14
        call   #WAIT_FUNC
 
        mov    #0x3000, r15
 
       /* --------------      SMCLK GENERATION - DCO_CLK INPUT     ----------------- */
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1
        mov    #0x3001, r15
        mov    #0x0050, r14
        call   #WAIT_FUNC
 
        mov.b  #0x02, &BCSCTL2  ; # Div /2
        mov    #0x3002, r15
        mov    #0x0050, r14
        call   #WAIT_FUNC
 
        mov.b  #0x04, &BCSCTL2  ; # Div /4
        mov    #0x3003, r15
        mov    #0x0050, r14
        call   #WAIT_FUNC
 
        mov.b  #0x06, &BCSCTL2  ; # Div /8
        mov    #0x3004, r15
        mov    #0x0050, r14
        call   #WAIT_FUNC
 
        mov    #0x4000, r15
 
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test        ; Interrupt  0 (lowest priority)    
.word end_of_test        ; Interrupt  1                      
.word end_of_test        ; Interrupt  2                      
.word end_of_test        ; Interrupt  3                      
.word end_of_test        ; Interrupt  4                      
.word end_of_test        ; Interrupt  5                      
.word end_of_test        ; Interrupt  6                      
.word end_of_test        ; Interrupt  7                      
.word end_of_test        ; Interrupt  8                      
.word end_of_test        ; Interrupt  9                      
.word end_of_test        ; Interrupt 10                      Watchdog timer
.word end_of_test        ; Interrupt 11                      
.word end_of_test        ; Interrupt 12                      
.word end_of_test        ; Interrupt 13                      
.word end_of_test        ; Interrupt 14                      NMI
.word main               ; Interrupt 15 (highest priority)   RESET

Line No.	Rev	Author	Line
1	134	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* CLOCK MODULE */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the clock module: */`
27			`/* - Check the SMCLK clock generation. */`
28			`/* */`
29			`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32			`/---------------------------------------------------------------------------/`
33			`/* $Rev: 19 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */`
36			`/===========================================================================/`
37
38	141	olivier.gi	`.include "pmem_defs.asm"`
39
40	134	olivier.gi	`.global main`
41
42			`WAIT_FUNC:`
43			`dec r14`
44			`jnz WAIT_FUNC`
45			`ret`
46
47			`main:`
48			`mov #DMEM_250, r1 ; # Initialize stack pointer`
49			`mov #0x0000, &DMEM_200`
50			`mov #0x0000, r15`
51
52
53			`/* -------------- SMCLK GENERATION - LFXT_CLK INPUT ----------------- */`
54
55			`mov.b #0x08, &BCSCTL2 ; # Div /1`
56			`mov #0x0001, r15`
57			`mov #0x00F0, r14`
58			`call #WAIT_FUNC`
59
60			`mov.b #0x0A, &BCSCTL2 ; # Div /2`
61			`mov #0x0002, r15`
62			`mov #0x01E0, r14`
63			`call #WAIT_FUNC`
64
65			`mov.b #0x0C, &BCSCTL2 ; # Div /4`
66			`mov #0x0003, r15`
67			`mov #0x03C0, r14`
68			`call #WAIT_FUNC`
69
70			`mov.b #0x0E, &BCSCTL2 ; # Div /8`
71			`mov #0x0004, r15`
72			`mov #0x0780, r14`
73			`call #WAIT_FUNC`
74
75			`mov #0x1000, r15`
76
77			`/* -------------- SMCLK GENERATION - DCO_CLK INPUT ----------------- */`
78
79			`mov.b #0x00, &BCSCTL2 ; # Div /1`
80			`mov #0x1001, r15`
81			`mov #0x0050, r14`
82			`call #WAIT_FUNC`
83
84			`mov.b #0x02, &BCSCTL2 ; # Div /2`
85			`mov #0x1002, r15`
86			`mov #0x0050, r14`
87			`call #WAIT_FUNC`
88
89			`mov.b #0x04, &BCSCTL2 ; # Div /4`
90			`mov #0x1003, r15`
91			`mov #0x0050, r14`
92			`call #WAIT_FUNC`
93
94			`mov.b #0x06, &BCSCTL2 ; # Div /8`
95			`mov #0x1004, r15`
96			`mov #0x0050, r14`
97			`call #WAIT_FUNC`
98
99			`mov #0x2000, r15`
100
101
102			`/* -------------- SMCLK GENERATION - LFXT_CLK INPUT ----------------- */`
103
104			`mov.b #0x08, &BCSCTL2 ; # Div /1`
105			`mov #0x2001, r15`
106			`mov #0x00F0, r14`
107			`call #WAIT_FUNC`
108
109			`mov.b #0x0A, &BCSCTL2 ; # Div /2`
110			`mov #0x2002, r15`
111			`mov #0x01E0, r14`
112			`call #WAIT_FUNC`
113
114			`mov.b #0x0C, &BCSCTL2 ; # Div /4`
115			`mov #0x2003, r15`
116			`mov #0x03C0, r14`
117			`call #WAIT_FUNC`
118
119			`mov.b #0x0E, &BCSCTL2 ; # Div /8`
120			`mov #0x2004, r15`
121			`mov #0x0780, r14`
122			`call #WAIT_FUNC`
123
124			`mov #0x3000, r15`
125
126			`/* -------------- SMCLK GENERATION - DCO_CLK INPUT ----------------- */`
127
128			`mov.b #0x00, &BCSCTL2 ; # Div /1`
129			`mov #0x3001, r15`
130			`mov #0x0050, r14`
131			`call #WAIT_FUNC`
132
133			`mov.b #0x02, &BCSCTL2 ; # Div /2`
134			`mov #0x3002, r15`
135			`mov #0x0050, r14`
136			`call #WAIT_FUNC`
137
138			`mov.b #0x04, &BCSCTL2 ; # Div /4`
139			`mov #0x3003, r15`
140			`mov #0x0050, r14`
141			`call #WAIT_FUNC`
142
143			`mov.b #0x06, &BCSCTL2 ; # Div /8`
144			`mov #0x3004, r15`
145			`mov #0x0050, r14`
146			`call #WAIT_FUNC`
147
148			`mov #0x4000, r15`
149
150
151
152			`/* ---------------------- END OF TEST --------------- */`
153			`end_of_test:`
154			`nop`
155			`br #0xffff`
156
157
158			`/* ---------------------- INTERRUPT VECTORS --------------- */`
159
160			`.section .vectors, "a"`
161			`.word end_of_test ; Interrupt 0 (lowest priority)`
162			`.word end_of_test ; Interrupt 1`
163			`.word end_of_test ; Interrupt 2`
164			`.word end_of_test ; Interrupt 3`
165			`.word end_of_test ; Interrupt 4`
166			`.word end_of_test ; Interrupt 5`
167			`.word end_of_test ; Interrupt 6`
168			`.word end_of_test ; Interrupt 7`
169			`.word end_of_test ; Interrupt 8`
170			`.word end_of_test ; Interrupt 9`
171			`.word end_of_test ; Interrupt 10 Watchdog timer`
172			`.word end_of_test ; Interrupt 11`
173			`.word end_of_test ; Interrupt 12`
174			`.word end_of_test ; Interrupt 13`
175			`.word end_of_test ; Interrupt 14 NMI`
176			`.word main ; Interrupt 15 (highest priority) RESET`

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module_asic_smclk.s43] - Blame information for rev 145