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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module_asic_smclk.v] - Blame information for rev 145

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1 134 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                               CLOCK MODULE                                */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the clock module:                                                    */
27 
/*                        - Check the SMCLK clock generation.                */
28 
/*                                                                           */
29 
/* Author(s):                                                                */
30 
/*             - Olivier Girard,    olgirard@gmail.com                       */
31 
/*                                                                           */
32 
/*---------------------------------------------------------------------------*/
33 
/* $Rev: 19 $                                                                */
34 
/* $LastChangedBy: olivier.girard $                                          */
35 
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
36 
/*===========================================================================*/
37 
 
38 
`define LONG_TIMEOUT
39 
 
40 
integer smclk_counter;
41 
always @ (negedge smclk)
42 
  smclk_counter     <=  smclk_counter+1;
43 
 
44 
integer dco_clk_counter;
45 
always @ (negedge dco_clk)
46 
  dco_clk_counter  <=  dco_clk_counter+1;
47 
 
48 
integer lfxt_clk_counter;
49 
always @ (negedge lfxt_clk)
50 
  lfxt_clk_counter <=  lfxt_clk_counter+1;
51 
 
52 
reg [15:0] reg_val;
53 
 
54 
initial
55 
   begin
56 
      $display(" ===============================================");
57 
      $display("|                 START SIMULATION              |");
58 
      $display(" ===============================================");
59 
      repeat(5) @(posedge smclk);
60 
      stimulus_done = 0;
61 
 
62 
`ifdef ASIC
63 
 
64 
      //--------------------------------------------------------
65 
      // SMCLK GENERATION - LFXT_CLK INPUT
66 
      //--------------------------------------------------------
67 
 
68 
                                // ------- Divider /1 ----------
69 
      @(r15 === 16'h0001);
70 
      repeat(2) @(posedge smclk);
71 
      smclk_counter     = 0;
72 
      lfxt_clk_counter = 0;
73 
      dco_clk_counter  = 0;
74 
      repeat(15) @(posedge smclk);
75 
      if (smclk_counter    !==  15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 1 =====");
76 
  `ifdef SMCLK_MUX
77 
      if (lfxt_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 2 =====");
78 
  `else
79 
      if (dco_clk_counter  !==  15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 3 =====");
80 
  `endif
81 
      $display("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /1) - DONE =====");
82 
 
83 
                                // ------- Divider /2 ----------
84 
      @(r15 === 16'h0002);
85 
      repeat(2) @(posedge smclk);
86 
      smclk_counter     = 0;
87 
      lfxt_clk_counter = 0;
88 
      dco_clk_counter  = 0;
89 
      repeat(15) @(posedge smclk);
90 
      if (smclk_counter    !==  15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 1 =====");
91 
  `ifdef SMCLK_DIVIDER
92 
    `ifdef SMCLK_MUX
93 
      if (lfxt_clk_counter !==  30) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 2 =====");
94 
    `else
95 
      if (dco_clk_counter  !==  30) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 3 =====");
96 
    `endif
97 
  `else
98 
    `ifdef SMCLK_MUX
99 
      if (lfxt_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 4 =====");
100 
    `else
101 
      if (dco_clk_counter  !==  15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 5 =====");
102 
    `endif
103 
  `endif
104 
      $display("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - DONE =====");
105 
 
106 
                                // ------- Divider /4 ----------
107 
      @(r15 === 16'h0003);
108 
      repeat(2) @(posedge smclk);
109 
      smclk_counter     = 0;
110 
      lfxt_clk_counter = 0;
111 
      dco_clk_counter  = 0;
112 
      repeat(15) @(posedge smclk);
113 
      if (smclk_counter    !==  15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 1 =====");
114 
  `ifdef SMCLK_DIVIDER
115 
    `ifdef SMCLK_MUX
116 
      if (lfxt_clk_counter !==  60) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 2 =====");
117 
    `else
118 
      if (dco_clk_counter  !==  60) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 3 =====");
119 
    `endif
120 
  `else
121 
    `ifdef SMCLK_MUX
122 
      if (lfxt_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 4 =====");
123 
    `else
124 
      if (dco_clk_counter  !==  15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 5 =====");
125 
    `endif
126 
  `endif
127 
      $display("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - DONE =====");
128 
 
129 
                                // ------- Divider /8 ----------
130 
      @(r15 === 16'h0004);
131 
      repeat(2) @(posedge smclk);
132 
      smclk_counter     = 0;
133 
      lfxt_clk_counter = 0;
134 
      dco_clk_counter  = 0;
135 
      repeat(15) @(posedge smclk);
136 
      if (smclk_counter    !==  15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 1 =====");
137 
  `ifdef SMCLK_DIVIDER
138 
    `ifdef SMCLK_MUX
139 
      if (lfxt_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 2 =====");
140 
    `else
141 
      if (dco_clk_counter  !== 120) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 3 =====");
142 
    `endif
143 
  `else
144 
    `ifdef SMCLK_MUX
145 
      if (lfxt_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 4 =====");
146 
    `else
147 
      if (dco_clk_counter  !==  15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 5 =====");
148 
    `endif
149 
  `endif
150 
      $display("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - DONE =====");
151 
 
152 
 
153 
      //--------------------------------------------------------
154 
      // SSMCLK GENERATION - DCO_CLK INPUT
155 
      //--------------------------------------------------------
156 
 
157 
                                // ------- Divider /1 ----------
158 
      @(r15 === 16'h1001);
159 
      repeat(2) @(posedge smclk);
160 
      smclk_counter     = 0;
161 
      lfxt_clk_counter = 0;
162 
      dco_clk_counter  = 0;
163 
      repeat(15) @(posedge smclk);
164 
      if (smclk_counter   !==  15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
165 
      if (dco_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
166 
      $display("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /1) - DONE =====");
167 
 
168 
                                // ------- Divider /2 ----------
169 
      @(r15 === 16'h1002);
170 
      repeat(2) @(posedge smclk);
171 
      smclk_counter     = 0;
172 
      lfxt_clk_counter = 0;
173 
      dco_clk_counter  = 0;
174 
      repeat(15) @(posedge smclk);
175 
      if (smclk_counter   !==  15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
176 
  `ifdef SMCLK_DIVIDER
177 
      if (dco_clk_counter !==  30) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
178 
  `else
179 
      if (dco_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 3 =====");
180 
  `endif
181 
      $display("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /2) - DONE =====");
182 
 
183 
                                // ------- Divider /4 ----------
184 
      @(r15 === 16'h1003);
185 
      repeat(2) @(posedge smclk);
186 
      smclk_counter     = 0;
187 
      lfxt_clk_counter = 0;
188 
      dco_clk_counter  = 0;
189 
      repeat(15) @(posedge smclk);
190 
      if (smclk_counter   !==  15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
191 
  `ifdef SMCLK_DIVIDER
192 
      if (dco_clk_counter !==  60) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
193 
  `else
194 
      if (dco_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 3 =====");
195 
  `endif
196 
      $display("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /4) - DONE =====");
197 
 
198 
                                // ------- Divider /8 ----------
199 
      @(r15 === 16'h1004);
200 
      repeat(2) @(posedge smclk);
201 
      smclk_counter     = 0;
202 
      lfxt_clk_counter = 0;
203 
      dco_clk_counter  = 0;
204 
      repeat(15) @(posedge smclk);
205 
      if (smclk_counter   !==  15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
206 
  `ifdef SMCLK_DIVIDER
207 
      if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
208 
  `else
209 
      if (dco_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 3 =====");
210 
  `endif
211 
      $display("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /8) - DONE =====");
212 
 
213 
 
214 
      //--------------------------------------------------------
215 
      // SMCLK GENERATION - LFXT_CLK INPUT
216 
      //--------------------------------------------------------
217 
 
218 
                                // ------- Divider /1 ----------
219 
      @(r15 === 16'h2001);
220 
      repeat(2) @(posedge smclk);
221 
      smclk_counter     = 0;
222 
      lfxt_clk_counter = 0;
223 
      dco_clk_counter  = 0;
224 
      repeat(15) @(posedge smclk);
225 
      if (smclk_counter    !==  15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 1 =====");
226 
  `ifdef SMCLK_MUX
227 
      if (lfxt_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 2 =====");
228 
  `else
229 
      if (dco_clk_counter  !==  15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 3 =====");
230 
  `endif
231 
      $display("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /1) - DONE =====");
232 
 
233 
                                // ------- Divider /2 ----------
234 
      @(r15 === 16'h2002);
235 
      repeat(2) @(posedge smclk);
236 
      smclk_counter     = 0;
237 
      lfxt_clk_counter = 0;
238 
      dco_clk_counter  = 0;
239 
      repeat(15) @(posedge smclk);
240 
      if (smclk_counter    !==  15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 1 =====");
241 
  `ifdef SMCLK_DIVIDER
242 
    `ifdef SMCLK_MUX
243 
      if (lfxt_clk_counter !==  30) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 2 =====");
244 
    `else
245 
      if (dco_clk_counter  !==  30) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 3 =====");
246 
    `endif
247 
  `else
248 
    `ifdef SMCLK_MUX
249 
      if (lfxt_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 4 =====");
250 
    `else
251 
      if (dco_clk_counter  !==  15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 5 =====");
252 
    `endif
253 
  `endif
254 
      $display("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - DONE =====");
255 
 
256 
                                // ------- Divider /4 ----------
257 
      @(r15 === 16'h2003);
258 
      repeat(2) @(posedge smclk);
259 
      smclk_counter     = 0;
260 
      lfxt_clk_counter = 0;
261 
      dco_clk_counter  = 0;
262 
      repeat(15) @(posedge smclk);
263 
      if (smclk_counter    !==  15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 1 =====");
264 
  `ifdef SMCLK_DIVIDER
265 
    `ifdef SMCLK_MUX
266 
      if (lfxt_clk_counter !==  60) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 2 =====");
267 
    `else
268 
      if (dco_clk_counter  !==  60) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 3 =====");
269 
    `endif
270 
  `else
271 
    `ifdef SMCLK_MUX
272 
      if (lfxt_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 4 =====");
273 
    `else
274 
      if (dco_clk_counter  !==  15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 5 =====");
275 
    `endif
276 
  `endif
277 
      $display("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - DONE =====");
278 
 
279 
                                // ------- Divider /8 ----------
280 
      @(r15 === 16'h2004);
281 
      repeat(2) @(posedge smclk);
282 
      smclk_counter     = 0;
283 
      lfxt_clk_counter = 0;
284 
      dco_clk_counter  = 0;
285 
      repeat(15) @(posedge smclk);
286 
      if (smclk_counter    !==  15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 1 =====");
287 
  `ifdef SMCLK_DIVIDER
288 
    `ifdef SMCLK_MUX
289 
      if (lfxt_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 2 =====");
290 
    `else
291 
      if (dco_clk_counter  !== 120) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 3 =====");
292 
    `endif
293 
  `else
294 
    `ifdef SMCLK_MUX
295 
      if (lfxt_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 4 =====");
296 
    `else
297 
      if (dco_clk_counter  !==  15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 5 =====");
298 
    `endif
299 
  `endif
300 
      $display("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - DONE =====");
301 
 
302 
 
303 
      //--------------------------------------------------------
304 
      // SSMCLK GENERATION - DCO_CLK INPUT
305 
      //--------------------------------------------------------
306 
 
307 
                                // ------- Divider /1 ----------
308 
      @(r15 === 16'h3001);
309 
      repeat(2) @(posedge smclk);
310 
      smclk_counter     = 0;
311 
      lfxt_clk_counter = 0;
312 
      dco_clk_counter  = 0;
313 
      repeat(15) @(posedge smclk);
314 
      if (smclk_counter   !==  15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
315 
      if (dco_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
316 
      $display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /1) - DONE =====");
317 
 
318 
                                // ------- Divider /2 ----------
319 
      @(r15 === 16'h3002);
320 
      repeat(2) @(posedge smclk);
321 
      smclk_counter     = 0;
322 
      lfxt_clk_counter = 0;
323 
      dco_clk_counter  = 0;
324 
      repeat(15) @(posedge smclk);
325 
      if (smclk_counter   !==  15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
326 
  `ifdef SMCLK_DIVIDER
327 
      if (dco_clk_counter !==  30) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
328 
  `else
329 
      if (dco_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 3 =====");
330 
  `endif
331 
      $display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /2) - DONE =====");
332 
 
333 
                                // ------- Divider /4 ----------
334 
      @(r15 === 16'h3003);
335 
      repeat(2) @(posedge smclk);
336 
      smclk_counter     = 0;
337 
      lfxt_clk_counter = 0;
338 
      dco_clk_counter  = 0;
339 
      repeat(15) @(posedge smclk);
340 
      if (smclk_counter   !==  15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
341 
  `ifdef SMCLK_DIVIDER
342 
      if (dco_clk_counter !==  60) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
343 
  `else
344 
      if (dco_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 3 =====");
345 
  `endif
346 
      $display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /4) - DONE =====");
347 
 
348 
                                // ------- Divider /8 ----------
349 
      @(r15 === 16'h3004);
350 
      repeat(2) @(posedge smclk);
351 
      smclk_counter     = 0;
352 
      lfxt_clk_counter = 0;
353 
      dco_clk_counter  = 0;
354 
      repeat(15) @(posedge smclk);
355 
      if (smclk_counter   !==  15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
356 
  `ifdef SMCLK_DIVIDER
357 
      if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
358 
  `else
359 
      if (dco_clk_counter !==  15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 3 =====");
360 
  `endif
361 
      $display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - DONE =====");
362 
 
363 
 
364 
`else
365 
      $display(" ===============================================");
366 
      $display("|               SIMULATION SKIPPED              |");
367 
      $display("|   (this test is not supported in FPGA mode)   |");
368 
      $display(" ===============================================");
369 
      $finish;
370 
`endif
371 
 
372 
      stimulus_done = 1;
373 
   end
374 
 

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