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olivier.gi |
/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/*===========================================================================*/
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/* CLOCK MODULE */
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/*---------------------------------------------------------------------------*/
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/* Test the clock module: */
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/* - Check the SMCLK clock generation. */
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/* */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 19 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
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/*===========================================================================*/
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`define LONG_TIMEOUT
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integer smclk_counter;
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always @ (negedge smclk)
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smclk_counter <= smclk_counter+1;
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integer dco_clk_counter;
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always @ (negedge dco_clk)
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dco_clk_counter <= dco_clk_counter+1;
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integer lfxt_clk_counter;
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always @ (negedge lfxt_clk)
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lfxt_clk_counter <= lfxt_clk_counter+1;
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reg [15:0] reg_val;
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olivier.gi |
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olivier.gi |
initial
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begin
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$display(" ===============================================");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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repeat(5) @(posedge smclk);
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stimulus_done = 0;
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olivier.gi |
`ifdef ASIC_CLOCKING
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olivier.gi |
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olivier.gi |
//--------------------------------------------------------
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// SMCLK GENERATION - LFXT_CLK INPUT
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//--------------------------------------------------------
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// ------- Divider /1 ----------
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@(r15 === 16'h0001);
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repeat(2) @(posedge smclk);
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smclk_counter = 0;
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lfxt_clk_counter = 0;
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dco_clk_counter = 0;
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repeat(15) @(posedge smclk);
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if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 1 =====");
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`ifdef SMCLK_MUX
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if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 2 =====");
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`else
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if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 3 =====");
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`endif
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$display("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /1) - DONE =====");
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// ------- Divider /2 ----------
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@(r15 === 16'h0002);
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repeat(2) @(posedge smclk);
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smclk_counter = 0;
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lfxt_clk_counter = 0;
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dco_clk_counter = 0;
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repeat(15) @(posedge smclk);
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if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 1 =====");
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`ifdef SMCLK_DIVIDER
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`ifdef SMCLK_MUX
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if (lfxt_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 2 =====");
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`else
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if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 3 =====");
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`endif
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`else
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`ifdef SMCLK_MUX
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if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 4 =====");
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`else
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if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 5 =====");
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`endif
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`endif
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$display("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /2) - DONE =====");
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olivier.gi |
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olivier.gi |
// ------- Divider /4 ----------
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@(r15 === 16'h0003);
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repeat(2) @(posedge smclk);
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smclk_counter = 0;
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lfxt_clk_counter = 0;
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dco_clk_counter = 0;
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repeat(15) @(posedge smclk);
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if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 1 =====");
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`ifdef SMCLK_DIVIDER
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`ifdef SMCLK_MUX
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if (lfxt_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 2 =====");
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`else
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if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 3 =====");
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`endif
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`else
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`ifdef SMCLK_MUX
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if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 4 =====");
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`else
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if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 5 =====");
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`endif
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`endif
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$display("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /4) - DONE =====");
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olivier.gi |
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olivier.gi |
// ------- Divider /8 ----------
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@(r15 === 16'h0004);
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repeat(2) @(posedge smclk);
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smclk_counter = 0;
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lfxt_clk_counter = 0;
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dco_clk_counter = 0;
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repeat(15) @(posedge smclk);
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if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 1 =====");
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`ifdef SMCLK_DIVIDER
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`ifdef SMCLK_MUX
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if (lfxt_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 2 =====");
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`else
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if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 3 =====");
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`endif
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`else
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`ifdef SMCLK_MUX
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if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 4 =====");
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`else
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if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 5 =====");
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`endif
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`endif
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$display("====== CLOCK GENERATOR 1: SMCLK - LFXT_CLK INPUT (DIV /8) - DONE =====");
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olivier.gi |
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olivier.gi |
//--------------------------------------------------------
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// SSMCLK GENERATION - DCO_CLK INPUT
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//--------------------------------------------------------
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// ------- Divider /1 ----------
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@(r15 === 16'h1001);
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repeat(2) @(posedge smclk);
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smclk_counter = 0;
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lfxt_clk_counter = 0;
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dco_clk_counter = 0;
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repeat(15) @(posedge smclk);
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if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
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if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
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$display("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /1) - DONE =====");
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// ------- Divider /2 ----------
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@(r15 === 16'h1002);
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repeat(2) @(posedge smclk);
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smclk_counter = 0;
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lfxt_clk_counter = 0;
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dco_clk_counter = 0;
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repeat(15) @(posedge smclk);
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if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
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`ifdef SMCLK_DIVIDER
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if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
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`else
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if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 3 =====");
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`endif
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$display("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /2) - DONE =====");
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olivier.gi |
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olivier.gi |
// ------- Divider /4 ----------
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@(r15 === 16'h1003);
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repeat(2) @(posedge smclk);
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smclk_counter = 0;
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lfxt_clk_counter = 0;
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dco_clk_counter = 0;
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repeat(15) @(posedge smclk);
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if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
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`ifdef SMCLK_DIVIDER
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if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
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`else
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if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 3 =====");
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`endif
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$display("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /4) - DONE =====");
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olivier.gi |
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olivier.gi |
// ------- Divider /8 ----------
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@(r15 === 16'h1004);
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repeat(2) @(posedge smclk);
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smclk_counter = 0;
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lfxt_clk_counter = 0;
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dco_clk_counter = 0;
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repeat(15) @(posedge smclk);
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if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
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`ifdef SMCLK_DIVIDER
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if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
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`else
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if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 3 =====");
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`endif
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$display("====== CLOCK GENERATOR 2: SMCLK - DCO_CLK INPUT (DIV /8) - DONE =====");
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//--------------------------------------------------------
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// SMCLK GENERATION - LFXT_CLK INPUT
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//--------------------------------------------------------
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// ------- Divider /1 ----------
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@(r15 === 16'h2001);
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repeat(2) @(posedge smclk);
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smclk_counter = 0;
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lfxt_clk_counter = 0;
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dco_clk_counter = 0;
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repeat(15) @(posedge smclk);
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if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 1 =====");
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`ifdef SMCLK_MUX
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if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 2 =====");
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`else
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if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /1) - TEST 3 =====");
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`endif
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$display("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /1) - DONE =====");
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// ------- Divider /2 ----------
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@(r15 === 16'h2002);
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repeat(2) @(posedge smclk);
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smclk_counter = 0;
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lfxt_clk_counter = 0;
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dco_clk_counter = 0;
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repeat(15) @(posedge smclk);
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if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 1 =====");
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`ifdef SMCLK_DIVIDER
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`ifdef SMCLK_MUX
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if (lfxt_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 2 =====");
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`else
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if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 3 =====");
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`endif
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`else
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`ifdef SMCLK_MUX
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if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 4 =====");
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`else
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if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - TEST 5 =====");
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`endif
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`endif
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$display("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /2) - DONE =====");
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olivier.gi |
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olivier.gi |
// ------- Divider /4 ----------
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@(r15 === 16'h2003);
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repeat(2) @(posedge smclk);
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smclk_counter = 0;
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lfxt_clk_counter = 0;
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dco_clk_counter = 0;
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repeat(15) @(posedge smclk);
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if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 1 =====");
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`ifdef SMCLK_DIVIDER
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`ifdef SMCLK_MUX
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if (lfxt_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 2 =====");
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`else
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if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 3 =====");
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`endif
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`else
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`ifdef SMCLK_MUX
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if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 4 =====");
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`else
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274 |
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if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - TEST 5 =====");
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`endif
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`endif
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$display("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /4) - DONE =====");
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278 |
202 |
olivier.gi |
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279 |
134 |
olivier.gi |
// ------- Divider /8 ----------
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280 |
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@(r15 === 16'h2004);
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281 |
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repeat(2) @(posedge smclk);
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smclk_counter = 0;
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283 |
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lfxt_clk_counter = 0;
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dco_clk_counter = 0;
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285 |
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repeat(15) @(posedge smclk);
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286 |
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if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 1 =====");
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287 |
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`ifdef SMCLK_DIVIDER
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288 |
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`ifdef SMCLK_MUX
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289 |
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if (lfxt_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 2 =====");
|
290 |
|
|
`else
|
291 |
|
|
if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 3 =====");
|
292 |
|
|
`endif
|
293 |
|
|
`else
|
294 |
|
|
`ifdef SMCLK_MUX
|
295 |
|
|
if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 4 =====");
|
296 |
|
|
`else
|
297 |
|
|
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - TEST 5 =====");
|
298 |
|
|
`endif
|
299 |
|
|
`endif
|
300 |
|
|
$display("====== CLOCK GENERATOR 3: SMCLK - LFXT_CLK INPUT (DIV /8) - DONE =====");
|
301 |
|
|
|
302 |
202 |
olivier.gi |
|
303 |
134 |
olivier.gi |
//--------------------------------------------------------
|
304 |
|
|
// SSMCLK GENERATION - DCO_CLK INPUT
|
305 |
|
|
//--------------------------------------------------------
|
306 |
|
|
|
307 |
|
|
// ------- Divider /1 ----------
|
308 |
|
|
@(r15 === 16'h3001);
|
309 |
|
|
repeat(2) @(posedge smclk);
|
310 |
|
|
smclk_counter = 0;
|
311 |
|
|
lfxt_clk_counter = 0;
|
312 |
|
|
dco_clk_counter = 0;
|
313 |
|
|
repeat(15) @(posedge smclk);
|
314 |
|
|
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
|
315 |
|
|
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
|
316 |
|
|
$display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /1) - DONE =====");
|
317 |
|
|
|
318 |
|
|
// ------- Divider /2 ----------
|
319 |
|
|
@(r15 === 16'h3002);
|
320 |
|
|
repeat(2) @(posedge smclk);
|
321 |
|
|
smclk_counter = 0;
|
322 |
|
|
lfxt_clk_counter = 0;
|
323 |
|
|
dco_clk_counter = 0;
|
324 |
|
|
repeat(15) @(posedge smclk);
|
325 |
|
|
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
|
326 |
|
|
`ifdef SMCLK_DIVIDER
|
327 |
|
|
if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
|
328 |
|
|
`else
|
329 |
|
|
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 3 =====");
|
330 |
|
|
`endif
|
331 |
|
|
$display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /2) - DONE =====");
|
332 |
202 |
olivier.gi |
|
333 |
134 |
olivier.gi |
// ------- Divider /4 ----------
|
334 |
|
|
@(r15 === 16'h3003);
|
335 |
|
|
repeat(2) @(posedge smclk);
|
336 |
|
|
smclk_counter = 0;
|
337 |
|
|
lfxt_clk_counter = 0;
|
338 |
|
|
dco_clk_counter = 0;
|
339 |
|
|
repeat(15) @(posedge smclk);
|
340 |
|
|
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
|
341 |
|
|
`ifdef SMCLK_DIVIDER
|
342 |
|
|
if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
|
343 |
|
|
`else
|
344 |
|
|
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 3 =====");
|
345 |
|
|
`endif
|
346 |
|
|
$display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /4) - DONE =====");
|
347 |
202 |
olivier.gi |
|
348 |
134 |
olivier.gi |
// ------- Divider /8 ----------
|
349 |
|
|
@(r15 === 16'h3004);
|
350 |
|
|
repeat(2) @(posedge smclk);
|
351 |
|
|
smclk_counter = 0;
|
352 |
|
|
lfxt_clk_counter = 0;
|
353 |
|
|
dco_clk_counter = 0;
|
354 |
|
|
repeat(15) @(posedge smclk);
|
355 |
|
|
if (smclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
|
356 |
|
|
`ifdef SMCLK_DIVIDER
|
357 |
|
|
if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
|
358 |
|
|
`else
|
359 |
|
|
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 3 =====");
|
360 |
|
|
`endif
|
361 |
|
|
$display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - DONE =====");
|
362 |
|
|
|
363 |
|
|
|
364 |
|
|
`else
|
365 |
202 |
olivier.gi |
tb_skip_finish("| (this test is not supported in FPGA mode) |");
|
366 |
134 |
olivier.gi |
`endif
|
367 |
|
|
|
368 |
|
|
stimulus_done = 1;
|
369 |
|
|
end
|