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olivier.gi |
/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/*===========================================================================*/
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/* DEBUG INTERFACE: I2C */
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/*---------------------------------------------------------------------------*/
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/* Test the I2C debug interface: */
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/* - Check RD/WR access to debugg registers. */
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/* - Check RD Bursts. */
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/* - Check WR Bursts. */
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/* */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 95 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
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/*===========================================================================*/
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`define LONG_TIMEOUT
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reg [2:0] cpu_version;
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reg cpu_asic;
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reg [4:0] user_version;
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reg [6:0] per_space;
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reg mpy_info;
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reg [8:0] dmem_size;
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reg [5:0] pmem_size;
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reg [31:0] dbg_id;
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integer step;
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olivier.gi |
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olivier.gi |
initial
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begin
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$display(" ===============================================");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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`ifdef DBG_EN
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`ifdef DBG_I2C
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step = 0;
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#1 dbg_en = 1;
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repeat(30) @(posedge mclk);
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stimulus_done = 0;
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olivier.gi |
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olivier.gi |
`ifdef DBG_RST_BRK_EN
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dbg_i2c_wr(CPU_CTL, 16'h0002); // RUN
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`endif
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olivier.gi |
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olivier.gi |
// TEST CPU REGISTERS
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//--------------------------------------------------------
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step = 1;
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cpu_version = `CPU_VERSION;
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`ifdef ASIC
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cpu_asic = 1'b1;
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`else
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cpu_asic = 1'b0;
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`endif
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user_version = `USER_VERSION;
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per_space = (`PER_SIZE >> 9);
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`ifdef MULTIPLIER
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mpy_info = 1'b1;
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`else
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mpy_info = 1'b0;
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`endif
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dmem_size = (`DMEM_SIZE >> 7);
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pmem_size = (`PMEM_SIZE >> 10);
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dbg_id = {pmem_size,
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dmem_size,
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mpy_info,
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per_space,
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user_version,
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cpu_asic,
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cpu_version};
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dbg_i2c_wr(CPU_ID_LO , 16'hffff);
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dbg_i2c_rd(CPU_ID_LO);
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if (dbg_i2c_buf !== dbg_id[15:0]) tb_error("====== CPU_ID_LO uncorrect =====");
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dbg_i2c_wr(CPU_ID_LO , 16'h0000);
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dbg_i2c_rd(CPU_ID_LO);
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if (dbg_i2c_buf !== dbg_id[15:0]) tb_error("====== CPU_ID_LO uncorrect =====");
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dbg_i2c_wr(CPU_ID_HI , 16'hffff);
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dbg_i2c_rd(CPU_ID_HI);
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if (dbg_i2c_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect =====");
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dbg_i2c_wr(CPU_ID_HI , 16'h0000);
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dbg_i2c_rd(CPU_ID_HI);
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if (dbg_i2c_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect =====");
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dbg_i2c_wr(CPU_STAT , 16'hffff);
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dbg_i2c_rd(CPU_STAT);
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== CPU_STAT uncorrect =====");
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dbg_i2c_wr(CPU_STAT , 16'h0000);
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dbg_i2c_rd(CPU_STAT);
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== CPU_STAT uncorrect =====");
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dbg_i2c_wr(CPU_CTL , 16'hffff);
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dbg_i2c_rd(CPU_CTL);
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if (dbg_i2c_buf !== 16'h0078) tb_error("====== CPU_CTL uncorrect =====");
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dbg_i2c_wr(CPU_CTL , 16'h0000);
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dbg_i2c_rd(CPU_CTL);
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== CPU_CTL uncorrect =====");
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olivier.gi |
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154 |
olivier.gi |
// TEST MEMORY CONTROL REGISTERS
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//--------------------------------------------------------
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step = 2;
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dbg_i2c_wr(MEM_CTL , 16'hfffe);
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dbg_i2c_rd(MEM_CTL);
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if (dbg_i2c_buf !== 16'h000E) tb_error("====== MEM_CTL uncorrect =====");
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dbg_i2c_wr(MEM_CTL , 16'h0000);
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dbg_i2c_rd(MEM_CTL);
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_CTL uncorrect =====");
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dbg_i2c_wr(MEM_ADDR , 16'hffff);
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dbg_i2c_rd(MEM_ADDR);
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if (dbg_i2c_buf !== 16'hffff) tb_error("====== MEM_ADDR uncorrect =====");
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dbg_i2c_wr(MEM_ADDR , 16'h0000);
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dbg_i2c_rd(MEM_ADDR);
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_ADDR uncorrect =====");
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dbg_i2c_wr(MEM_DATA , 16'hffff);
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dbg_i2c_rd(MEM_DATA);
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if (dbg_i2c_buf !== 16'hffff) tb_error("====== MEM_DATA uncorrect =====");
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dbg_i2c_wr(MEM_DATA , 16'h0000);
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dbg_i2c_rd(MEM_DATA);
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_DATA uncorrect =====");
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dbg_i2c_wr(MEM_CNT , 16'hffff);
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dbg_i2c_rd(MEM_CNT);
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if (dbg_i2c_buf !== 16'hffff) tb_error("====== MEM_CNT uncorrect =====");
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dbg_i2c_wr(MEM_CNT , 16'h0000);
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dbg_i2c_rd(MEM_CNT);
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_CNT uncorrect =====");
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// TEST HARDWARE BREAKPOINT 0 REGISTERS
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//--------------------------------------------------------
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`ifdef DBG_HWBRK_0
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step = 3;
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dbg_i2c_wr(BRK0_CTL , 16'hffff);
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dbg_i2c_rd(BRK0_CTL);
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if (`HWBRK_RANGE)
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begin
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if (dbg_i2c_buf !== 16'h001F) tb_error("====== BRK0_CTL uncorrect =====");
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end
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else
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begin
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if (dbg_i2c_buf !== 16'h000F) tb_error("====== BRK0_CTL uncorrect =====");
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end
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dbg_i2c_wr(BRK0_CTL , 16'h0000);
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dbg_i2c_rd(BRK0_CTL);
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK0_CTL uncorrect =====");
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dbg_i2c_wr(BRK0_STAT , 16'hffff);
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dbg_i2c_rd(BRK0_STAT);
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK0_STAT uncorrect =====");
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dbg_i2c_wr(BRK0_STAT , 16'h0000);
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dbg_i2c_rd(BRK0_STAT);
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK0_STAT uncorrect =====");
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dbg_i2c_wr(BRK0_ADDR0 , 16'hffff);
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dbg_i2c_rd(BRK0_ADDR0);
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if (dbg_i2c_buf !== 16'hffff) tb_error("====== BRK0_ADDR0 uncorrect =====");
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dbg_i2c_wr(BRK0_ADDR0 , 16'h0000);
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dbg_i2c_rd(BRK0_ADDR0);
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK0_ADDR0 uncorrect =====");
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dbg_i2c_wr(BRK0_ADDR1 , 16'hffff);
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dbg_i2c_rd(BRK0_ADDR1);
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if (dbg_i2c_buf !== 16'hffff) tb_error("====== BRK0_ADDR1 uncorrect =====");
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dbg_i2c_wr(BRK0_ADDR1 , 16'h0000);
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dbg_i2c_rd(BRK0_ADDR1);
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK0_ADDR1 uncorrect =====");
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`endif
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// TEST HARDWARE BREAKPOINT 1 REGISTERS
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//--------------------------------------------------------
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`ifdef DBG_HWBRK_1
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step = 4;
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dbg_i2c_wr(BRK1_CTL , 16'hffff);
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dbg_i2c_rd(BRK1_CTL);
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if (`HWBRK_RANGE)
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begin
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if (dbg_i2c_buf !== 16'h001F) tb_error("====== BRK1_CTL uncorrect =====");
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end
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else
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begin
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if (dbg_i2c_buf !== 16'h000F) tb_error("====== BRK1_CTL uncorrect =====");
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end
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dbg_i2c_wr(BRK1_CTL , 16'h0000);
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dbg_i2c_rd(BRK1_CTL);
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK1_CTL uncorrect =====");
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217 |
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218 |
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dbg_i2c_wr(BRK1_STAT , 16'hffff);
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dbg_i2c_rd(BRK1_STAT);
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220 |
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK1_STAT uncorrect =====");
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221 |
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dbg_i2c_wr(BRK1_STAT , 16'h0000);
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dbg_i2c_rd(BRK1_STAT);
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK1_STAT uncorrect =====");
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224 |
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225 |
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dbg_i2c_wr(BRK1_ADDR0 , 16'hffff);
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dbg_i2c_rd(BRK1_ADDR0);
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227 |
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if (dbg_i2c_buf !== 16'hffff) tb_error("====== BRK1_ADDR0 uncorrect =====");
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228 |
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dbg_i2c_wr(BRK1_ADDR0 , 16'h0000);
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dbg_i2c_rd(BRK1_ADDR0);
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK1_ADDR0 uncorrect =====");
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231 |
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232 |
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dbg_i2c_wr(BRK1_ADDR1 , 16'hffff);
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dbg_i2c_rd(BRK1_ADDR1);
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if (dbg_i2c_buf !== 16'hffff) tb_error("====== BRK1_ADDR1 uncorrect =====");
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dbg_i2c_wr(BRK1_ADDR1 , 16'h0000);
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dbg_i2c_rd(BRK1_ADDR1);
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK1_ADDR1 uncorrect =====");
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`endif
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239 |
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240 |
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// TEST HARDWARE BREAKPOINT 2 REGISTERS
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241 |
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//--------------------------------------------------------
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242 |
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`ifdef DBG_HWBRK_2
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step = 5;
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dbg_i2c_wr(BRK2_CTL , 16'hffff);
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245 |
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dbg_i2c_rd(BRK2_CTL);
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246 |
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if (`HWBRK_RANGE)
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begin
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248 |
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if (dbg_i2c_buf !== 16'h001F) tb_error("====== BRK2_CTL uncorrect =====");
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249 |
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end
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250 |
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else
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251 |
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begin
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252 |
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if (dbg_i2c_buf !== 16'h000F) tb_error("====== BRK2_CTL uncorrect =====");
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253 |
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end
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254 |
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dbg_i2c_wr(BRK2_CTL , 16'h0000);
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255 |
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dbg_i2c_rd(BRK2_CTL);
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256 |
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK2_CTL uncorrect =====");
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257 |
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258 |
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dbg_i2c_wr(BRK2_STAT , 16'hffff);
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259 |
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dbg_i2c_rd(BRK2_STAT);
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260 |
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK2_STAT uncorrect =====");
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261 |
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dbg_i2c_wr(BRK2_STAT , 16'h0000);
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262 |
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dbg_i2c_rd(BRK2_STAT);
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263 |
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK2_STAT uncorrect =====");
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264 |
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265 |
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dbg_i2c_wr(BRK2_ADDR0 , 16'hffff);
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266 |
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dbg_i2c_rd(BRK2_ADDR0);
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267 |
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if (dbg_i2c_buf !== 16'hffff) tb_error("====== BRK2_ADDR0 uncorrect =====");
|
268 |
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dbg_i2c_wr(BRK2_ADDR0 , 16'h0000);
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269 |
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dbg_i2c_rd(BRK2_ADDR0);
|
270 |
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK2_ADDR0 uncorrect =====");
|
271 |
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272 |
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dbg_i2c_wr(BRK2_ADDR1 , 16'hffff);
|
273 |
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dbg_i2c_rd(BRK2_ADDR1);
|
274 |
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if (dbg_i2c_buf !== 16'hffff) tb_error("====== BRK2_ADDR1 uncorrect =====");
|
275 |
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dbg_i2c_wr(BRK2_ADDR1 , 16'h0000);
|
276 |
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dbg_i2c_rd(BRK2_ADDR1);
|
277 |
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK2_ADDR1 uncorrect =====");
|
278 |
|
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`endif
|
279 |
202 |
olivier.gi |
|
280 |
154 |
olivier.gi |
// TEST HARDWARE BREAKPOINT 3 REGISTERS
|
281 |
|
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//--------------------------------------------------------
|
282 |
|
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`ifdef DBG_HWBRK_3
|
283 |
|
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step = 6;
|
284 |
|
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dbg_i2c_wr(BRK3_CTL , 16'hffff);
|
285 |
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dbg_i2c_rd(BRK3_CTL);
|
286 |
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if (`HWBRK_RANGE)
|
287 |
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begin
|
288 |
|
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if (dbg_i2c_buf !== 16'h001F) tb_error("====== BRK3_CTL uncorrect =====");
|
289 |
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end
|
290 |
|
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else
|
291 |
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begin
|
292 |
|
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if (dbg_i2c_buf !== 16'h000F) tb_error("====== BRK3_CTL uncorrect =====");
|
293 |
|
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end
|
294 |
|
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dbg_i2c_wr(BRK3_CTL , 16'h0000);
|
295 |
|
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dbg_i2c_rd(BRK3_CTL);
|
296 |
|
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if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK3_CTL uncorrect =====");
|
297 |
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|
298 |
|
|
dbg_i2c_wr(BRK3_STAT , 16'hffff);
|
299 |
|
|
dbg_i2c_rd(BRK3_STAT);
|
300 |
|
|
if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK3_STAT uncorrect =====");
|
301 |
|
|
dbg_i2c_wr(BRK3_STAT , 16'h0000);
|
302 |
|
|
dbg_i2c_rd(BRK3_STAT);
|
303 |
|
|
if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK3_STAT uncorrect =====");
|
304 |
|
|
|
305 |
|
|
dbg_i2c_wr(BRK3_ADDR0 , 16'hffff);
|
306 |
|
|
dbg_i2c_rd(BRK3_ADDR0);
|
307 |
|
|
if (dbg_i2c_buf !== 16'hffff) tb_error("====== BRK3_ADDR0 uncorrect =====");
|
308 |
|
|
dbg_i2c_wr(BRK3_ADDR0 , 16'h0000);
|
309 |
|
|
dbg_i2c_rd(BRK3_ADDR0);
|
310 |
|
|
if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK3_ADDR0 uncorrect =====");
|
311 |
|
|
|
312 |
|
|
dbg_i2c_wr(BRK3_ADDR1 , 16'hffff);
|
313 |
|
|
dbg_i2c_rd(BRK3_ADDR1);
|
314 |
|
|
if (dbg_i2c_buf !== 16'hffff) tb_error("====== BRK3_ADDR1 uncorrect =====");
|
315 |
|
|
dbg_i2c_wr(BRK3_ADDR1 , 16'h0000);
|
316 |
|
|
dbg_i2c_rd(BRK3_ADDR1);
|
317 |
|
|
if (dbg_i2c_buf !== 16'h0000) tb_error("====== BRK3_ADDR1 uncorrect =====");
|
318 |
|
|
`endif
|
319 |
|
|
|
320 |
|
|
// TEST 16B WRITE BURSTS (MEMORY)
|
321 |
|
|
//--------------------------------------------------------
|
322 |
|
|
step = 7;
|
323 |
|
|
|
324 |
|
|
dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
|
325 |
|
|
dbg_i2c_wr(MEM_CNT, 16'h0004); // 5 consecutive access
|
326 |
202 |
olivier.gi |
|
327 |
154 |
olivier.gi |
dbg_i2c_wr(MEM_CTL, 16'h0003); // Start burst to 16 bit memory write
|
328 |
|
|
dbg_i2c_burst_start(0);
|
329 |
|
|
dbg_i2c_tx16(16'h1234, 0); // write 1st data
|
330 |
|
|
repeat(12) @(posedge mclk);
|
331 |
|
|
if (mem200 !== 16'h1234) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
|
332 |
|
|
dbg_i2c_tx16(16'h5678, 0); // write 2nd data
|
333 |
|
|
repeat(12) @(posedge mclk);
|
334 |
|
|
if (mem202 !== 16'h5678) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
|
335 |
|
|
dbg_i2c_tx16(16'h9abc, 0); // write 3rd data
|
336 |
|
|
repeat(12) @(posedge mclk);
|
337 |
|
|
if (mem204 !== 16'h9abc) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
|
338 |
|
|
dbg_i2c_tx16(16'hdef0, 0); // write 4th data
|
339 |
|
|
repeat(12) @(posedge mclk);
|
340 |
|
|
if (mem206 !== 16'hdef0) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
|
341 |
|
|
dbg_i2c_tx16(16'h0fed, 1); // write 5th data
|
342 |
|
|
repeat(12) @(posedge mclk);
|
343 |
|
|
if (mem208 !== 16'h0fed) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
|
344 |
|
|
|
345 |
|
|
step = 8;
|
346 |
|
|
dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
|
347 |
|
|
dbg_i2c_wr(MEM_CNT, 16'h0004); // 5 consecutive access
|
348 |
202 |
olivier.gi |
|
349 |
154 |
olivier.gi |
dbg_i2c_wr(MEM_CTL, 16'h0001); // Start burst to 16 bit registers read
|
350 |
|
|
dbg_i2c_burst_start(1);
|
351 |
|
|
dbg_i2c_rx16(0); // read 1st data
|
352 |
|
|
if (dbg_i2c_buf !== 16'h1234) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
|
353 |
|
|
dbg_i2c_rx16(0); // read 2nd data
|
354 |
|
|
if (dbg_i2c_buf !== 16'h5678) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
|
355 |
|
|
dbg_i2c_rx16(0); // read 3rd data
|
356 |
|
|
if (dbg_i2c_buf !== 16'h9abc) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
|
357 |
|
|
dbg_i2c_rx16(0); // read 4th data
|
358 |
|
|
if (dbg_i2c_buf !== 16'hdef0) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
|
359 |
|
|
dbg_i2c_rx16(1); // read 5th data
|
360 |
|
|
if (dbg_i2c_buf !== 16'h0fed) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
|
361 |
|
|
|
362 |
|
|
|
363 |
|
|
// TEST 16B WRITE BURSTS (CPU REGISTERS)
|
364 |
|
|
//--------------------------------------------------------
|
365 |
|
|
step = 9;
|
366 |
|
|
|
367 |
|
|
dbg_i2c_wr(MEM_ADDR, 16'h0005); // select R5
|
368 |
|
|
dbg_i2c_wr(MEM_CNT, 16'h0004); // 5 consecutive access
|
369 |
202 |
olivier.gi |
|
370 |
154 |
olivier.gi |
dbg_i2c_wr(MEM_CTL, 16'h0007); // Start burst to 16 bit cpu register write
|
371 |
|
|
dbg_i2c_burst_start(0);
|
372 |
|
|
dbg_i2c_tx16(16'hcba9, 0); // write 1st data
|
373 |
|
|
repeat(12) @(posedge mclk);
|
374 |
|
|
if (r5 !== 16'hcba9) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 1st DATA =====");
|
375 |
|
|
dbg_i2c_tx16(16'h8765, 0); // write 2nd data
|
376 |
|
|
repeat(12) @(posedge mclk);
|
377 |
|
|
if (r6 !== 16'h8765) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 2nd DATA =====");
|
378 |
|
|
dbg_i2c_tx16(16'h4321, 0); // write 3rd data
|
379 |
|
|
repeat(12) @(posedge mclk);
|
380 |
|
|
if (r7 !== 16'h4321) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 3rd DATA =====");
|
381 |
|
|
dbg_i2c_tx16(16'h0123, 0); // write 4th data
|
382 |
|
|
repeat(12) @(posedge mclk);
|
383 |
|
|
if (r8 !== 16'h0123) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 4th DATA =====");
|
384 |
|
|
dbg_i2c_tx16(16'h4567, 1); // write 5th data
|
385 |
|
|
repeat(12) @(posedge mclk);
|
386 |
|
|
if (r9 !== 16'h4567) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 5th DATA =====");
|
387 |
202 |
olivier.gi |
|
388 |
154 |
olivier.gi |
step = 10;
|
389 |
|
|
dbg_i2c_wr(MEM_ADDR, 16'h0005); // select @0x0200
|
390 |
|
|
dbg_i2c_wr(MEM_CNT, 16'h0004); // 5 consecutive access
|
391 |
202 |
olivier.gi |
|
392 |
154 |
olivier.gi |
dbg_i2c_wr(MEM_CTL, 16'h0005); // Start burst to 16 bit cpu registers read
|
393 |
|
|
dbg_i2c_burst_start(1);
|
394 |
|
|
dbg_i2c_rx16(0); // read 1st data
|
395 |
|
|
if (dbg_i2c_buf !== 16'hcba9) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 1st DATA =====");
|
396 |
|
|
dbg_i2c_rx16(0); // read 2nd data
|
397 |
|
|
if (dbg_i2c_buf !== 16'h8765) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 2nd DATA =====");
|
398 |
|
|
dbg_i2c_rx16(0); // read 3rd data
|
399 |
|
|
if (dbg_i2c_buf !== 16'h4321) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 3rd DATA =====");
|
400 |
|
|
dbg_i2c_rx16(0); // read 4th data
|
401 |
|
|
if (dbg_i2c_buf !== 16'h0123) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 4th DATA =====");
|
402 |
|
|
dbg_i2c_rx16(1); // read 5th data
|
403 |
|
|
if (dbg_i2c_buf !== 16'h4567) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 5th DATA =====");
|
404 |
|
|
|
405 |
|
|
|
406 |
|
|
// TEST 8B WRITE BURSTS (MEMORY)
|
407 |
|
|
//--------------------------------------------------------
|
408 |
|
|
step = 11;
|
409 |
|
|
|
410 |
|
|
dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0210
|
411 |
|
|
dbg_i2c_wr(MEM_CNT, 16'h0004); // 5 consecutive access
|
412 |
202 |
olivier.gi |
|
413 |
154 |
olivier.gi |
dbg_i2c_wr(MEM_CTL, 16'h000b); // Start burst to 8 bit memory write
|
414 |
|
|
dbg_i2c_burst_start(0);
|
415 |
|
|
dbg_i2c_tx8(8'h91, 0); // write 1st data
|
416 |
|
|
repeat(12) @(posedge mclk);
|
417 |
|
|
if (mem200 !== 16'h1291) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
|
418 |
|
|
dbg_i2c_tx8(8'h82, 0); // write 2nd data
|
419 |
|
|
repeat(12) @(posedge mclk);
|
420 |
|
|
if (mem200 !== 16'h8291) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
|
421 |
|
|
dbg_i2c_tx8(8'h73, 0); // write 3rd data
|
422 |
|
|
repeat(12) @(posedge mclk);
|
423 |
|
|
if (mem202 !== 16'h5673) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
|
424 |
|
|
dbg_i2c_tx8(8'h64, 0); // write 4th data
|
425 |
|
|
repeat(12) @(posedge mclk);
|
426 |
|
|
if (mem202 !== 16'h6473) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
|
427 |
|
|
dbg_i2c_tx8(8'h55, 1); // write 5th data
|
428 |
|
|
repeat(12) @(posedge mclk);
|
429 |
|
|
if (mem204 !== 16'h9a55) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
|
430 |
202 |
olivier.gi |
|
431 |
154 |
olivier.gi |
step = 12;
|
432 |
|
|
dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
|
433 |
|
|
dbg_i2c_wr(MEM_CNT, 16'h0004); // 5 consecutive access
|
434 |
202 |
olivier.gi |
|
435 |
154 |
olivier.gi |
dbg_i2c_wr(MEM_CTL, 16'h0009); // Start burst to 8 bit registers read
|
436 |
|
|
dbg_i2c_burst_start(1);
|
437 |
|
|
dbg_i2c_rx8(0); // read 1st data
|
438 |
|
|
if (dbg_i2c_buf !== 16'h0091) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
|
439 |
|
|
dbg_i2c_rx8(0); // read 2nd data
|
440 |
|
|
if (dbg_i2c_buf !== 16'h0082) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
|
441 |
|
|
dbg_i2c_rx8(1); // read 3rd data
|
442 |
|
|
if (dbg_i2c_buf !== 16'h0073) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
|
443 |
|
|
dbg_i2c_burst_start(1);
|
444 |
|
|
dbg_i2c_rx8(0); // read 4th data
|
445 |
|
|
if (dbg_i2c_buf !== 16'h0064) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
|
446 |
|
|
dbg_i2c_rx8(1); // read 5th data
|
447 |
|
|
if (dbg_i2c_buf !== 16'h0055) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
|
448 |
|
|
|
449 |
|
|
|
450 |
202 |
olivier.gi |
dbg_i2c_wr(CPU_CTL , 16'h0002);
|
451 |
154 |
olivier.gi |
repeat(10) @(posedge mclk);
|
452 |
|
|
|
453 |
|
|
stimulus_done = 1;
|
454 |
|
|
`else
|
455 |
|
|
|
456 |
202 |
olivier.gi |
tb_skip_finish("| (serial debug interface I2C not included) |");
|
457 |
154 |
olivier.gi |
`endif
|
458 |
|
|
`else
|
459 |
202 |
olivier.gi |
tb_skip_finish("| (serial debug interface I2C not included) |");
|
460 |
154 |
olivier.gi |
`endif
|
461 |
|
|
end
|