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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_i2c.v] - Blame information for rev 219

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1 154 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                            DEBUG INTERFACE:  I2C                          */
25
/*---------------------------------------------------------------------------*/
26
/* Test the I2C debug interface:                                             */
27
/*                        - Check RD/WR access to debugg registers.          */
28
/*                        - Check RD Bursts.                                 */
29
/*                        - Check WR Bursts.                                 */
30
/*                                                                           */
31
/* Author(s):                                                                */
32
/*             - Olivier Girard,    olgirard@gmail.com                       */
33
/*                                                                           */
34
/*---------------------------------------------------------------------------*/
35
/* $Rev: 95 $                                                                */
36
/* $LastChangedBy: olivier.girard $                                          */
37
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $          */
38
/*===========================================================================*/
39
 
40
`define LONG_TIMEOUT
41
 
42
reg  [2:0] cpu_version;
43
reg        cpu_asic;
44
reg  [4:0] user_version;
45
reg  [6:0] per_space;
46
reg        mpy_info;
47
reg  [8:0] dmem_size;
48
reg  [5:0] pmem_size;
49
reg [31:0] dbg_id;
50
integer    step;
51 202 olivier.gi
 
52 154 olivier.gi
initial
53
   begin
54
      $display(" ===============================================");
55
      $display("|                 START SIMULATION              |");
56
      $display(" ===============================================");
57
`ifdef DBG_EN
58
`ifdef DBG_I2C
59
      step = 0;
60
      #1 dbg_en = 1;
61
      repeat(30) @(posedge mclk);
62
      stimulus_done = 0;
63
 
64 202 olivier.gi
 
65 154 olivier.gi
   `ifdef DBG_RST_BRK_EN
66
      dbg_i2c_wr(CPU_CTL,  16'h0002);  // RUN
67
   `endif
68
 
69 202 olivier.gi
 
70 154 olivier.gi
      // TEST CPU REGISTERS
71
      //--------------------------------------------------------
72
      step = 1;
73
 
74
      cpu_version  =  `CPU_VERSION;
75
`ifdef ASIC
76
      cpu_asic     =  1'b1;
77
`else
78
      cpu_asic     =  1'b0;
79
`endif
80
      user_version =  `USER_VERSION;
81
      per_space    = (`PER_SIZE  >> 9);
82
`ifdef MULTIPLIER
83
      mpy_info     =  1'b1;
84
`else
85
      mpy_info     =  1'b0;
86
`endif
87
      dmem_size    = (`DMEM_SIZE >> 7);
88
      pmem_size    = (`PMEM_SIZE >> 10);
89
 
90
      dbg_id       = {pmem_size,
91
                      dmem_size,
92
                      mpy_info,
93
                      per_space,
94
                      user_version,
95
                      cpu_asic,
96
                      cpu_version};
97
 
98
      dbg_i2c_wr(CPU_ID_LO  ,  16'hffff);
99
      dbg_i2c_rd(CPU_ID_LO);
100
      if (dbg_i2c_buf !== dbg_id[15:0])  tb_error("====== CPU_ID_LO uncorrect =====");
101
      dbg_i2c_wr(CPU_ID_LO  ,  16'h0000);
102
      dbg_i2c_rd(CPU_ID_LO);
103
      if (dbg_i2c_buf !== dbg_id[15:0])  tb_error("====== CPU_ID_LO uncorrect =====");
104 202 olivier.gi
 
105 154 olivier.gi
      dbg_i2c_wr(CPU_ID_HI  ,  16'hffff);
106
      dbg_i2c_rd(CPU_ID_HI);
107
      if (dbg_i2c_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect =====");
108
      dbg_i2c_wr(CPU_ID_HI  ,  16'h0000);
109
      dbg_i2c_rd(CPU_ID_HI);
110
      if (dbg_i2c_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect =====");
111
 
112
      dbg_i2c_wr(CPU_STAT   ,  16'hffff);
113
      dbg_i2c_rd(CPU_STAT);
114
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== CPU_STAT uncorrect =====");
115
      dbg_i2c_wr(CPU_STAT   ,  16'h0000);
116
      dbg_i2c_rd(CPU_STAT);
117
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== CPU_STAT uncorrect =====");
118
 
119
      dbg_i2c_wr(CPU_CTL    ,  16'hffff);
120
      dbg_i2c_rd(CPU_CTL);
121
      if (dbg_i2c_buf !== 16'h0078)      tb_error("====== CPU_CTL uncorrect =====");
122
      dbg_i2c_wr(CPU_CTL    ,  16'h0000);
123
      dbg_i2c_rd(CPU_CTL);
124
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== CPU_CTL uncorrect =====");
125
 
126 202 olivier.gi
 
127 154 olivier.gi
      // TEST MEMORY CONTROL REGISTERS
128
      //--------------------------------------------------------
129
      step = 2;
130
 
131
      dbg_i2c_wr(MEM_CTL    ,  16'hfffe);
132
      dbg_i2c_rd(MEM_CTL);
133
      if (dbg_i2c_buf !== 16'h000E)      tb_error("====== MEM_CTL uncorrect =====");
134
      dbg_i2c_wr(MEM_CTL    ,  16'h0000);
135
      dbg_i2c_rd(MEM_CTL);
136
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== MEM_CTL uncorrect =====");
137
 
138
      dbg_i2c_wr(MEM_ADDR   ,  16'hffff);
139
      dbg_i2c_rd(MEM_ADDR);
140
      if (dbg_i2c_buf !== 16'hffff)      tb_error("====== MEM_ADDR uncorrect =====");
141
      dbg_i2c_wr(MEM_ADDR   ,  16'h0000);
142
      dbg_i2c_rd(MEM_ADDR);
143
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== MEM_ADDR uncorrect =====");
144
 
145
      dbg_i2c_wr(MEM_DATA   ,  16'hffff);
146
      dbg_i2c_rd(MEM_DATA);
147
      if (dbg_i2c_buf !== 16'hffff)      tb_error("====== MEM_DATA uncorrect =====");
148
      dbg_i2c_wr(MEM_DATA   ,  16'h0000);
149
      dbg_i2c_rd(MEM_DATA);
150
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== MEM_DATA uncorrect =====");
151
 
152
      dbg_i2c_wr(MEM_CNT    ,  16'hffff);
153
      dbg_i2c_rd(MEM_CNT);
154
      if (dbg_i2c_buf !== 16'hffff)      tb_error("====== MEM_CNT uncorrect =====");
155
      dbg_i2c_wr(MEM_CNT    ,  16'h0000);
156
      dbg_i2c_rd(MEM_CNT);
157
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== MEM_CNT uncorrect =====");
158
 
159
 
160
      // TEST HARDWARE BREAKPOINT 0 REGISTERS
161
      //--------------------------------------------------------
162
`ifdef DBG_HWBRK_0
163
      step = 3;
164
      dbg_i2c_wr(BRK0_CTL   ,  16'hffff);
165
      dbg_i2c_rd(BRK0_CTL);
166
      if (`HWBRK_RANGE)
167
        begin
168
           if (dbg_i2c_buf !== 16'h001F)      tb_error("====== BRK0_CTL uncorrect =====");
169
        end
170
      else
171
        begin
172
           if (dbg_i2c_buf !== 16'h000F)      tb_error("====== BRK0_CTL uncorrect =====");
173
        end
174
      dbg_i2c_wr(BRK0_CTL   ,  16'h0000);
175
      dbg_i2c_rd(BRK0_CTL);
176
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK0_CTL uncorrect =====");
177
 
178
      dbg_i2c_wr(BRK0_STAT  ,  16'hffff);
179
      dbg_i2c_rd(BRK0_STAT);
180
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK0_STAT uncorrect =====");
181
      dbg_i2c_wr(BRK0_STAT  ,  16'h0000);
182
      dbg_i2c_rd(BRK0_STAT);
183
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK0_STAT uncorrect =====");
184
 
185
      dbg_i2c_wr(BRK0_ADDR0 ,  16'hffff);
186
      dbg_i2c_rd(BRK0_ADDR0);
187
      if (dbg_i2c_buf !== 16'hffff)      tb_error("====== BRK0_ADDR0 uncorrect =====");
188
      dbg_i2c_wr(BRK0_ADDR0 ,  16'h0000);
189
      dbg_i2c_rd(BRK0_ADDR0);
190
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK0_ADDR0 uncorrect =====");
191
 
192
      dbg_i2c_wr(BRK0_ADDR1 ,  16'hffff);
193
      dbg_i2c_rd(BRK0_ADDR1);
194
      if (dbg_i2c_buf !== 16'hffff)      tb_error("====== BRK0_ADDR1 uncorrect =====");
195
      dbg_i2c_wr(BRK0_ADDR1 ,  16'h0000);
196
      dbg_i2c_rd(BRK0_ADDR1);
197
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK0_ADDR1 uncorrect =====");
198
`endif
199
 
200
      // TEST HARDWARE BREAKPOINT 1 REGISTERS
201
      //--------------------------------------------------------
202
`ifdef DBG_HWBRK_1
203
      step = 4;
204
      dbg_i2c_wr(BRK1_CTL   ,  16'hffff);
205
      dbg_i2c_rd(BRK1_CTL);
206
      if (`HWBRK_RANGE)
207
        begin
208
           if (dbg_i2c_buf !== 16'h001F)      tb_error("====== BRK1_CTL uncorrect =====");
209
        end
210
      else
211
        begin
212
           if (dbg_i2c_buf !== 16'h000F)      tb_error("====== BRK1_CTL uncorrect =====");
213
        end
214
      dbg_i2c_wr(BRK1_CTL   ,  16'h0000);
215
      dbg_i2c_rd(BRK1_CTL);
216
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK1_CTL uncorrect =====");
217
 
218
      dbg_i2c_wr(BRK1_STAT  ,  16'hffff);
219
      dbg_i2c_rd(BRK1_STAT);
220
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK1_STAT uncorrect =====");
221
      dbg_i2c_wr(BRK1_STAT  ,  16'h0000);
222
      dbg_i2c_rd(BRK1_STAT);
223
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK1_STAT uncorrect =====");
224
 
225
      dbg_i2c_wr(BRK1_ADDR0 ,  16'hffff);
226
      dbg_i2c_rd(BRK1_ADDR0);
227
      if (dbg_i2c_buf !== 16'hffff)      tb_error("====== BRK1_ADDR0 uncorrect =====");
228
      dbg_i2c_wr(BRK1_ADDR0 ,  16'h0000);
229
      dbg_i2c_rd(BRK1_ADDR0);
230
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK1_ADDR0 uncorrect =====");
231
 
232
      dbg_i2c_wr(BRK1_ADDR1 ,  16'hffff);
233
      dbg_i2c_rd(BRK1_ADDR1);
234
      if (dbg_i2c_buf !== 16'hffff)      tb_error("====== BRK1_ADDR1 uncorrect =====");
235
      dbg_i2c_wr(BRK1_ADDR1 ,  16'h0000);
236
      dbg_i2c_rd(BRK1_ADDR1);
237
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK1_ADDR1 uncorrect =====");
238
`endif
239
 
240
      // TEST HARDWARE BREAKPOINT 2 REGISTERS
241
      //--------------------------------------------------------
242
`ifdef DBG_HWBRK_2
243
      step = 5;
244
      dbg_i2c_wr(BRK2_CTL   ,  16'hffff);
245
      dbg_i2c_rd(BRK2_CTL);
246
      if (`HWBRK_RANGE)
247
        begin
248
           if (dbg_i2c_buf !== 16'h001F)      tb_error("====== BRK2_CTL uncorrect =====");
249
        end
250
      else
251
        begin
252
           if (dbg_i2c_buf !== 16'h000F)      tb_error("====== BRK2_CTL uncorrect =====");
253
        end
254
      dbg_i2c_wr(BRK2_CTL   ,  16'h0000);
255
      dbg_i2c_rd(BRK2_CTL);
256
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK2_CTL uncorrect =====");
257
 
258
      dbg_i2c_wr(BRK2_STAT  ,  16'hffff);
259
      dbg_i2c_rd(BRK2_STAT);
260
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK2_STAT uncorrect =====");
261
      dbg_i2c_wr(BRK2_STAT  ,  16'h0000);
262
      dbg_i2c_rd(BRK2_STAT);
263
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK2_STAT uncorrect =====");
264
 
265
      dbg_i2c_wr(BRK2_ADDR0 ,  16'hffff);
266
      dbg_i2c_rd(BRK2_ADDR0);
267
      if (dbg_i2c_buf !== 16'hffff)      tb_error("====== BRK2_ADDR0 uncorrect =====");
268
      dbg_i2c_wr(BRK2_ADDR0 ,  16'h0000);
269
      dbg_i2c_rd(BRK2_ADDR0);
270
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK2_ADDR0 uncorrect =====");
271
 
272
      dbg_i2c_wr(BRK2_ADDR1 ,  16'hffff);
273
      dbg_i2c_rd(BRK2_ADDR1);
274
      if (dbg_i2c_buf !== 16'hffff)      tb_error("====== BRK2_ADDR1 uncorrect =====");
275
      dbg_i2c_wr(BRK2_ADDR1 ,  16'h0000);
276
      dbg_i2c_rd(BRK2_ADDR1);
277
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK2_ADDR1 uncorrect =====");
278
`endif
279 202 olivier.gi
 
280 154 olivier.gi
      // TEST HARDWARE BREAKPOINT 3 REGISTERS
281
      //--------------------------------------------------------
282
`ifdef DBG_HWBRK_3
283
      step = 6;
284
      dbg_i2c_wr(BRK3_CTL   ,  16'hffff);
285
      dbg_i2c_rd(BRK3_CTL);
286
      if (`HWBRK_RANGE)
287
        begin
288
           if (dbg_i2c_buf !== 16'h001F)      tb_error("====== BRK3_CTL uncorrect =====");
289
        end
290
      else
291
        begin
292
           if (dbg_i2c_buf !== 16'h000F)      tb_error("====== BRK3_CTL uncorrect =====");
293
        end
294
      dbg_i2c_wr(BRK3_CTL   ,  16'h0000);
295
      dbg_i2c_rd(BRK3_CTL);
296
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK3_CTL uncorrect =====");
297
 
298
      dbg_i2c_wr(BRK3_STAT  ,  16'hffff);
299
      dbg_i2c_rd(BRK3_STAT);
300
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK3_STAT uncorrect =====");
301
      dbg_i2c_wr(BRK3_STAT  ,  16'h0000);
302
      dbg_i2c_rd(BRK3_STAT);
303
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK3_STAT uncorrect =====");
304
 
305
      dbg_i2c_wr(BRK3_ADDR0 ,  16'hffff);
306
      dbg_i2c_rd(BRK3_ADDR0);
307
      if (dbg_i2c_buf !== 16'hffff)      tb_error("====== BRK3_ADDR0 uncorrect =====");
308
      dbg_i2c_wr(BRK3_ADDR0 ,  16'h0000);
309
      dbg_i2c_rd(BRK3_ADDR0);
310
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK3_ADDR0 uncorrect =====");
311
 
312
      dbg_i2c_wr(BRK3_ADDR1 ,  16'hffff);
313
      dbg_i2c_rd(BRK3_ADDR1);
314
      if (dbg_i2c_buf !== 16'hffff)      tb_error("====== BRK3_ADDR1 uncorrect =====");
315
      dbg_i2c_wr(BRK3_ADDR1 ,  16'h0000);
316
      dbg_i2c_rd(BRK3_ADDR1);
317
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== BRK3_ADDR1 uncorrect =====");
318
`endif
319
 
320
      // TEST 16B WRITE BURSTS (MEMORY)
321
      //--------------------------------------------------------
322
      step = 7;
323
 
324
      dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
325
      dbg_i2c_wr(MEM_CNT,  16'h0004);             // 5 consecutive access
326 202 olivier.gi
 
327 154 olivier.gi
      dbg_i2c_wr(MEM_CTL,  16'h0003); // Start burst to 16 bit memory write
328
      dbg_i2c_burst_start(0);
329
      dbg_i2c_tx16(16'h1234, 0);      // write 1st data
330
      repeat(12) @(posedge mclk);
331
      if (mem200 !== 16'h1234)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
332
      dbg_i2c_tx16(16'h5678, 0);      // write 2nd data
333
      repeat(12) @(posedge mclk);
334
      if (mem202 !== 16'h5678)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
335
      dbg_i2c_tx16(16'h9abc, 0);      // write 3rd data
336
      repeat(12) @(posedge mclk);
337
      if (mem204 !== 16'h9abc)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
338
      dbg_i2c_tx16(16'hdef0, 0);      // write 4th data
339
      repeat(12) @(posedge mclk);
340
      if (mem206 !== 16'hdef0)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
341
      dbg_i2c_tx16(16'h0fed, 1);      // write 5th data
342
      repeat(12) @(posedge mclk);
343
      if (mem208 !== 16'h0fed)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
344
 
345
      step = 8;
346
      dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
347
      dbg_i2c_wr(MEM_CNT,  16'h0004);             // 5 consecutive access
348 202 olivier.gi
 
349 154 olivier.gi
      dbg_i2c_wr(MEM_CTL,  16'h0001); // Start burst to 16 bit registers read
350
      dbg_i2c_burst_start(1);
351
      dbg_i2c_rx16(0);                // read 1st data
352
      if (dbg_i2c_buf !== 16'h1234)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
353
      dbg_i2c_rx16(0);                // read 2nd data
354
      if (dbg_i2c_buf !== 16'h5678)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
355
      dbg_i2c_rx16(0);                // read 3rd data
356
      if (dbg_i2c_buf !== 16'h9abc)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
357
      dbg_i2c_rx16(0);                // read 4th data
358
      if (dbg_i2c_buf !== 16'hdef0)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
359
      dbg_i2c_rx16(1);                // read 5th data
360
      if (dbg_i2c_buf !== 16'h0fed)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
361
 
362
 
363
      // TEST 16B WRITE BURSTS (CPU REGISTERS)
364
      //--------------------------------------------------------
365
      step = 9;
366
 
367
      dbg_i2c_wr(MEM_ADDR, 16'h0005); // select R5
368
      dbg_i2c_wr(MEM_CNT,  16'h0004); // 5 consecutive access
369 202 olivier.gi
 
370 154 olivier.gi
      dbg_i2c_wr(MEM_CTL,  16'h0007); // Start burst to 16 bit cpu register write
371
      dbg_i2c_burst_start(0);
372
      dbg_i2c_tx16(16'hcba9, 0);      // write 1st data
373
      repeat(12) @(posedge mclk);
374
      if (r5 !== 16'hcba9)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 1st DATA =====");
375
      dbg_i2c_tx16(16'h8765, 0);      // write 2nd data
376
      repeat(12) @(posedge mclk);
377
      if (r6 !== 16'h8765)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 2nd DATA =====");
378
      dbg_i2c_tx16(16'h4321, 0);      // write 3rd data
379
      repeat(12) @(posedge mclk);
380
      if (r7 !== 16'h4321)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 3rd DATA =====");
381
      dbg_i2c_tx16(16'h0123, 0);      // write 4th data
382
      repeat(12) @(posedge mclk);
383
      if (r8 !== 16'h0123)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 4th DATA =====");
384
      dbg_i2c_tx16(16'h4567, 1);      // write 5th data
385
      repeat(12) @(posedge mclk);
386
      if (r9 !== 16'h4567)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 5th DATA =====");
387 202 olivier.gi
 
388 154 olivier.gi
      step = 10;
389
      dbg_i2c_wr(MEM_ADDR, 16'h0005); // select @0x0200
390
      dbg_i2c_wr(MEM_CNT,  16'h0004); // 5 consecutive access
391 202 olivier.gi
 
392 154 olivier.gi
      dbg_i2c_wr(MEM_CTL,  16'h0005); // Start burst to 16 bit cpu registers read
393
      dbg_i2c_burst_start(1);
394
      dbg_i2c_rx16(0);                // read 1st data
395
      if (dbg_i2c_buf !== 16'hcba9)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 1st DATA =====");
396
      dbg_i2c_rx16(0);                // read 2nd data
397
      if (dbg_i2c_buf !== 16'h8765)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 2nd DATA =====");
398
      dbg_i2c_rx16(0);                // read 3rd data
399
      if (dbg_i2c_buf !== 16'h4321)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 3rd DATA =====");
400
      dbg_i2c_rx16(0);                // read 4th data
401
      if (dbg_i2c_buf !== 16'h0123)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 4th DATA =====");
402
      dbg_i2c_rx16(1);                // read 5th data
403
      if (dbg_i2c_buf !== 16'h4567)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 5th DATA =====");
404
 
405
 
406
      // TEST 8B WRITE BURSTS (MEMORY)
407
      //--------------------------------------------------------
408
      step = 11;
409
 
410
      dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0210
411
      dbg_i2c_wr(MEM_CNT,  16'h0004); // 5 consecutive access
412 202 olivier.gi
 
413 154 olivier.gi
      dbg_i2c_wr(MEM_CTL,  16'h000b); // Start burst to 8 bit memory write
414
      dbg_i2c_burst_start(0);
415
      dbg_i2c_tx8(8'h91, 0);          // write 1st data
416
      repeat(12) @(posedge mclk);
417
      if (mem200 !== 16'h1291)           tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
418
      dbg_i2c_tx8(8'h82, 0);          // write 2nd data
419
      repeat(12) @(posedge mclk);
420
      if (mem200 !== 16'h8291)           tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
421
      dbg_i2c_tx8(8'h73, 0);          // write 3rd data
422
      repeat(12) @(posedge mclk);
423
      if (mem202 !== 16'h5673)           tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
424
      dbg_i2c_tx8(8'h64, 0);          // write 4th data
425
      repeat(12) @(posedge mclk);
426
      if (mem202 !== 16'h6473)           tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
427
      dbg_i2c_tx8(8'h55, 1);          // write 5th data
428
      repeat(12) @(posedge mclk);
429
      if (mem204 !== 16'h9a55)           tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
430 202 olivier.gi
 
431 154 olivier.gi
      step = 12;
432
      dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
433
      dbg_i2c_wr(MEM_CNT,  16'h0004); // 5 consecutive access
434 202 olivier.gi
 
435 154 olivier.gi
      dbg_i2c_wr(MEM_CTL,  16'h0009); // Start burst to 8 bit registers read
436
      dbg_i2c_burst_start(1);
437
      dbg_i2c_rx8(0);                 // read 1st data
438
      if (dbg_i2c_buf !== 16'h0091)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
439
      dbg_i2c_rx8(0);                 // read 2nd data
440
      if (dbg_i2c_buf !== 16'h0082)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
441
      dbg_i2c_rx8(1);                 // read 3rd data
442
      if (dbg_i2c_buf !== 16'h0073)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
443
      dbg_i2c_burst_start(1);
444
      dbg_i2c_rx8(0);                 // read 4th data
445
      if (dbg_i2c_buf !== 16'h0064)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
446
      dbg_i2c_rx8(1);                 // read 5th data
447
      if (dbg_i2c_buf !== 16'h0055)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
448
 
449
 
450 202 olivier.gi
      dbg_i2c_wr(CPU_CTL    ,  16'h0002);
451 154 olivier.gi
      repeat(10) @(posedge mclk);
452
 
453
      stimulus_done = 1;
454
`else
455
 
456 202 olivier.gi
       tb_skip_finish("|   (serial debug interface I2C not included)   |");
457 154 olivier.gi
`endif
458
`else
459 202 olivier.gi
       tb_skip_finish("|   (serial debug interface I2C not included)   |");
460 154 olivier.gi
`endif
461
   end

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