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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_i2c_cpu.v] - Blame information for rev 162

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            DEBUG INTERFACE                                */
/*---------------------------------------------------------------------------*/
/* Test the debug interface:                                                 */
/*                           - CPU Control features.                         */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 95 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $          */
/*===========================================================================*/
 
`define LONG_TIMEOUT
 
   integer my_test;
   integer test_var;
 
 
initial
   begin
      $display(" ===============================================");
      $display("|                 START SIMULATION              |");
      $display(" ===============================================");
`ifdef DBG_EN
`ifdef DBG_I2C
      #1 dbg_en = 1;
      repeat(30) @(posedge mclk);
      stimulus_done = 0;
 
   `ifdef DBG_RST_BRK_EN
      dbg_i2c_wr(CPU_CTL,  16'h0002);  // RUN
   `endif
 
 
      // STOP, FREEZE, ISTEP, RUN
      //--------------------------------------------------------
 
      dbg_i2c_wr(CPU_STAT,  16'h00ff); // HALT
      dbg_i2c_rd(CPU_STAT);            // READ STATUS
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== STOP, FREEZE, ISTEP, RUN: status test 1 =====");
 
      dbg_i2c_wr(CPU_CTL,  16'h0001);  // HALT
      repeat(10) @(posedge mclk);
      test_var = inst_number;
      repeat(50) @(posedge mclk);
      if (test_var !== inst_number)       tb_error("====== STOP, FREEZE, ISTEP, RUN: HALT function =====");
 
      dbg_i2c_rd(CPU_STAT);            // READ STATUS
      if (dbg_i2c_buf !== 16'h0001)      tb_error("====== STOP, FREEZE, ISTEP, RUN: HALT status - test 1 =====");
 
      if (dbg_freeze !== 1'b0)            tb_error("====== STOP, FREEZE, ISTEP, RUN: FREEZE value - test 1 =====");
      dbg_i2c_wr(CPU_CTL,  16'h0010);  // FREEZE WITH BREAK
      repeat(10) @(posedge mclk);
      if (dbg_freeze !== 1'b1)            tb_error("====== STOP, FREEZE, ISTEP, RUN: FREEZE value - test 2 =====");
 
 
      test_var = r14;
      dbg_i2c_wr(CPU_CTL,  16'h0004); // ISTEP
      dbg_i2c_wr(CPU_CTL,  16'h0004); // ISTEP
      repeat(12) @(posedge mclk);
      if (test_var !== (r14+1))           tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 1 =====");
      dbg_i2c_wr(CPU_CTL,  16'h0004); // ISTEP
      dbg_i2c_wr(CPU_CTL,  16'h0004); // ISTEP
      repeat(12) @(posedge mclk);
      if (test_var !== (r14+2))           tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 2 =====");
      dbg_i2c_wr(CPU_CTL,  16'h0004); // ISTEP
      dbg_i2c_wr(CPU_CTL,  16'h0004); // ISTEP
      repeat(12) @(posedge mclk);
      if (test_var !== (r14+3))           tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 3 =====");
 
 
      test_var = inst_number;
      dbg_i2c_wr(CPU_CTL,  16'h0002); // RUN
      repeat(50) @(posedge mclk);
      if (test_var === inst_number)       tb_error("====== STOP, FREEZE, ISTEP, RUN: RUN function - test 1 =====");
      test_var = inst_number;
      repeat(50) @(posedge mclk);
      if (test_var === inst_number)       tb_error("====== STOP, FREEZE, ISTEP, RUN: RUN function - test 2 =====");
 
      dbg_i2c_rd(CPU_STAT);           // READ STATUS
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== STOP/RUN, ISTEP: HALT status - test 2 =====");
 
 
 
      // RESET / BREAK ON RESET
      //--------------------------------------------------------
 
      test_var = r14;
      dbg_i2c_wr(CPU_CTL,  16'h0040); // RESET CPU
      dbg_i2c_rd(CPU_STAT);           // READ STATUS
      if (dbg_i2c_buf !== 16'h0004)      tb_error("====== RESET / BREAK ON RESET: RESET error- test 1 =====");
      if (puc_rst      !== 1'b1)          tb_error("====== RESET / BREAK ON RESET: RESET error- test 2 =====");
      dbg_i2c_wr(CPU_CTL,  16'h0000); // RELEASE RESET
      dbg_i2c_rd(CPU_STAT);           // READ STATUS
      if (dbg_i2c_buf !== 16'h0004)      tb_error("====== RESET / BREAK ON RESET: RESET error- test 3 =====");
      if (puc_rst      !== 1'b0)          tb_error("====== RESET / BREAK ON RESET: RESET error- test 4 =====");
      if (test_var >= r14)                tb_error("====== RESET / BREAK ON RESET: RESET error- test 5 =====");
      dbg_i2c_wr(CPU_STAT,  16'h0004); // CLEAR STATUS
      dbg_i2c_rd(CPU_STAT);            // READ STATUS
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== RESET / BREAK ON RESET: RESET error- test 6 =====");
 
 
      test_var = r14;
      dbg_i2c_wr(CPU_CTL,  16'h0060); // RESET & BREAK ON RESET
      dbg_i2c_rd(CPU_STAT);           // READ STATUS
      if (dbg_i2c_buf !== 16'h0004)      tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 1 =====");
      if (puc_rst      !== 1'b1)          tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 2 =====");
      dbg_i2c_wr(CPU_CTL,  16'h0020); // RELEASE RESET
      dbg_i2c_rd(CPU_STAT);           // READ STATUS
      if (dbg_i2c_buf !== 16'h0005)      tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 3 =====");
      if (puc_rst      !== 1'b0)          tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 4 =====");
      repeat(10) @(posedge mclk);
      test_var = inst_number;
      repeat(50) @(posedge mclk);
      if (test_var !== inst_number)       tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 5 =====");
      if (r0       !== irq_vect_15)       tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 6 =====");
 
      dbg_i2c_wr(CPU_STAT,  16'h0004); // CLEAR STATUS
      dbg_i2c_rd(CPU_STAT);            // READ STATUS
      if (dbg_i2c_buf !== 16'h0001)      tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 7 =====");
 
      dbg_i2c_wr(CPU_CTL,  16'h0002);  // RUN
      dbg_i2c_rd(CPU_STAT);            // READ STATUS
      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 8 =====");
 
 
      // SOFTWARE BREAKPOINT
      //--------------------------------------------------------
 
      dbg_i2c_wr(CPU_CTL,  16'h0048);  // RESET & ENABLE SOFTWARE BREAKPOINT
      dbg_i2c_wr(CPU_CTL,  16'h0008);  // RELEASE RESET
      dbg_i2c_rd(CPU_STAT);            // READ STATUS
      if (dbg_i2c_buf !== 16'h000D)      tb_error("====== SOFTWARE BREAKPOINT: test 1 =====");
      if (r0           !== ('h10000-`PMEM_SIZE+'h12))      tb_error("====== SOFTWARE BREAKPOINT: test 2 =====");
      dbg_i2c_wr(CPU_STAT,  16'h000C); // CLEAR STATUS
      dbg_i2c_rd(CPU_STAT);            // READ STATUS
      if (dbg_i2c_buf !== 16'h0001)      tb_error("====== SOFTWARE BREAKPOINT: test 3 =====");
 
      // Replace software breakpoint with a mov #2, r15 (opcode=0x432f)
      dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h12));
      dbg_i2c_wr(MEM_DATA, 16'h432f);
      dbg_i2c_wr(MEM_CTL,  16'h0003);
 
      // Dummy write
      dbg_i2c_wr(MEM_ADDR, 16'hff00);
      dbg_i2c_wr(MEM_DATA, 16'h1234);
      dbg_i2c_wr(MEM_CTL,  16'h0003);
 
      // RUN
      dbg_i2c_wr(CPU_CTL,  16'h000A);
      repeat(20) @(posedge mclk);
      if (r15     !== 16'h0002)           tb_error("====== SOFTWARE BREAKPOINT: test 4 =====");
 
      dbg_i2c_rd(CPU_STAT);            // READ STATUS
      if (dbg_i2c_buf !== 16'h0009)      tb_error("====== SOFTWARE BREAKPOINT: test 5 =====");
      if (r0           !== ('h10000-`PMEM_SIZE+'h16))      tb_error("====== SOFTWARE BREAKPOINT: test 6 =====");
      dbg_i2c_wr(CPU_STAT,  16'h0008); // CLEAR STATUS
      dbg_i2c_rd(CPU_STAT);            // READ STATUS
      if (dbg_i2c_buf !== 16'h0001)      tb_error("====== SOFTWARE BREAKPOINT: test 7 =====");
 
 
      // Replace software breakpoint with a mov #4, r15 (opcode=0x422f)
      dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h16));
      dbg_i2c_wr(MEM_DATA, 16'h422f);
      dbg_i2c_wr(MEM_CTL,  16'h0003);
 
      // Dummy write
      dbg_i2c_wr(MEM_ADDR, 16'hff00);
      dbg_i2c_wr(MEM_DATA, 16'h5678);
      dbg_i2c_wr(MEM_CTL,  16'h0003);
 
      // RUN
      dbg_i2c_wr(CPU_CTL,  16'h000A);
      repeat(20) @(posedge mclk);
      if (r15     !== 16'h0004)           tb_error("====== SOFTWARE BREAKPOINT: test 8 =====");
 
 
      stimulus_done = 1;
`else
 
       $display(" ===============================================");
       $display("|               SIMULATION SKIPPED              |");
       $display("|   (serial debug interface I2C not included)   |");
       $display(" ===============================================");
       $finish;
`endif
`else
 
       $display(" ===============================================");
       $display("|               SIMULATION SKIPPED              |");
       $display("|      (serial debug interface not included)    |");
       $display(" ===============================================");
       $finish;
`endif
   end
 

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_i2c_cpu.v] - Blame information for rev 162

Line No.	Rev	Author	Line
1	154	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* DEBUG INTERFACE */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the debug interface: */`
27			`/* - CPU Control features. */`
28			`/* */`
29			`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32			`/---------------------------------------------------------------------------/`
33			`/* $Rev: 95 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */`
36			`/===========================================================================/`
37
38			`define LONG_TIMEOUT
39
40			`integer my_test;`
41			`integer test_var;`
42
43
44			`initial`
45			`begin`
46			`$display(" ===============================================");`
47			`$display("\| START SIMULATION \|");`
48			`$display(" ===============================================");`
49			`ifdef DBG_EN
50			`ifdef DBG_I2C
51			`#1 dbg_en = 1;`
52			`repeat(30) @(posedge mclk);`
53			`stimulus_done = 0;`
54
55			`ifdef DBG_RST_BRK_EN
56			`dbg_i2c_wr(CPU_CTL, 16'h0002); // RUN`
57			`endif
58
59
60			`// STOP, FREEZE, ISTEP, RUN`
61			`//--------------------------------------------------------`
62
63			`dbg_i2c_wr(CPU_STAT, 16'h00ff); // HALT`
64			`dbg_i2c_rd(CPU_STAT); // READ STATUS`
65			`if (dbg_i2c_buf !== 16'h0000) tb_error("====== STOP, FREEZE, ISTEP, RUN: status test 1 =====");`
66
67			`dbg_i2c_wr(CPU_CTL, 16'h0001); // HALT`
68			`repeat(10) @(posedge mclk);`
69			`test_var = inst_number;`
70			`repeat(50) @(posedge mclk);`
71			`if (test_var !== inst_number) tb_error("====== STOP, FREEZE, ISTEP, RUN: HALT function =====");`
72
73			`dbg_i2c_rd(CPU_STAT); // READ STATUS`
74			`if (dbg_i2c_buf !== 16'h0001) tb_error("====== STOP, FREEZE, ISTEP, RUN: HALT status - test 1 =====");`
75
76			`if (dbg_freeze !== 1'b0) tb_error("====== STOP, FREEZE, ISTEP, RUN: FREEZE value - test 1 =====");`
77			`dbg_i2c_wr(CPU_CTL, 16'h0010); // FREEZE WITH BREAK`
78			`repeat(10) @(posedge mclk);`
79			`if (dbg_freeze !== 1'b1) tb_error("====== STOP, FREEZE, ISTEP, RUN: FREEZE value - test 2 =====");`
80
81
82			`test_var = r14;`
83			`dbg_i2c_wr(CPU_CTL, 16'h0004); // ISTEP`
84			`dbg_i2c_wr(CPU_CTL, 16'h0004); // ISTEP`
85			`repeat(12) @(posedge mclk);`
86			`if (test_var !== (r14+1)) tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 1 =====");`
87			`dbg_i2c_wr(CPU_CTL, 16'h0004); // ISTEP`
88			`dbg_i2c_wr(CPU_CTL, 16'h0004); // ISTEP`
89			`repeat(12) @(posedge mclk);`
90			`if (test_var !== (r14+2)) tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 2 =====");`
91			`dbg_i2c_wr(CPU_CTL, 16'h0004); // ISTEP`
92			`dbg_i2c_wr(CPU_CTL, 16'h0004); // ISTEP`
93			`repeat(12) @(posedge mclk);`
94			`if (test_var !== (r14+3)) tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 3 =====");`
95
96
97			`test_var = inst_number;`
98			`dbg_i2c_wr(CPU_CTL, 16'h0002); // RUN`
99			`repeat(50) @(posedge mclk);`
100			`if (test_var === inst_number) tb_error("====== STOP, FREEZE, ISTEP, RUN: RUN function - test 1 =====");`
101			`test_var = inst_number;`
102			`repeat(50) @(posedge mclk);`
103			`if (test_var === inst_number) tb_error("====== STOP, FREEZE, ISTEP, RUN: RUN function - test 2 =====");`
104
105			`dbg_i2c_rd(CPU_STAT); // READ STATUS`
106			`if (dbg_i2c_buf !== 16'h0000) tb_error("====== STOP/RUN, ISTEP: HALT status - test 2 =====");`
107
108
109
110			`// RESET / BREAK ON RESET`
111			`//--------------------------------------------------------`
112
113			`test_var = r14;`
114			`dbg_i2c_wr(CPU_CTL, 16'h0040); // RESET CPU`
115			`dbg_i2c_rd(CPU_STAT); // READ STATUS`
116			`if (dbg_i2c_buf !== 16'h0004) tb_error("====== RESET / BREAK ON RESET: RESET error- test 1 =====");`
117			`if (puc_rst !== 1'b1) tb_error("====== RESET / BREAK ON RESET: RESET error- test 2 =====");`
118			`dbg_i2c_wr(CPU_CTL, 16'h0000); // RELEASE RESET`
119			`dbg_i2c_rd(CPU_STAT); // READ STATUS`
120			`if (dbg_i2c_buf !== 16'h0004) tb_error("====== RESET / BREAK ON RESET: RESET error- test 3 =====");`
121			`if (puc_rst !== 1'b0) tb_error("====== RESET / BREAK ON RESET: RESET error- test 4 =====");`
122			`if (test_var >= r14) tb_error("====== RESET / BREAK ON RESET: RESET error- test 5 =====");`
123			`dbg_i2c_wr(CPU_STAT, 16'h0004); // CLEAR STATUS`
124			`dbg_i2c_rd(CPU_STAT); // READ STATUS`
125			`if (dbg_i2c_buf !== 16'h0000) tb_error("====== RESET / BREAK ON RESET: RESET error- test 6 =====");`
126
127
128			`test_var = r14;`
129			`dbg_i2c_wr(CPU_CTL, 16'h0060); // RESET & BREAK ON RESET`
130			`dbg_i2c_rd(CPU_STAT); // READ STATUS`
131			`if (dbg_i2c_buf !== 16'h0004) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 1 =====");`
132			`if (puc_rst !== 1'b1) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 2 =====");`
133			`dbg_i2c_wr(CPU_CTL, 16'h0020); // RELEASE RESET`
134			`dbg_i2c_rd(CPU_STAT); // READ STATUS`
135			`if (dbg_i2c_buf !== 16'h0005) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 3 =====");`
136			`if (puc_rst !== 1'b0) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 4 =====");`
137			`repeat(10) @(posedge mclk);`
138			`test_var = inst_number;`
139			`repeat(50) @(posedge mclk);`
140			`if (test_var !== inst_number) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 5 =====");`
141			`if (r0 !== irq_vect_15) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 6 =====");`
142
143			`dbg_i2c_wr(CPU_STAT, 16'h0004); // CLEAR STATUS`
144			`dbg_i2c_rd(CPU_STAT); // READ STATUS`
145			`if (dbg_i2c_buf !== 16'h0001) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 7 =====");`
146
147			`dbg_i2c_wr(CPU_CTL, 16'h0002); // RUN`
148			`dbg_i2c_rd(CPU_STAT); // READ STATUS`
149			`if (dbg_i2c_buf !== 16'h0000) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 8 =====");`
150
151
152			`// SOFTWARE BREAKPOINT`
153			`//--------------------------------------------------------`
154
155			`dbg_i2c_wr(CPU_CTL, 16'h0048); // RESET & ENABLE SOFTWARE BREAKPOINT`
156			`dbg_i2c_wr(CPU_CTL, 16'h0008); // RELEASE RESET`
157			`dbg_i2c_rd(CPU_STAT); // READ STATUS`
158			`if (dbg_i2c_buf !== 16'h000D) tb_error("====== SOFTWARE BREAKPOINT: test 1 =====");`
159			if (r0 !== ('h10000-`PMEM_SIZE+'h12)) tb_error("====== SOFTWARE BREAKPOINT: test 2 =====");
160			`dbg_i2c_wr(CPU_STAT, 16'h000C); // CLEAR STATUS`
161			`dbg_i2c_rd(CPU_STAT); // READ STATUS`
162			`if (dbg_i2c_buf !== 16'h0001) tb_error("====== SOFTWARE BREAKPOINT: test 3 =====");`
163
164			`// Replace software breakpoint with a mov #2, r15 (opcode=0x432f)`
165			dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h12));
166			`dbg_i2c_wr(MEM_DATA, 16'h432f);`
167			`dbg_i2c_wr(MEM_CTL, 16'h0003);`
168
169			`// Dummy write`
170			`dbg_i2c_wr(MEM_ADDR, 16'hff00);`
171			`dbg_i2c_wr(MEM_DATA, 16'h1234);`
172			`dbg_i2c_wr(MEM_CTL, 16'h0003);`
173
174			`// RUN`
175			`dbg_i2c_wr(CPU_CTL, 16'h000A);`
176			`repeat(20) @(posedge mclk);`
177			`if (r15 !== 16'h0002) tb_error("====== SOFTWARE BREAKPOINT: test 4 =====");`
178
179			`dbg_i2c_rd(CPU_STAT); // READ STATUS`
180			`if (dbg_i2c_buf !== 16'h0009) tb_error("====== SOFTWARE BREAKPOINT: test 5 =====");`
181			if (r0 !== ('h10000-`PMEM_SIZE+'h16)) tb_error("====== SOFTWARE BREAKPOINT: test 6 =====");
182			`dbg_i2c_wr(CPU_STAT, 16'h0008); // CLEAR STATUS`
183			`dbg_i2c_rd(CPU_STAT); // READ STATUS`
184			`if (dbg_i2c_buf !== 16'h0001) tb_error("====== SOFTWARE BREAKPOINT: test 7 =====");`
185
186
187			`// Replace software breakpoint with a mov #4, r15 (opcode=0x422f)`
188			dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h16));
189			`dbg_i2c_wr(MEM_DATA, 16'h422f);`
190			`dbg_i2c_wr(MEM_CTL, 16'h0003);`
191
192			`// Dummy write`
193			`dbg_i2c_wr(MEM_ADDR, 16'hff00);`
194			`dbg_i2c_wr(MEM_DATA, 16'h5678);`
195			`dbg_i2c_wr(MEM_CTL, 16'h0003);`
196
197			`// RUN`
198			`dbg_i2c_wr(CPU_CTL, 16'h000A);`
199			`repeat(20) @(posedge mclk);`
200			`if (r15 !== 16'h0004) tb_error("====== SOFTWARE BREAKPOINT: test 8 =====");`
201
202
203			`stimulus_done = 1;`
204			`else
205
206			`$display(" ===============================================");`
207			`$display("\| SIMULATION SKIPPED \|");`
208			`$display("\| (serial debug interface I2C not included) \|");`
209			`$display(" ===============================================");`
210			`$finish;`
211			`endif
212			`else
213
214			`$display(" ===============================================");`
215			`$display("\| SIMULATION SKIPPED \|");`
216			`$display("\| (serial debug interface not included) \|");`
217			`$display(" ===============================================");`
218			`$finish;`
219			`endif
220			`end`
221