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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_i2c_cpu.v] - Blame information for rev 219

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1 154 olivier.gi
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                            DEBUG INTERFACE                                */
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/*---------------------------------------------------------------------------*/
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/* Test the debug interface:                                                 */
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/*                           - CPU Control features.                         */
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/*                                                                           */
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/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 95 $                                                                */
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/* $LastChangedBy: olivier.girard $                                          */
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/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $          */
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/*===========================================================================*/
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`define LONG_TIMEOUT
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   integer my_test;
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   integer test_var;
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43 202 olivier.gi
 
44 154 olivier.gi
initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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`ifdef DBG_EN
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`ifdef DBG_I2C
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      #1 dbg_en = 1;
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      repeat(30) @(posedge mclk);
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      stimulus_done = 0;
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   `ifdef DBG_RST_BRK_EN
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      dbg_i2c_wr(CPU_CTL,  16'h0002);  // RUN
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   `endif
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59
 
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      // STOP, FREEZE, ISTEP, RUN
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      //--------------------------------------------------------
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      dbg_i2c_wr(CPU_STAT,  16'h00ff); // HALT
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      dbg_i2c_rd(CPU_STAT);            // READ STATUS
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      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== STOP, FREEZE, ISTEP, RUN: status test 1 =====");
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      dbg_i2c_wr(CPU_CTL,  16'h0001);  // HALT
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      repeat(10) @(posedge mclk);
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      test_var = inst_number;
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      repeat(50) @(posedge mclk);
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      if (test_var !== inst_number)       tb_error("====== STOP, FREEZE, ISTEP, RUN: HALT function =====");
72 202 olivier.gi
 
73 154 olivier.gi
      dbg_i2c_rd(CPU_STAT);            // READ STATUS
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      if (dbg_i2c_buf !== 16'h0001)      tb_error("====== STOP, FREEZE, ISTEP, RUN: HALT status - test 1 =====");
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76
      if (dbg_freeze !== 1'b0)            tb_error("====== STOP, FREEZE, ISTEP, RUN: FREEZE value - test 1 =====");
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      dbg_i2c_wr(CPU_CTL,  16'h0010);  // FREEZE WITH BREAK
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      repeat(10) @(posedge mclk);
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      if (dbg_freeze !== 1'b1)            tb_error("====== STOP, FREEZE, ISTEP, RUN: FREEZE value - test 2 =====");
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81 202 olivier.gi
 
82 154 olivier.gi
      test_var = r14;
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      dbg_i2c_wr(CPU_CTL,  16'h0004); // ISTEP
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      dbg_i2c_wr(CPU_CTL,  16'h0004); // ISTEP
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      repeat(12) @(posedge mclk);
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      if (test_var !== (r14+1))           tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 1 =====");
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      dbg_i2c_wr(CPU_CTL,  16'h0004); // ISTEP
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      dbg_i2c_wr(CPU_CTL,  16'h0004); // ISTEP
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      repeat(12) @(posedge mclk);
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      if (test_var !== (r14+2))           tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 2 =====");
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      dbg_i2c_wr(CPU_CTL,  16'h0004); // ISTEP
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      dbg_i2c_wr(CPU_CTL,  16'h0004); // ISTEP
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      repeat(12) @(posedge mclk);
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      if (test_var !== (r14+3))           tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 3 =====");
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96 202 olivier.gi
 
97 154 olivier.gi
      test_var = inst_number;
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      dbg_i2c_wr(CPU_CTL,  16'h0002); // RUN
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      repeat(50) @(posedge mclk);
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      if (test_var === inst_number)       tb_error("====== STOP, FREEZE, ISTEP, RUN: RUN function - test 1 =====");
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      test_var = inst_number;
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      repeat(50) @(posedge mclk);
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      if (test_var === inst_number)       tb_error("====== STOP, FREEZE, ISTEP, RUN: RUN function - test 2 =====");
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105
      dbg_i2c_rd(CPU_STAT);           // READ STATUS
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      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== STOP/RUN, ISTEP: HALT status - test 2 =====");
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108 202 olivier.gi
 
109
 
110 154 olivier.gi
      // RESET / BREAK ON RESET
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      //--------------------------------------------------------
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113
      test_var = r14;
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      dbg_i2c_wr(CPU_CTL,  16'h0040); // RESET CPU
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      dbg_i2c_rd(CPU_STAT);           // READ STATUS
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      if (dbg_i2c_buf !== 16'h0004)      tb_error("====== RESET / BREAK ON RESET: RESET error- test 1 =====");
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      if (puc_rst      !== 1'b1)          tb_error("====== RESET / BREAK ON RESET: RESET error- test 2 =====");
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      dbg_i2c_wr(CPU_CTL,  16'h0000); // RELEASE RESET
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      dbg_i2c_rd(CPU_STAT);           // READ STATUS
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      if (dbg_i2c_buf !== 16'h0004)      tb_error("====== RESET / BREAK ON RESET: RESET error- test 3 =====");
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      if (puc_rst      !== 1'b0)          tb_error("====== RESET / BREAK ON RESET: RESET error- test 4 =====");
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      if (test_var >= r14)                tb_error("====== RESET / BREAK ON RESET: RESET error- test 5 =====");
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      dbg_i2c_wr(CPU_STAT,  16'h0004); // CLEAR STATUS
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      dbg_i2c_rd(CPU_STAT);            // READ STATUS
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      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== RESET / BREAK ON RESET: RESET error- test 6 =====");
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127
 
128
      test_var = r14;
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      dbg_i2c_wr(CPU_CTL,  16'h0060); // RESET & BREAK ON RESET
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      dbg_i2c_rd(CPU_STAT);           // READ STATUS
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      if (dbg_i2c_buf !== 16'h0004)      tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 1 =====");
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      if (puc_rst      !== 1'b1)          tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 2 =====");
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      dbg_i2c_wr(CPU_CTL,  16'h0020); // RELEASE RESET
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      dbg_i2c_rd(CPU_STAT);           // READ STATUS
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      if (dbg_i2c_buf !== 16'h0005)      tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 3 =====");
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      if (puc_rst      !== 1'b0)          tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 4 =====");
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      repeat(10) @(posedge mclk);
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      test_var = inst_number;
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      repeat(50) @(posedge mclk);
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      if (test_var !== inst_number)       tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 5 =====");
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      if (r0       !== irq_vect_15)       tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 6 =====");
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143
      dbg_i2c_wr(CPU_STAT,  16'h0004); // CLEAR STATUS
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      dbg_i2c_rd(CPU_STAT);            // READ STATUS
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      if (dbg_i2c_buf !== 16'h0001)      tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 7 =====");
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      dbg_i2c_wr(CPU_CTL,  16'h0002);  // RUN
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      dbg_i2c_rd(CPU_STAT);            // READ STATUS
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      if (dbg_i2c_buf !== 16'h0000)      tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 8 =====");
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151 202 olivier.gi
 
152 154 olivier.gi
      // SOFTWARE BREAKPOINT
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      //--------------------------------------------------------
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      dbg_i2c_wr(CPU_CTL,  16'h0048);  // RESET & ENABLE SOFTWARE BREAKPOINT
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      dbg_i2c_wr(CPU_CTL,  16'h0008);  // RELEASE RESET
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      dbg_i2c_rd(CPU_STAT);            // READ STATUS
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      if (dbg_i2c_buf !== 16'h000D)      tb_error("====== SOFTWARE BREAKPOINT: test 1 =====");
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      if (r0           !== ('h10000-`PMEM_SIZE+'h12))      tb_error("====== SOFTWARE BREAKPOINT: test 2 =====");
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      dbg_i2c_wr(CPU_STAT,  16'h000C); // CLEAR STATUS
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      dbg_i2c_rd(CPU_STAT);            // READ STATUS
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      if (dbg_i2c_buf !== 16'h0001)      tb_error("====== SOFTWARE BREAKPOINT: test 3 =====");
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      // Replace software breakpoint with a mov #2, r15 (opcode=0x432f)
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      dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h12));
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      dbg_i2c_wr(MEM_DATA, 16'h432f);
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      dbg_i2c_wr(MEM_CTL,  16'h0003);
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      // Dummy write
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      dbg_i2c_wr(MEM_ADDR, 16'hff00);
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      dbg_i2c_wr(MEM_DATA, 16'h1234);
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      dbg_i2c_wr(MEM_CTL,  16'h0003);
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      // RUN
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      dbg_i2c_wr(CPU_CTL,  16'h000A);
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      repeat(20) @(posedge mclk);
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      if (r15     !== 16'h0002)           tb_error("====== SOFTWARE BREAKPOINT: test 4 =====");
178 202 olivier.gi
 
179 154 olivier.gi
      dbg_i2c_rd(CPU_STAT);            // READ STATUS
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      if (dbg_i2c_buf !== 16'h0009)      tb_error("====== SOFTWARE BREAKPOINT: test 5 =====");
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      if (r0           !== ('h10000-`PMEM_SIZE+'h16))      tb_error("====== SOFTWARE BREAKPOINT: test 6 =====");
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      dbg_i2c_wr(CPU_STAT,  16'h0008); // CLEAR STATUS
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      dbg_i2c_rd(CPU_STAT);            // READ STATUS
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      if (dbg_i2c_buf !== 16'h0001)      tb_error("====== SOFTWARE BREAKPOINT: test 7 =====");
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186 202 olivier.gi
 
187 154 olivier.gi
      // Replace software breakpoint with a mov #4, r15 (opcode=0x422f)
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      dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h16));
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      dbg_i2c_wr(MEM_DATA, 16'h422f);
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      dbg_i2c_wr(MEM_CTL,  16'h0003);
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192
      // Dummy write
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      dbg_i2c_wr(MEM_ADDR, 16'hff00);
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      dbg_i2c_wr(MEM_DATA, 16'h5678);
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      dbg_i2c_wr(MEM_CTL,  16'h0003);
196 202 olivier.gi
 
197 154 olivier.gi
      // RUN
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      dbg_i2c_wr(CPU_CTL,  16'h000A);
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      repeat(20) @(posedge mclk);
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      if (r15     !== 16'h0004)           tb_error("====== SOFTWARE BREAKPOINT: test 8 =====");
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202 202 olivier.gi
 
203 154 olivier.gi
      stimulus_done = 1;
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`else
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206 202 olivier.gi
       tb_skip_finish("|   (serial debug interface I2C not included)   |");
207 154 olivier.gi
`endif
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`else
209 202 olivier.gi
       tb_skip_finish("|      (serial debug interface not included)    |");
210 154 olivier.gi
`endif
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   end

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