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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_i2c_hwbrk1.v] - Blame information for rev 219

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1 154 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                            DEBUG INTERFACE                                */
25
/*---------------------------------------------------------------------------*/
26
/* Test the debug interface:                                                 */
27
/*                        - Check Hardware breakpoint unit 1.                */
28
/*                                                                           */
29
/* Author(s):                                                                */
30
/*             - Olivier Girard,    olgirard@gmail.com                       */
31
/*                                                                           */
32
/*---------------------------------------------------------------------------*/
33
/* $Rev: 86 $                                                                */
34
/* $LastChangedBy: olivier.girard $                                          */
35
/* $LastChangedDate: 2011-01-28 23:53:28 +0100 (Fri, 28 Jan 2011) $          */
36
/*===========================================================================*/
37
 
38
`define LONG_TIMEOUT
39 202 olivier.gi
 
40 154 olivier.gi
initial
41
   begin
42
      $display(" ===============================================");
43
      $display("|                 START SIMULATION              |");
44
      $display(" ===============================================");
45
`ifdef DBG_EN
46
`ifdef DBG_I2C
47
`ifdef DBG_HWBRK_1
48
      #1 dbg_en = 1;
49
      repeat(30) @(posedge mclk);
50
      stimulus_done = 0;
51
 
52
   `ifdef DBG_RST_BRK_EN
53
      dbg_i2c_wr(CPU_CTL,  16'h0002);  // RUN
54
   `endif
55
 
56 202 olivier.gi
 
57 154 olivier.gi
      // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES
58
      //----------------------------------------------------------------------
59
 
60
      // RESET & BREAK
61
      dbg_i2c_wr(CPU_CTL, 16'h0060);
62
      dbg_i2c_wr(CPU_CTL, 16'h0020);
63
 
64
      // CONFIGURE BREAKPOINT (DISABLED) & RUN
65
      dbg_i2c_wr(BRK1_ADDR0, ('h10000-`PMEM_SIZE+'h04));
66
      dbg_i2c_wr(BRK1_ADDR1, ('h10000-`PMEM_SIZE+'h18));
67
      dbg_i2c_wr(BRK1_CTL,   16'h000C);
68
      dbg_i2c_wr(CPU_CTL,    16'h0002);
69
      repeat(100) @(posedge mclk);
70
 
71
      // RESET & BREAK
72
      dbg_i2c_wr(CPU_CTL,  16'h0060);
73
      dbg_i2c_wr(CPU_CTL,  16'h0020);
74
      dbg_i2c_wr(CPU_STAT, 16'h00ff);
75
 
76
      // CHECK
77
      if (mem200 === 16'h0000)  tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 1 =====");
78 202 olivier.gi
 
79 154 olivier.gi
      // CONFIGURE BREAKPOINT (ENABLED) & RUN
80
      dbg_i2c_wr(BRK1_ADDR0, ('h10000-`PMEM_SIZE+'h04));
81
      dbg_i2c_wr(BRK1_ADDR1, ('h10000-`PMEM_SIZE+'h18));
82
      dbg_i2c_wr(BRK1_CTL,   16'h000D);
83
      dbg_i2c_wr(CPU_CTL,    16'h0002);
84
      repeat(100) @(posedge mclk);
85
 
86
      // CHECK
87
      if (r0 !== ('h10000-`PMEM_SIZE+'h04))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 2 =====");
88
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 3 =====");
89
      dbg_i2c_rd(CPU_STAT);
90
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 4 =====");
91
      dbg_i2c_rd(BRK1_STAT);
92
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 5 =====");
93
      dbg_i2c_wr(BRK1_STAT, 16'h0001);
94
      dbg_i2c_rd(CPU_STAT);
95
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 6 =====");
96 202 olivier.gi
 
97 154 olivier.gi
      // RE-RUN
98
      dbg_i2c_wr(BRK1_ADDR0, 16'h0000);
99
      dbg_i2c_wr(CPU_CTL,    16'h0002);
100
      repeat(100) @(posedge mclk);
101
 
102
      // RE-CHECK
103
      if (r0 !== ('h10000-`PMEM_SIZE+'h18))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 7 =====");
104
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 8 =====");
105
      dbg_i2c_rd(CPU_STAT);
106
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 9 =====");
107
      dbg_i2c_rd(BRK1_STAT);
108
      if (dbg_i2c_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 10 =====");
109
      dbg_i2c_wr(BRK1_STAT, 16'h0004);
110
      dbg_i2c_rd(CPU_STAT);
111
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 11 =====");
112
 
113
 
114
 
115
      // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE
116
      //----------------------------------------------------------------------
117
      if (`HWBRK_RANGE)
118
        begin
119 202 olivier.gi
 
120 154 olivier.gi
      // RESET, BREAK & CLEAR STATUS
121
      dbg_i2c_wr(CPU_CTL,    16'h0060);
122
      dbg_i2c_wr(CPU_CTL,    16'h0020);
123
      dbg_i2c_wr(BRK1_STAT,  16'h00ff);
124
      dbg_i2c_wr(CPU_STAT,   16'h00ff);
125
 
126
      // CONFIGURE BREAKPOINT(ENABLED) & RUN
127
      dbg_i2c_wr(BRK1_ADDR0, ('h10000-`PMEM_SIZE-'h100));
128
      dbg_i2c_wr(BRK1_ADDR1, ('h10000-`PMEM_SIZE+'h20));
129
      dbg_i2c_wr(BRK1_CTL,   16'h001D);
130
      dbg_i2c_wr(CPU_CTL,    16'h0002);
131
      repeat(100) @(posedge mclk);
132
 
133
      // CHECK
134
      if (r0 !== ('h10000-`PMEM_SIZE))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 1 =====");
135
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 2 =====");
136
      dbg_i2c_rd(CPU_STAT);
137
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 3 =====");
138
      dbg_i2c_rd(BRK1_STAT);
139
      if (dbg_i2c_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 4 =====");
140
      dbg_i2c_wr(BRK1_STAT, 16'h0010);
141
      dbg_i2c_rd(CPU_STAT);
142
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 5 =====");
143
        end
144 202 olivier.gi
 
145
 
146 154 olivier.gi
      // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ
147
      //----------------------------------------------------------------------------
148
 
149
      // RESET, BREAK & CLEAR STATUS
150
      dbg_i2c_wr(CPU_CTL,    16'h0060);
151
      dbg_i2c_wr(CPU_CTL,    16'h0020);
152
      dbg_i2c_wr(BRK1_STAT,  16'h00ff);
153
      dbg_i2c_wr(CPU_STAT,   16'h00ff);
154
 
155 202 olivier.gi
 
156 154 olivier.gi
      // CONFIGURE BREAKPOINT (ENABLED) & RUN
157
      dbg_i2c_wr(BRK1_ADDR0, (`PER_SIZE+16'h0004));
158
      dbg_i2c_wr(BRK1_ADDR1, (`PER_SIZE+16'h0008));
159
      dbg_i2c_wr(BRK1_CTL,   16'h0005);
160
      dbg_i2c_wr(CPU_CTL,    16'h0002);
161
      repeat(100) @(posedge mclk);
162
 
163
      // CHECK
164 175 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h0C))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
165
      if (mem200 !== 16'h0000)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
166 154 olivier.gi
      dbg_i2c_rd(CPU_STAT);
167
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 =====");
168
      dbg_i2c_rd(BRK1_STAT);
169
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 4 =====");
170
      dbg_i2c_wr(BRK1_STAT, 16'h0001);
171
      dbg_i2c_rd(CPU_STAT);
172
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 5 =====");
173 202 olivier.gi
 
174 154 olivier.gi
      // RE-RUN
175
      dbg_i2c_wr(CPU_CTL,    16'h0002);
176
      repeat(100) @(posedge mclk);
177
 
178
      // RE-CHECK
179 175 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h14))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
180 154 olivier.gi
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 =====");
181
      dbg_i2c_rd(CPU_STAT);
182
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 =====");
183
      dbg_i2c_rd(BRK1_STAT);
184
      if (dbg_i2c_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 9 =====");
185
      dbg_i2c_wr(BRK1_STAT, 16'h0004);
186
      dbg_i2c_rd(CPU_STAT);
187
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 10 =====");
188
 
189
      // RE-RUN
190
      dbg_i2c_wr(CPU_CTL,    16'h0002);
191
      repeat(100) @(posedge mclk);
192
 
193
      // CHECK
194
      if (r0 !== ('h10000-`PMEM_SIZE+'h18))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 =====");
195 175 olivier.gi
      if (mem200 !== 16'h0001)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
196 154 olivier.gi
      dbg_i2c_rd(CPU_STAT);
197
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 =====");
198
      dbg_i2c_rd(BRK1_STAT);
199
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 14 =====");
200
      dbg_i2c_wr(BRK1_STAT, 16'h0001);
201
      dbg_i2c_rd(CPU_STAT);
202
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 15 =====");
203 202 olivier.gi
 
204
 
205 154 olivier.gi
      // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE
206
      //-----------------------------------------------------------------------------
207
 
208
      // RESET, BREAK & CLEAR STATUS
209
      dbg_i2c_wr(CPU_CTL,    16'h0060);
210
      dbg_i2c_wr(CPU_CTL,    16'h0020);
211
      dbg_i2c_wr(BRK1_STAT,  16'h00ff);
212
      dbg_i2c_wr(CPU_STAT,   16'h00ff);
213
 
214 202 olivier.gi
 
215 154 olivier.gi
      // CONFIGURE BREAKPOINT (ENABLED) & RUN
216
      dbg_i2c_wr(BRK1_ADDR0, (`PER_SIZE+16'h0004));
217
      dbg_i2c_wr(BRK1_ADDR1, (`PER_SIZE+16'h0008));
218
      dbg_i2c_wr(BRK1_CTL,   16'h0006);
219
      dbg_i2c_wr(CPU_CTL,    16'h0002);
220
      repeat(100) @(posedge mclk);
221
 
222
      // CHECK
223
      if (r0 !== ('h10000-`PMEM_SIZE+'h3a))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 1 =====");
224
      if (mem200 !== 16'h0000)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 2 =====");
225
      dbg_i2c_rd(CPU_STAT);
226
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 3 =====");
227
      dbg_i2c_rd(BRK1_STAT);
228
      if (dbg_i2c_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 4 =====");
229
      dbg_i2c_wr(BRK1_STAT, 16'h0002);
230
      dbg_i2c_rd(CPU_STAT);
231
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 5 =====");
232 202 olivier.gi
 
233 154 olivier.gi
      // RE-RUN
234
      dbg_i2c_wr(CPU_CTL,    16'h0002);
235
      repeat(100) @(posedge mclk);
236
 
237
      // RE-CHECK
238
      if (r0 !== ('h10000-`PMEM_SIZE+'h44))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 6 =====");
239
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 7 =====");
240
      dbg_i2c_rd(CPU_STAT);
241
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 8 =====");
242
      dbg_i2c_rd(BRK1_STAT);
243
      if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 9 =====");
244
      dbg_i2c_wr(BRK1_STAT, 16'h0008);
245
      dbg_i2c_rd(CPU_STAT);
246
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 10 =====");
247
 
248
      // RE-RUN
249
      dbg_i2c_wr(CPU_CTL,    16'h0002);
250
      repeat(100) @(posedge mclk);
251
 
252
      // RE-CHECK
253
      if (r0 !== ('h10000-`PMEM_SIZE+'h0c))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 11 =====");
254
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 12 =====");
255
      dbg_i2c_rd(CPU_STAT);
256
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 13 =====");
257
      dbg_i2c_rd(BRK1_STAT);
258
      if (dbg_i2c_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 14 =====");
259
      dbg_i2c_wr(BRK1_STAT, 16'h0002);
260
      dbg_i2c_rd(CPU_STAT);
261
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 15 =====");
262
 
263
      // RE-RUN
264
      dbg_i2c_wr(CPU_CTL,    16'h0002);
265
      repeat(100) @(posedge mclk);
266
 
267
      // RE-CHECK
268
      if (r0 !== ('h10000-`PMEM_SIZE+'h14))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 16 =====");
269
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 17 =====");
270
      dbg_i2c_rd(CPU_STAT);
271
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 18 =====");
272
      dbg_i2c_rd(BRK1_STAT);
273
      if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 19 =====");
274
      dbg_i2c_wr(BRK1_STAT, 16'h0008);
275
      dbg_i2c_rd(CPU_STAT);
276
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 20 =====");
277
 
278
      // RE-RUN
279
      dbg_i2c_wr(CPU_CTL,    16'h0002);
280
      repeat(100) @(posedge mclk);
281
 
282
      // RE-CHECK
283
      if (r0 !== ('h10000-`PMEM_SIZE+'h0c))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 21 =====");
284
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 22 =====");
285
      dbg_i2c_rd(CPU_STAT);
286
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 23 =====");
287
      dbg_i2c_rd(BRK1_STAT);
288
      if (dbg_i2c_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 24 =====");
289
      dbg_i2c_wr(BRK1_STAT, 16'h0002);
290
      dbg_i2c_rd(CPU_STAT);
291
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 25 =====");
292
 
293 202 olivier.gi
 
294 154 olivier.gi
      // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE
295
      //----------------------------------------------------------------------------------
296
 
297
      // RESET, BREAK & CLEAR STATUS
298
      dbg_i2c_wr(CPU_CTL,    16'h0060);
299
      dbg_i2c_wr(CPU_CTL,    16'h0020);
300
      dbg_i2c_wr(BRK1_STAT,  16'h00ff);
301
      dbg_i2c_wr(CPU_STAT,   16'h00ff);
302
 
303 202 olivier.gi
 
304 154 olivier.gi
      // CONFIGURE BREAKPOINT (ENABLED) & RUN
305
      dbg_i2c_wr(BRK1_ADDR0, (`PER_SIZE+16'h0004));
306
      dbg_i2c_wr(BRK1_ADDR1, (`PER_SIZE+16'h0008));
307
      dbg_i2c_wr(BRK1_CTL,   16'h0007);
308
      dbg_i2c_wr(CPU_CTL,    16'h0002);
309
      repeat(100) @(posedge mclk);
310
 
311
      // CHECK
312
      if (r0 !== ('h10000-`PMEM_SIZE+'h3a))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 1 =====");
313
      if (mem200 !== 16'h0000)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 2 =====");
314
      dbg_i2c_rd(CPU_STAT);
315
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 3 =====");
316
      dbg_i2c_rd(BRK1_STAT);
317
      if (dbg_i2c_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 4 =====");
318
      dbg_i2c_wr(BRK1_STAT, 16'h0002);
319
      dbg_i2c_rd(CPU_STAT);
320
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 5 =====");
321 202 olivier.gi
 
322 154 olivier.gi
      // RE-RUN
323
      dbg_i2c_wr(CPU_CTL,    16'h0002);
324
      repeat(100) @(posedge mclk);
325
 
326
      // RE-CHECK
327
      if (r0 !== ('h10000-`PMEM_SIZE+'h44))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 6 =====");
328
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 7 =====");
329
      dbg_i2c_rd(CPU_STAT);
330
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 8 =====");
331
      dbg_i2c_rd(BRK1_STAT);
332
      if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 9 =====");
333
      dbg_i2c_wr(BRK1_STAT, 16'h0008);
334
      dbg_i2c_rd(CPU_STAT);
335
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 10 =====");
336
 
337
      // RE-RUN
338
      dbg_i2c_wr(CPU_CTL,    16'h0002);
339
      repeat(100) @(posedge mclk);
340
 
341
      // RE-CHECK
342
      if (r0 !== ('h10000-`PMEM_SIZE+'h0c))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 11 =====");
343
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 12 =====");
344
      dbg_i2c_rd(CPU_STAT);
345
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 =====");
346
      dbg_i2c_rd(BRK1_STAT);
347 175 olivier.gi
      if (dbg_i2c_buf !== 16'h0003) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
348
      dbg_i2c_wr(BRK1_STAT, 16'h0003);
349 154 olivier.gi
      dbg_i2c_rd(CPU_STAT);
350
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 =====");
351
 
352
      // RE-RUN
353
      dbg_i2c_wr(CPU_CTL,    16'h0002);
354
      repeat(100) @(posedge mclk);
355
 
356
      // RE-CHECK
357
      if (r0 !== ('h10000-`PMEM_SIZE+'h14))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 16 =====");
358
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 17 =====");
359
      dbg_i2c_rd(CPU_STAT);
360
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 =====");
361
      dbg_i2c_rd(BRK1_STAT);
362 175 olivier.gi
      if (dbg_i2c_buf !== 16'h000C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
363
      dbg_i2c_wr(BRK1_STAT, 16'h000C);
364 154 olivier.gi
      dbg_i2c_rd(CPU_STAT);
365
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 =====");
366
 
367
      // RE-RUN
368
      dbg_i2c_wr(CPU_CTL,    16'h0002);
369
      repeat(100) @(posedge mclk);
370
 
371
      // CHECK
372
      if (r0 !== ('h10000-`PMEM_SIZE+'h18))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 21 =====");
373
      if (mem200 !== 16'h0001)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 22 =====");
374
      dbg_i2c_rd(CPU_STAT);
375
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 23 =====");
376
      dbg_i2c_rd(BRK1_STAT);
377
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 24 =====");
378
      dbg_i2c_wr(BRK1_STAT, 16'h0001);
379
      dbg_i2c_rd(CPU_STAT);
380
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 25 =====");
381 202 olivier.gi
 
382 154 olivier.gi
      // RE-RUN
383
      dbg_i2c_wr(CPU_CTL,    16'h0002);
384
      repeat(100) @(posedge mclk);
385
 
386
      // RE-CHECK
387
      if (r0 !== ('h10000-`PMEM_SIZE+'h1C))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 26 =====");
388
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 27 =====");
389
      dbg_i2c_rd(CPU_STAT);
390
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 28 =====");
391
      dbg_i2c_rd(BRK1_STAT);
392
      if (dbg_i2c_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 29 =====");
393
      dbg_i2c_wr(BRK1_STAT, 16'h0004);
394
      dbg_i2c_rd(CPU_STAT);
395
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 30 =====");
396
 
397 202 olivier.gi
 
398 154 olivier.gi
      // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ
399
      //----------------------------------------------------------------------------
400
      if (`HWBRK_RANGE)
401
        begin
402
 
403
      // RESET, BREAK & CLEAR STATUS
404
      dbg_i2c_wr(CPU_CTL,    16'h0060);
405
      dbg_i2c_wr(CPU_CTL,    16'h0020);
406
      dbg_i2c_wr(BRK1_STAT,  16'h00ff);
407
      dbg_i2c_wr(CPU_STAT,   16'h00ff);
408
 
409 202 olivier.gi
 
410 154 olivier.gi
      // CONFIGURE BREAKPOINT (ENABLED) & RUN
411
      dbg_i2c_wr(BRK1_ADDR0, (`PER_SIZE+16'h0001));
412
      dbg_i2c_wr(BRK1_ADDR1, (`PER_SIZE+16'h0005));
413
      dbg_i2c_wr(BRK1_CTL,   16'h0015);
414
      dbg_i2c_wr(CPU_CTL,    16'h0002);
415
      repeat(100) @(posedge mclk);
416
 
417
      // CHECK
418 175 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h08))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
419
      if (mem200 !== 16'h0000)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
420 154 olivier.gi
      dbg_i2c_rd(CPU_STAT);
421
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 =====");
422
      dbg_i2c_rd(BRK1_STAT);
423
      if (dbg_i2c_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 4 =====");
424
      dbg_i2c_wr(BRK1_STAT, 16'h0010);
425
      dbg_i2c_rd(CPU_STAT);
426
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 5 =====");
427 202 olivier.gi
 
428 154 olivier.gi
      // RE-RUN
429
      dbg_i2c_wr(CPU_CTL,    16'h0002);
430
      repeat(100) @(posedge mclk);
431
 
432
      // RE-CHECK
433 175 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h0C))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
434
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
435 154 olivier.gi
      dbg_i2c_rd(CPU_STAT);
436
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 =====");
437
      dbg_i2c_rd(BRK1_STAT);
438
      if (dbg_i2c_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 9 =====");
439
      dbg_i2c_wr(BRK1_STAT, 16'h0010);
440
      dbg_i2c_rd(CPU_STAT);
441
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 10 =====");
442
        end
443 202 olivier.gi
 
444
 
445 154 olivier.gi
      // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE
446
      //-----------------------------------------------------------------------------
447
      if (`HWBRK_RANGE)
448
        begin
449
 
450
      // RESET, BREAK & CLEAR STATUS
451
      dbg_i2c_wr(CPU_CTL,    16'h0060);
452
      dbg_i2c_wr(CPU_CTL,    16'h0020);
453
      dbg_i2c_wr(BRK1_STAT,  16'h00ff);
454
      dbg_i2c_wr(CPU_STAT,   16'h00ff);
455
 
456 202 olivier.gi
 
457 154 olivier.gi
      // CONFIGURE BREAKPOINT (ENABLED) & RUN
458
      dbg_i2c_wr(BRK1_ADDR0, (`PER_SIZE+16'h0001));
459
      dbg_i2c_wr(BRK1_ADDR1, (`PER_SIZE+16'h0005));
460
      dbg_i2c_wr(BRK1_CTL,   16'h0016);
461
      dbg_i2c_wr(CPU_CTL,    16'h0002);
462
      repeat(100) @(posedge mclk);
463
 
464
      // CHECK
465
      if (r0 !== ('h10000-`PMEM_SIZE+'h36))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 1 =====");
466
      if (mem200 !== 16'h0000)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 2 =====");
467
      dbg_i2c_rd(CPU_STAT);
468
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 3 =====");
469
      dbg_i2c_rd(BRK1_STAT);
470
      if (dbg_i2c_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 4 =====");
471
      dbg_i2c_wr(BRK1_STAT, 16'h0020);
472
      dbg_i2c_rd(CPU_STAT);
473
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 5 =====");
474 202 olivier.gi
 
475 154 olivier.gi
      // RE-RUN
476
      dbg_i2c_wr(CPU_CTL,    16'h0002);
477
      repeat(100) @(posedge mclk);
478
 
479
      // RE-CHECK
480
      if (r0 !== ('h10000-`PMEM_SIZE+'h3a))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 6 =====");
481
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 7 =====");
482
      dbg_i2c_rd(CPU_STAT);
483
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 8 =====");
484
      dbg_i2c_rd(BRK1_STAT);
485
      if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 9 =====");
486
      dbg_i2c_wr(BRK1_STAT, 16'h0020);
487
      dbg_i2c_rd(CPU_STAT);
488
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 10 =====");
489
 
490
      // RE-RUN
491
      dbg_i2c_wr(CPU_CTL,    16'h0002);
492
      repeat(100) @(posedge mclk);
493
 
494
      // RE-CHECK
495
      if (r0 !== ('h10000-`PMEM_SIZE+'h08))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 11 =====");
496
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 12 =====");
497
      dbg_i2c_rd(CPU_STAT);
498
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 13 =====");
499
      dbg_i2c_rd(BRK1_STAT);
500
      if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 14 =====");
501
      dbg_i2c_wr(BRK1_STAT, 16'h0020);
502
      dbg_i2c_rd(CPU_STAT);
503
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 15 =====");
504
 
505
      // RE-RUN
506
      dbg_i2c_wr(CPU_CTL,    16'h0002);
507
      repeat(100) @(posedge mclk);
508
 
509
      // RE-CHECK
510
      if (r0 !== ('h10000-`PMEM_SIZE+'h0C))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 16 =====");
511
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 17 =====");
512
      dbg_i2c_rd(CPU_STAT);
513
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 18 =====");
514
      dbg_i2c_rd(BRK1_STAT);
515
      if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 19 =====");
516
      dbg_i2c_wr(BRK1_STAT, 16'h0020);
517
      dbg_i2c_rd(CPU_STAT);
518
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 20 =====");
519
 
520
      // RE-RUN
521
      dbg_i2c_wr(CPU_CTL,    16'h0002);
522
      repeat(100) @(posedge mclk);
523
 
524
      // RE-CHECK
525
      if (r0 !== ('h10000-`PMEM_SIZE+'h08))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 21 =====");
526
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 22 =====");
527
      dbg_i2c_rd(CPU_STAT);
528
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 23 =====");
529
      dbg_i2c_rd(BRK1_STAT);
530
      if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 24 =====");
531
      dbg_i2c_wr(BRK1_STAT, 16'h0020);
532
      dbg_i2c_rd(CPU_STAT);
533
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 25 =====");
534
        end
535 202 olivier.gi
 
536 154 olivier.gi
      // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE
537
      //----------------------------------------------------------------------------------
538
      if (`HWBRK_RANGE)
539
        begin
540
 
541
      // RESET, BREAK & CLEAR STATUS
542
      dbg_i2c_wr(CPU_CTL,    16'h0060);
543
      dbg_i2c_wr(CPU_CTL,    16'h0020);
544
      dbg_i2c_wr(BRK1_STAT,  16'h00ff);
545
      dbg_i2c_wr(CPU_STAT,   16'h00ff);
546
 
547 202 olivier.gi
 
548 154 olivier.gi
      // CONFIGURE BREAKPOINT (ENABLED) & RUN
549
      dbg_i2c_wr(BRK1_ADDR0, (`PER_SIZE+16'h0001));
550
      dbg_i2c_wr(BRK1_ADDR1, (`PER_SIZE+16'h0005));
551
      dbg_i2c_wr(BRK1_CTL,   16'h0017);
552
      dbg_i2c_wr(CPU_CTL,    16'h0002);
553
      repeat(100) @(posedge mclk);
554
 
555
      // CHECK
556
      if (r0 !== ('h10000-`PMEM_SIZE+'h36))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 1 =====");
557
      if (mem200 !== 16'h0000)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 2 =====");
558
      dbg_i2c_rd(CPU_STAT);
559
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 3 =====");
560
      dbg_i2c_rd(BRK1_STAT);
561
      if (dbg_i2c_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 4 =====");
562
      dbg_i2c_wr(BRK1_STAT, 16'h0020);
563
      dbg_i2c_rd(CPU_STAT);
564
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 5 =====");
565 202 olivier.gi
 
566 154 olivier.gi
      // RE-RUN
567
      dbg_i2c_wr(CPU_CTL,    16'h0002);
568
      repeat(100) @(posedge mclk);
569
 
570
      // RE-CHECK
571
      if (r0 !== ('h10000-`PMEM_SIZE+'h3a))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 6 =====");
572
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 7 =====");
573
      dbg_i2c_rd(CPU_STAT);
574
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 8 =====");
575
      dbg_i2c_rd(BRK1_STAT);
576
      if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 9 =====");
577
      dbg_i2c_wr(BRK1_STAT, 16'h0020);
578
      dbg_i2c_rd(CPU_STAT);
579
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 10 =====");
580
 
581
      // RE-RUN
582
      dbg_i2c_wr(CPU_CTL,    16'h0002);
583
      repeat(100) @(posedge mclk);
584
 
585
      // RE-CHECK
586
      if (r0 !== ('h10000-`PMEM_SIZE+'h08))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 11 =====");
587
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 12 =====");
588
      dbg_i2c_rd(CPU_STAT);
589
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 =====");
590
      dbg_i2c_rd(BRK1_STAT);
591 175 olivier.gi
      if (dbg_i2c_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
592
      dbg_i2c_wr(BRK1_STAT, 16'h0030);
593 154 olivier.gi
      dbg_i2c_rd(CPU_STAT);
594
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 =====");
595
 
596
      // RE-RUN
597
      dbg_i2c_wr(CPU_CTL,    16'h0002);
598
      repeat(100) @(posedge mclk);
599
 
600
      // RE-CHECK
601
      if (r0 !== ('h10000-`PMEM_SIZE+'h0C))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 16 =====");
602
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 17 =====");
603
      dbg_i2c_rd(CPU_STAT);
604
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 =====");
605
      dbg_i2c_rd(BRK1_STAT);
606 175 olivier.gi
      if (dbg_i2c_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
607
      dbg_i2c_wr(BRK1_STAT, 16'h0030);
608 154 olivier.gi
      dbg_i2c_rd(CPU_STAT);
609
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 =====");
610
 
611
      // RE-RUN
612
      dbg_i2c_wr(CPU_CTL,    16'h0002);
613
      repeat(100) @(posedge mclk);
614
 
615
      // CHECK
616
      if (r0 !== ('h10000-`PMEM_SIZE+'h18))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 21 =====");
617
      if (mem200 !== 16'h0001)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 22 =====");
618
      dbg_i2c_rd(CPU_STAT);
619
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 23 =====");
620
      dbg_i2c_rd(BRK1_STAT);
621
      if (dbg_i2c_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 24 =====");
622
      dbg_i2c_wr(BRK1_STAT, 16'h0010);
623
      dbg_i2c_rd(CPU_STAT);
624
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 25 =====");
625 202 olivier.gi
 
626 154 olivier.gi
      // RE-RUN
627
      dbg_i2c_wr(CPU_CTL,    16'h0002);
628
      repeat(100) @(posedge mclk);
629
 
630
      // RE-CHECK
631
      if (r0 !== ('h10000-`PMEM_SIZE+'h08))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 26 =====");
632
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 27 =====");
633
      dbg_i2c_rd(CPU_STAT);
634
      if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 =====");
635
      dbg_i2c_rd(BRK1_STAT);
636 175 olivier.gi
      if (dbg_i2c_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
637
      dbg_i2c_wr(BRK1_STAT, 16'h0030);
638 154 olivier.gi
      dbg_i2c_rd(CPU_STAT);
639
      if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 =====");
640
 
641
        end
642
 
643
       // RE-RUN UNTIL END OF PATTERN
644
      dbg_i2c_wr(BRK1_CTL,   16'h0000);
645
      dbg_i2c_wr(CPU_CTL,    16'h0002);
646
      repeat(100) @(posedge mclk);
647
 
648 202 olivier.gi
 
649 154 olivier.gi
      stimulus_done = 1;
650
`else
651
 
652 202 olivier.gi
       tb_skip_finish("|   (hardware breakpoint unit 1 not included)   |");
653 154 olivier.gi
`endif
654
`else
655 202 olivier.gi
       tb_skip_finish("|   (serial debug interface I2C not included)   |");
656 154 olivier.gi
`endif
657
`else
658 202 olivier.gi
       tb_skip_finish("|      (serial debug interface not included)    |");
659 154 olivier.gi
`endif
660
   end

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