OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_i2c_mem.s43] - Blame information for rev 219

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 154 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                            DEBUG INTERFACE                                */
25
/*---------------------------------------------------------------------------*/
26
/* Test the debug interface:                                                 */
27
/*                        - Check Memory RD/WR features.                     */
28
/*                                                                           */
29
/*  Note: The burst features are specific to the selected interface          */
30
/*    (UART/I2C) and are therefore tested in the dbg_uart/dbg_i2c patterns   */
31
/*                                                                           */
32
/* Author(s):                                                                */
33
/*             - Olivier Girard,    olgirard@gmail.com                       */
34
/*                                                                           */
35
/*---------------------------------------------------------------------------*/
36
/* $Rev: 19 $                                                                */
37
/* $LastChangedBy: olivier.girard $                                          */
38
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
39
/*===========================================================================*/
40
 
41
.include "pmem_defs.asm"
42
 
43
.global main
44
 
45 200 olivier.gi
        /* ----------------------         SOME VARIABLES IN ROM  --------------- */
46
diverse_data:
47
        .word 0x5ab7
48
        .word 0x6bc8
49
 
50
        /* ----------------------              WAIT FUNCTION     --------------- */
51 154 olivier.gi
WAIT_FUNC:
52
        dec r14
53
        jnz WAIT_FUNC
54
        ret
55 200 olivier.gi
 
56
        /* ----------------------                 MAIN           --------------- */
57 154 olivier.gi
main:
58 200 olivier.gi
        mov   #0x5a10, &WDTCTL  ; # Disable Watchdog
59
 
60 154 olivier.gi
        mov #DMEM_250, r1       ; # Initialize stack pointer
61
 
62
        mov   #0x1122, &DMEM_210
63
        mov   #0x3344, &DMEM_212
64
 
65
        mov   #0xaaaa, r5
66
        mov   #0xbbbb, r6
67
 
68
        mov   #0x2F00, r14
69
        call  #WAIT_FUNC
70
 
71
        mov   #0x1000, r15
72
 
73 200 olivier.gi
 
74 154 olivier.gi
        /* ----------------------         END OF TEST        --------------- */
75
end_of_test:
76
        nop
77
        br #0xffff
78
 
79
        /* ----------------------         INTERRUPT VECTORS  --------------- */
80
 
81
.section .vectors, "a"
82
.word end_of_test        ; Interrupt  0 (lowest priority)    
83
.word end_of_test        ; Interrupt  1                      
84
.word end_of_test        ; Interrupt  2                      
85
.word end_of_test        ; Interrupt  3                      
86
.word end_of_test        ; Interrupt  4                      
87
.word end_of_test        ; Interrupt  5                      
88
.word end_of_test        ; Interrupt  6                      
89
.word end_of_test        ; Interrupt  7                      
90
.word end_of_test        ; Interrupt  8                      
91
.word end_of_test        ; Interrupt  9                      
92
.word end_of_test        ; Interrupt 10                      Watchdog timer
93
.word end_of_test        ; Interrupt 11                      
94
.word end_of_test        ; Interrupt 12                      
95
.word end_of_test        ; Interrupt 13                      
96
.word end_of_test        ; Interrupt 14                      NMI
97
.word main               ; Interrupt 15 (highest priority)   RESET

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.