URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_i2c_onoff.v] - Blame information for rev 219

Go to most recent revision | Details | Compare with Previous | View Log


/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            DEBUG INTERFACE                                */
/*---------------------------------------------------------------------------*/
/* Test the debug interface:                                                 */
/*                           - CPU Control features.                         */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 95 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $          */
/*===========================================================================*/
 
 
   integer test_nr;
   integer test_var;
 
 
initial
   begin
      $display(" ===============================================");
      $display("|                 START SIMULATION              |");
      $display(" ===============================================");
`ifdef DBG_EN
`ifdef DBG_I2C
  `ifdef ASIC_CLOCKING
      tb_skip_finish("|   (this test is not supported in ASIC mode)   |");
  `else
      test_nr = 0;
      #1 dbg_en = 0;
      repeat(30) @(posedge mclk);
      stimulus_done = 0;
 
      // Make sure the CPU always starts executing when the
      // debug interface is disabled during POR.
      //--------------------------------------------------------
      dbg_en  = 0;
      test_nr = 1;
 
      repeat(300) @(posedge mclk);
      if (r14 === 16'h0000)       tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 =====");
      test_var = r14;
 
 
      // Make sure that enabling the debug interface after the POR
      // don't stop the cpu
      //--------------------------------------------------------
      dbg_en  = 1;
      test_nr = 2;
 
      repeat(300) @(posedge mclk);
      if (r14 === test_var[15:0]) tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 2 =====");
 
 
      // Create POR with debug enable and observe the
      // behavior depending on the DBG_RST_BRK_EN define
      //--------------------------------------------------------
      dbg_en  = 1;
      test_nr = 3;
 
      @(posedge mclk); // Generate POR
      reset_n = 1'b0;
      @(posedge mclk);
      reset_n = 1'b1;
 
      repeat(300) @(posedge mclk);
`ifdef DBG_RST_BRK_EN
      if (r14 !== 16'h0000)       tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 =====");
`else
      if (r14 === 16'h0000)       tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 =====");
`endif
 
      // Check CPU_CTL reset value
      dbg_i2c_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
      if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value -  test 4 =====");
`else
      if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value -  test 4 =====");
`endif
 
 
      // Make sure that DBG_EN resets the debug interface
      //--------------------------------------------------------
      test_nr = 4;
 
      // Let the CPU run
      dbg_i2c_wr(CPU_CTL,  16'h0002);
 
      repeat(300) @(posedge mclk);
      dbg_i2c_wr(CPU_CTL,   16'h0000);
      dbg_i2c_wr(MEM_DATA,  16'haa55);
      dbg_i2c_rd(CPU_CTL);
      if (dbg_i2c_buf !== 16'h0000)  tb_error("====== CPU_CTL write access failed  - test 5 =====");
      dbg_i2c_rd(MEM_DATA);
      if (dbg_i2c_buf !== 16'haa55)  tb_error("====== MEM_DATA write access failed - test 6 =====");
 
 
      test_var = r14;  // Backup the current register value
 
 
      @(posedge mclk); // Resets the debug interface
      dbg_en = 1'b0;
      repeat(2) @(posedge mclk);
      dbg_en = 1'b1;
 
      // Make sure that the register was not reseted
      if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN -  test 7 =====");
      repeat(2) @(posedge mclk);
 
      // Check CPU_CTL reset value
      dbg_i2c_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
      if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value -  test 8 =====");
`else
      if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value -  test 8 =====");
`endif
      dbg_i2c_rd(MEM_DATA);
      if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
 
 
      // Make sure that RESET_N resets the debug interface
      //--------------------------------------------------------
      test_nr = 5;
 
      // Let the CPU run
      dbg_i2c_wr(CPU_CTL,  16'h0002);
 
      repeat(300) @(posedge mclk);
      dbg_i2c_wr(CPU_CTL,   16'h0000);
      dbg_i2c_wr(MEM_DATA,  16'haa55);
      dbg_i2c_rd(CPU_CTL);
      if (dbg_i2c_buf !== 16'h0000)  tb_error("====== CPU_CTL write access failed  - test 10 =====");
      dbg_i2c_rd(MEM_DATA);
      if (dbg_i2c_buf !== 16'haa55)  tb_error("====== MEM_DATA write access failed - test 11 =====");
 
      test_nr = 6;
 
      @(posedge mclk); // Generates POR
      reset_n = 1'b0;
      repeat(2) @(posedge mclk);
      reset_n = 1'b1;
 
      // Make sure that the register was reseted
      if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N -  test 12 =====");
      repeat(2) @(posedge mclk);
 
      test_nr = 7;
 
      // Check CPU_CTL reset value
      dbg_i2c_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
      if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value -  test 8 =====");
`else
      if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value -  test 8 =====");
`endif
      dbg_i2c_rd(MEM_DATA);
      if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
 
 
      // Let the CPU run
      dbg_i2c_wr(CPU_CTL,  16'h0002);
 
      test_nr = 8;
 
      // Generate IRQ to terminate the test pattern
      irq[`IRQ_NR-15] = 1'b1;
      @(r13);
      irq[`IRQ_NR-15] = 1'b0;
 
      stimulus_done = 1;
 
  `endif
`else
 
       tb_skip_finish("|   (serial debug interface I2C not included)   |");
`endif
`else
       tb_skip_finish("|      (serial debug interface not included)    |");
`endif
   end

Line No.	Rev	Author	Line
1	154	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* DEBUG INTERFACE */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the debug interface: */`
27			`/* - CPU Control features. */`
28			`/* */`
29			`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32			`/---------------------------------------------------------------------------/`
33			`/* $Rev: 95 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */`
36			`/===========================================================================/`
37
38
39			`integer test_nr;`
40			`integer test_var;`
41
42	200	olivier.gi
43	154	olivier.gi	`initial`
44			`begin`
45			`$display(" ===============================================");`
46			`$display("\| START SIMULATION \|");`
47			`$display(" ===============================================");`
48			`ifdef DBG_EN
49			`ifdef DBG_I2C
50	180	olivier.gi	`ifdef ASIC_CLOCKING
51	202	olivier.gi	`tb_skip_finish("\| (this test is not supported in ASIC mode) \|");`
52	154	olivier.gi	`else
53			`test_nr = 0;`
54			`#1 dbg_en = 0;`
55			`repeat(30) @(posedge mclk);`
56			`stimulus_done = 0;`
57
58			`// Make sure the CPU always starts executing when the`
59			`// debug interface is disabled during POR.`
60			`//--------------------------------------------------------`
61			`dbg_en = 0;`
62			`test_nr = 1;`
63
64			`repeat(300) @(posedge mclk);`
65			`if (r14 === 16'h0000) tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 =====");`
66			`test_var = r14;`
67	200	olivier.gi
68
69	154	olivier.gi	`// Make sure that enabling the debug interface after the POR`
70			`// don't stop the cpu`
71			`//--------------------------------------------------------`
72			`dbg_en = 1;`
73			`test_nr = 2;`
74	200	olivier.gi
75	154	olivier.gi	`repeat(300) @(posedge mclk);`
76			`if (r14 === test_var[15:0]) tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 2 =====");`
77
78	200	olivier.gi
79	154	olivier.gi	`// Create POR with debug enable and observe the`
80			`// behavior depending on the DBG_RST_BRK_EN define`
81			`//--------------------------------------------------------`
82			`dbg_en = 1;`
83			`test_nr = 3;`
84	200	olivier.gi
85	154	olivier.gi	`@(posedge mclk); // Generate POR`
86			`reset_n = 1'b0;`
87			`@(posedge mclk);`
88			`reset_n = 1'b1;`
89	200	olivier.gi
90	154	olivier.gi	`repeat(300) @(posedge mclk);`
91			`ifdef DBG_RST_BRK_EN
92			`if (r14 !== 16'h0000) tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 =====");`
93			`else
94			`if (r14 === 16'h0000) tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 =====");`
95			`endif
96
97			`// Check CPU_CTL reset value`
98			`dbg_i2c_rd(CPU_CTL);`
99			`ifdef DBG_RST_BRK_EN
100			`if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 4 =====");`
101			`else
102	200	olivier.gi	`if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 4 =====");`
103	154	olivier.gi	`endif
104
105
106			`// Make sure that DBG_EN resets the debug interface`
107			`//--------------------------------------------------------`
108			`test_nr = 4;`
109
110			`// Let the CPU run`
111			`dbg_i2c_wr(CPU_CTL, 16'h0002);`
112
113			`repeat(300) @(posedge mclk);`
114			`dbg_i2c_wr(CPU_CTL, 16'h0000);`
115			`dbg_i2c_wr(MEM_DATA, 16'haa55);`
116			`dbg_i2c_rd(CPU_CTL);`
117			`if (dbg_i2c_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 5 =====");`
118			`dbg_i2c_rd(MEM_DATA);`
119			`if (dbg_i2c_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 6 =====");`
120
121	200	olivier.gi
122	154	olivier.gi	`test_var = r14; // Backup the current register value`
123
124	200	olivier.gi
125	154	olivier.gi	`@(posedge mclk); // Resets the debug interface`
126			`dbg_en = 1'b0;`
127			`repeat(2) @(posedge mclk);`
128			`dbg_en = 1'b1;`
129
130			`// Make sure that the register was not reseted`
131			`if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN - test 7 =====");`
132	200	olivier.gi	`repeat(2) @(posedge mclk);`
133
134	154	olivier.gi	`// Check CPU_CTL reset value`
135			`dbg_i2c_rd(CPU_CTL);`
136			`ifdef DBG_RST_BRK_EN
137			`if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 =====");`
138			`else
139	200	olivier.gi	`if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 =====");`
140	154	olivier.gi	`endif
141			`dbg_i2c_rd(MEM_DATA);`
142			`if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");`
143
144
145			`// Make sure that RESET_N resets the debug interface`
146			`//--------------------------------------------------------`
147			`test_nr = 5;`
148
149			`// Let the CPU run`
150			`dbg_i2c_wr(CPU_CTL, 16'h0002);`
151
152			`repeat(300) @(posedge mclk);`
153			`dbg_i2c_wr(CPU_CTL, 16'h0000);`
154			`dbg_i2c_wr(MEM_DATA, 16'haa55);`
155			`dbg_i2c_rd(CPU_CTL);`
156			`if (dbg_i2c_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 10 =====");`
157			`dbg_i2c_rd(MEM_DATA);`
158			`if (dbg_i2c_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 11 =====");`
159
160			`test_nr = 6;`
161
162			`@(posedge mclk); // Generates POR`
163			`reset_n = 1'b0;`
164			`repeat(2) @(posedge mclk);`
165			`reset_n = 1'b1;`
166
167			`// Make sure that the register was reseted`
168			`if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N - test 12 =====");`
169			`repeat(2) @(posedge mclk);`
170	200	olivier.gi
171	154	olivier.gi	`test_nr = 7;`
172
173			`// Check CPU_CTL reset value`
174			`dbg_i2c_rd(CPU_CTL);`
175			`ifdef DBG_RST_BRK_EN
176			`if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 =====");`
177			`else
178	200	olivier.gi	`if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 =====");`
179	154	olivier.gi	`endif
180			`dbg_i2c_rd(MEM_DATA);`
181			`if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");`
182
183	200	olivier.gi
184	154	olivier.gi	`// Let the CPU run`
185			`dbg_i2c_wr(CPU_CTL, 16'h0002);`
186
187			`test_nr = 8;`
188
189			`// Generate IRQ to terminate the test pattern`
190	200	olivier.gi	irq[`IRQ_NR-15] = 1'b1;
191	154	olivier.gi	`@(r13);`
192	200	olivier.gi	irq[`IRQ_NR-15] = 1'b0;
193
194	154	olivier.gi	`stimulus_done = 1;`
195
196			`endif
197			`else
198
199	202	olivier.gi	`tb_skip_finish("\| (serial debug interface I2C not included) \|");`
200	154	olivier.gi	`endif
201			`else
202	202	olivier.gi	`tb_skip_finish("\| (serial debug interface not included) \|");`
203	154	olivier.gi	`endif
204			`end`

Browse

Tools

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_i2c_onoff.v] - Blame information for rev 219