1 |
154 |
olivier.gi |
/*===========================================================================*/
|
2 |
|
|
/* Copyright (C) 2001 Authors */
|
3 |
|
|
/* */
|
4 |
|
|
/* This source file may be used and distributed without restriction provided */
|
5 |
|
|
/* that this copyright statement is not removed from the file and that any */
|
6 |
|
|
/* derivative work contains the original copyright notice and the associated */
|
7 |
|
|
/* disclaimer. */
|
8 |
|
|
/* */
|
9 |
|
|
/* This source file is free software; you can redistribute it and/or modify */
|
10 |
|
|
/* it under the terms of the GNU Lesser General Public License as published */
|
11 |
|
|
/* by the Free Software Foundation; either version 2.1 of the License, or */
|
12 |
|
|
/* (at your option) any later version. */
|
13 |
|
|
/* */
|
14 |
|
|
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
|
15 |
|
|
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
|
16 |
|
|
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
|
17 |
|
|
/* License for more details. */
|
18 |
|
|
/* */
|
19 |
|
|
/* You should have received a copy of the GNU Lesser General Public License */
|
20 |
|
|
/* along with this source; if not, write to the Free Software Foundation, */
|
21 |
|
|
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
|
22 |
|
|
/* */
|
23 |
|
|
/*===========================================================================*/
|
24 |
|
|
/* DEBUG INTERFACE: RD / WR */
|
25 |
|
|
/*---------------------------------------------------------------------------*/
|
26 |
|
|
/* Test the UART debug interface: */
|
27 |
|
|
/* - Check RD/WR access to all adressable */
|
28 |
|
|
/* debug registers. */
|
29 |
|
|
/* */
|
30 |
|
|
/* Author(s): */
|
31 |
|
|
/* - Olivier Girard, olgirard@gmail.com */
|
32 |
|
|
/* */
|
33 |
|
|
/*---------------------------------------------------------------------------*/
|
34 |
|
|
/* $Rev: 95 $ */
|
35 |
|
|
/* $LastChangedBy: olivier.girard $ */
|
36 |
|
|
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
|
37 |
|
|
/*===========================================================================*/
|
38 |
|
|
|
39 |
|
|
`define LONG_TIMEOUT
|
40 |
|
|
|
41 |
|
|
reg [2:0] cpu_version;
|
42 |
|
|
reg cpu_asic;
|
43 |
|
|
reg [4:0] user_version;
|
44 |
|
|
reg [6:0] per_space;
|
45 |
|
|
reg mpy_info;
|
46 |
|
|
reg [8:0] dmem_size;
|
47 |
|
|
reg [5:0] pmem_size;
|
48 |
|
|
reg [31:0] dbg_id;
|
49 |
|
|
|
50 |
|
|
// Set oMSP parameters for later check
|
51 |
|
|
defparam dut.INST_NR = 8'h12;
|
52 |
|
|
defparam dut.TOTAL_NR = 8'h34;
|
53 |
|
|
|
54 |
|
|
integer ii;
|
55 |
|
|
|
56 |
|
|
|
57 |
|
|
initial
|
58 |
|
|
begin
|
59 |
|
|
$display(" ===============================================");
|
60 |
|
|
$display("| START SIMULATION |");
|
61 |
|
|
$display(" ===============================================");
|
62 |
|
|
`ifdef DBG_EN
|
63 |
|
|
`ifdef DBG_I2C
|
64 |
|
|
#1 dbg_en = 1;
|
65 |
|
|
repeat(30) @(posedge mclk);
|
66 |
|
|
stimulus_done = 0;
|
67 |
|
|
|
68 |
|
|
// STOP CPU
|
69 |
|
|
dbg_i2c_wr(CPU_CTL , 16'h0001);
|
70 |
|
|
|
71 |
|
|
// TEST READ/WR TO ALL DEBUG REGISTERS
|
72 |
|
|
//--------------------------------------------------------
|
73 |
|
|
|
74 |
|
|
cpu_version = `CPU_VERSION;
|
75 |
|
|
`ifdef ASIC
|
76 |
|
|
cpu_asic = 1'b1;
|
77 |
|
|
`else
|
78 |
|
|
cpu_asic = 1'b0;
|
79 |
|
|
`endif
|
80 |
|
|
user_version = `USER_VERSION;
|
81 |
|
|
per_space = (`PER_SIZE >> 9);
|
82 |
|
|
`ifdef MULTIPLIER
|
83 |
|
|
mpy_info = 1'b1;
|
84 |
|
|
`else
|
85 |
|
|
mpy_info = 1'b0;
|
86 |
|
|
`endif
|
87 |
|
|
dmem_size = (`DMEM_SIZE >> 7);
|
88 |
|
|
pmem_size = (`PMEM_SIZE >> 10);
|
89 |
|
|
|
90 |
|
|
dbg_id = {pmem_size,
|
91 |
|
|
dmem_size,
|
92 |
|
|
mpy_info,
|
93 |
|
|
per_space,
|
94 |
|
|
user_version,
|
95 |
|
|
cpu_asic,
|
96 |
|
|
cpu_version};
|
97 |
|
|
|
98 |
|
|
// Check reset value
|
99 |
|
|
for ( ii=0; ii < 64; ii=ii+1)
|
100 |
|
|
begin
|
101 |
|
|
dbg_i2c_rd(ii[7:0]);
|
102 |
|
|
|
103 |
|
|
case(ii)
|
104 |
|
|
|
105 |
|
|
1 : if (dbg_i2c_buf !== dbg_id[31:16]) tb_error("READ 1 ERROR (CPU_ID_HI)");
|
106 |
|
|
2 : if (dbg_i2c_buf !== 16'h0000) tb_error("READ 1 ERROR (CPU_CTL)");
|
107 |
|
|
3 : if (dbg_i2c_buf !== 16'h0005) tb_error("READ 1 ERROR (CPU_STAT)");
|
108 |
|
|
24 : if (dbg_i2c_buf !== 16'h3412) tb_error("READ 1 ERROR (CPU_NR)");
|
109 |
|
|
default : if (dbg_i2c_buf !== 16'h0000) tb_error("READ 1 ERROR");
|
110 |
|
|
endcase
|
111 |
|
|
end
|
112 |
|
|
|
113 |
|
|
// Write access
|
114 |
|
|
for ( ii=0; ii < 64; ii=ii+1)
|
115 |
|
|
begin
|
116 |
|
|
// Skip write for MEM_CNT
|
117 |
|
|
if (ii!=7)
|
118 |
|
|
dbg_i2c_wr(ii[7:0] , 16'hffff);
|
119 |
|
|
end
|
120 |
202 |
olivier.gi |
|
121 |
154 |
olivier.gi |
// Read value back
|
122 |
|
|
for ( ii=0; ii < 64; ii=ii+1)
|
123 |
|
|
begin
|
124 |
|
|
dbg_i2c_rd(ii[7:0]);
|
125 |
|
|
|
126 |
|
|
case(ii)
|
127 |
|
|
|
128 |
|
|
1 : if (dbg_i2c_buf !== dbg_id[31:16]) tb_error("READ 2 ERROR (CPU_ID_HI)");
|
129 |
|
|
2 : if (dbg_i2c_buf !== 16'h0078) tb_error("READ 2 ERROR (CPU_CTL)");
|
130 |
|
|
3 : if ((dbg_i2c_buf !== 16'h0004)&0) tb_error("READ 2 ERROR (CPU_STAT)");
|
131 |
|
|
4 : if (dbg_i2c_buf !== 16'h000E) tb_error("READ 2 ERROR (MEM_CTL)");
|
132 |
|
|
5 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (MEM_ADDR)");
|
133 |
|
|
6 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (MEM_DATA)");
|
134 |
|
|
7 : if (dbg_i2c_buf !== 16'h0000) tb_error("READ 2 ERROR (MEM_CNT)");
|
135 |
|
|
`ifdef DBG_HWBRK_0
|
136 |
|
|
`ifdef DBG_HWBRK_RANGE
|
137 |
|
|
8 : if (dbg_i2c_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK0_CTL)");
|
138 |
|
|
`else
|
139 |
|
|
8 : if (dbg_i2c_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK0_CTL)");
|
140 |
|
|
`endif
|
141 |
175 |
olivier.gi |
9 : if (dbg_i2c_buf !== 16'h0000) tb_error("READ 2 ERROR (BRK0_STAT)");
|
142 |
154 |
olivier.gi |
10 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK0_ADDR0)");
|
143 |
|
|
11 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK0_ADDR1)");
|
144 |
|
|
`endif
|
145 |
|
|
`ifdef DBG_HWBRK_1
|
146 |
|
|
`ifdef DBG_HWBRK_RANGE
|
147 |
|
|
12 : if (dbg_i2c_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK1_CTL)");
|
148 |
|
|
`else
|
149 |
|
|
12 : if (dbg_i2c_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK1_CTL)");
|
150 |
|
|
`endif
|
151 |
175 |
olivier.gi |
13 : if (dbg_i2c_buf !== 16'h0000) tb_error("READ 2 ERROR (BRK1_STAT)");
|
152 |
154 |
olivier.gi |
14 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK1_ADDR0)");
|
153 |
|
|
15 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK1_ADDR1)");
|
154 |
|
|
`endif
|
155 |
|
|
`ifdef DBG_HWBRK_2
|
156 |
|
|
`ifdef DBG_HWBRK_RANGE
|
157 |
|
|
16 : if (dbg_i2c_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK2_CTL)");
|
158 |
|
|
`else
|
159 |
|
|
16 : if (dbg_i2c_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK2_CTL)");
|
160 |
|
|
`endif
|
161 |
175 |
olivier.gi |
17 : if (dbg_i2c_buf !== 16'h0000) tb_error("READ 2 ERROR (BRK2_STAT)");
|
162 |
154 |
olivier.gi |
18 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK2_ADDR0)");
|
163 |
|
|
19 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK2_ADDR1)");
|
164 |
|
|
`endif
|
165 |
|
|
`ifdef DBG_HWBRK_3
|
166 |
|
|
`ifdef DBG_HWBRK_RANGE
|
167 |
|
|
20 : if (dbg_i2c_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK3_CTL)");
|
168 |
|
|
`else
|
169 |
|
|
20 : if (dbg_i2c_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK3_CTL)");
|
170 |
|
|
`endif
|
171 |
175 |
olivier.gi |
21 : if (dbg_i2c_buf !== 16'h0000) tb_error("READ 2 ERROR (BRK3_STAT)");
|
172 |
154 |
olivier.gi |
22 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK3_ADDR0)");
|
173 |
|
|
23 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK3_ADDR1)");
|
174 |
|
|
`endif
|
175 |
|
|
24 : if (dbg_i2c_buf !== 16'h3412) tb_error("READ 2 ERROR (CPU_NR)");
|
176 |
|
|
default : if (dbg_i2c_buf !== 16'h0000) tb_error("READ 2 ERROR");
|
177 |
|
|
endcase
|
178 |
|
|
end
|
179 |
|
|
|
180 |
202 |
olivier.gi |
|
181 |
|
|
dbg_i2c_wr(CPU_CTL , 16'h0002);
|
182 |
154 |
olivier.gi |
repeat(10) @(posedge mclk);
|
183 |
|
|
|
184 |
|
|
stimulus_done = 1;
|
185 |
|
|
`else
|
186 |
|
|
|
187 |
202 |
olivier.gi |
tb_skip_finish("| (serial debug interface I2C not included) |");
|
188 |
154 |
olivier.gi |
`endif
|
189 |
|
|
`else
|
190 |
202 |
olivier.gi |
tb_skip_finish("| (serial debug interface not included) |");
|
191 |
154 |
olivier.gi |
`endif
|
192 |
|
|
end
|