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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_i2c_rdwr.v] - Blame information for rev 219

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1 154 olivier.gi
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                            DEBUG INTERFACE:  RD / WR                      */
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/*---------------------------------------------------------------------------*/
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/* Test the UART debug interface:                                            */
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/*                        - Check RD/WR access to all adressable             */
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/*                          debug registers.                                 */
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/*                                                                           */
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/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 95 $                                                                */
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/* $LastChangedBy: olivier.girard $                                          */
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/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $          */
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/*===========================================================================*/
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`define LONG_TIMEOUT
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reg  [2:0] cpu_version;
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reg        cpu_asic;
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reg  [4:0] user_version;
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reg  [6:0] per_space;
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reg        mpy_info;
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reg  [8:0] dmem_size;
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reg  [5:0] pmem_size;
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reg [31:0] dbg_id;
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// Set oMSP parameters for later check
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defparam dut.INST_NR  = 8'h12;
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defparam dut.TOTAL_NR = 8'h34;
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integer    ii;
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initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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`ifdef DBG_EN
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`ifdef DBG_I2C
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    #1 dbg_en = 1;
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      repeat(30) @(posedge mclk);
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      stimulus_done = 0;
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      // STOP CPU
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      dbg_i2c_wr(CPU_CTL ,  16'h0001);
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      // TEST READ/WR TO ALL DEBUG REGISTERS
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      //--------------------------------------------------------
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      cpu_version  =  `CPU_VERSION;
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`ifdef ASIC
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      cpu_asic     =  1'b1;
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`else
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      cpu_asic     =  1'b0;
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`endif
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      user_version =  `USER_VERSION;
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      per_space    = (`PER_SIZE  >> 9);
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`ifdef MULTIPLIER
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      mpy_info     =  1'b1;
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`else
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      mpy_info     =  1'b0;
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`endif
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      dmem_size    = (`DMEM_SIZE >> 7);
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      pmem_size    = (`PMEM_SIZE >> 10);
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      dbg_id       = {pmem_size,
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                      dmem_size,
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                      mpy_info,
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                      per_space,
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                      user_version,
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                      cpu_asic,
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                      cpu_version};
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      // Check reset value
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      for ( ii=0; ii < 64; ii=ii+1)
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        begin
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           dbg_i2c_rd(ii[7:0]);
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           case(ii)
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             1       : if (dbg_i2c_buf !== dbg_id[31:16]) tb_error("READ 1 ERROR (CPU_ID_HI)");
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             2       : if (dbg_i2c_buf !== 16'h0000)      tb_error("READ 1 ERROR (CPU_CTL)");
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             3       : if (dbg_i2c_buf !== 16'h0005)      tb_error("READ 1 ERROR (CPU_STAT)");
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            24       : if (dbg_i2c_buf !== 16'h3412)      tb_error("READ 1 ERROR (CPU_NR)");
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             default : if (dbg_i2c_buf !== 16'h0000)      tb_error("READ 1 ERROR");
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           endcase
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        end
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      // Write access
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      for ( ii=0; ii < 64; ii=ii+1)
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        begin
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           // Skip write for MEM_CNT
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           if (ii!=7)
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             dbg_i2c_wr(ii[7:0] ,  16'hffff);
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        end
120 202 olivier.gi
 
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      // Read value back
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      for ( ii=0; ii < 64; ii=ii+1)
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        begin
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           dbg_i2c_rd(ii[7:0]);
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           case(ii)
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             1       : if (dbg_i2c_buf !== dbg_id[31:16]) tb_error("READ 2 ERROR (CPU_ID_HI)");
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             2       : if (dbg_i2c_buf !== 16'h0078)      tb_error("READ 2 ERROR (CPU_CTL)");
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             3       : if ((dbg_i2c_buf !== 16'h0004)&0)  tb_error("READ 2 ERROR (CPU_STAT)");
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             4       : if (dbg_i2c_buf !== 16'h000E)      tb_error("READ 2 ERROR (MEM_CTL)");
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             5       : if (dbg_i2c_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (MEM_ADDR)");
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             6       : if (dbg_i2c_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (MEM_DATA)");
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             7       : if (dbg_i2c_buf !== 16'h0000)      tb_error("READ 2 ERROR (MEM_CNT)");
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`ifdef DBG_HWBRK_0
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   `ifdef DBG_HWBRK_RANGE
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             8       : if (dbg_i2c_buf !== 16'h001F)      tb_error("READ 2 ERROR (BRK0_CTL)");
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   `else
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             8       : if (dbg_i2c_buf !== 16'h000F)      tb_error("READ 2 ERROR (BRK0_CTL)");
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   `endif
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             9       : if (dbg_i2c_buf !== 16'h0000)      tb_error("READ 2 ERROR (BRK0_STAT)");
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            10       : if (dbg_i2c_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (BRK0_ADDR0)");
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            11       : if (dbg_i2c_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (BRK0_ADDR1)");
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`endif
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`ifdef DBG_HWBRK_1
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   `ifdef DBG_HWBRK_RANGE
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            12       : if (dbg_i2c_buf !== 16'h001F)      tb_error("READ 2 ERROR (BRK1_CTL)");
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   `else
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            12       : if (dbg_i2c_buf !== 16'h000F)      tb_error("READ 2 ERROR (BRK1_CTL)");
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   `endif
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            13       : if (dbg_i2c_buf !== 16'h0000)      tb_error("READ 2 ERROR (BRK1_STAT)");
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            14       : if (dbg_i2c_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (BRK1_ADDR0)");
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            15       : if (dbg_i2c_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (BRK1_ADDR1)");
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`endif
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`ifdef DBG_HWBRK_2
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   `ifdef DBG_HWBRK_RANGE
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            16       : if (dbg_i2c_buf !== 16'h001F)      tb_error("READ 2 ERROR (BRK2_CTL)");
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   `else
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            16       : if (dbg_i2c_buf !== 16'h000F)      tb_error("READ 2 ERROR (BRK2_CTL)");
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   `endif
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            17       : if (dbg_i2c_buf !== 16'h0000)      tb_error("READ 2 ERROR (BRK2_STAT)");
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            18       : if (dbg_i2c_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (BRK2_ADDR0)");
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            19       : if (dbg_i2c_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (BRK2_ADDR1)");
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`endif
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`ifdef DBG_HWBRK_3
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   `ifdef DBG_HWBRK_RANGE
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            20       : if (dbg_i2c_buf !== 16'h001F)      tb_error("READ 2 ERROR (BRK3_CTL)");
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   `else
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            20       : if (dbg_i2c_buf !== 16'h000F)      tb_error("READ 2 ERROR (BRK3_CTL)");
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   `endif
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            21       : if (dbg_i2c_buf !== 16'h0000)      tb_error("READ 2 ERROR (BRK3_STAT)");
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            22       : if (dbg_i2c_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (BRK3_ADDR0)");
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            23       : if (dbg_i2c_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (BRK3_ADDR1)");
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`endif
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            24       : if (dbg_i2c_buf !== 16'h3412)      tb_error("READ 2 ERROR (CPU_NR)");
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             default : if (dbg_i2c_buf !== 16'h0000)      tb_error("READ 2 ERROR");
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           endcase
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        end
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      dbg_i2c_wr(CPU_CTL    ,  16'h0002);
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      repeat(10) @(posedge mclk);
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      stimulus_done = 1;
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`else
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       tb_skip_finish("|   (serial debug interface I2C not included)  |");
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`endif
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`else
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       tb_skip_finish("|      (serial debug interface not included)   |");
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`endif
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   end

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