OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart.v] - Blame information for rev 175

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                            DEBUG INTERFACE:  UART                         */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the UART debug interface:                                            */
27 
/*                        - Check RD/WR access to debugg registers.          */
28 
/*                        - Check RD Bursts.                                 */
29 
/*                        - Check WR Bursts.                                 */
30 18 olivier.gi 
/*                                                                           */
31 
/* Author(s):                                                                */
32 
/*             - Olivier Girard,    olgirard@gmail.com                       */
33 
/*                                                                           */
34 
/*---------------------------------------------------------------------------*/
35 19 olivier.gi 
/* $Rev: 134 $                                                                */
36 
/* $LastChangedBy: olivier.girard $                                          */
37 
/* $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $          */
38 2 olivier.gi 
/*===========================================================================*/
39 
 
40 
`define LONG_TIMEOUT
41 
 
42 111 olivier.gi 
reg  [2:0] cpu_version;
43 
reg        cpu_asic;
44 
reg  [4:0] user_version;
45 
reg  [6:0] per_space;
46 
reg        mpy_info;
47 
reg  [8:0] dmem_size;
48 
reg  [5:0] pmem_size;
49 2 olivier.gi 
reg [31:0] dbg_id;
50 
 
51 
initial
52 
   begin
53 
      $display(" ===============================================");
54 
      $display("|                 START SIMULATION              |");
55 
      $display(" ===============================================");
56 111 olivier.gi 
`ifdef DBG_EN
57 
`ifdef DBG_UART
58 
    #1 dbg_en = 1;
59 2 olivier.gi 
      repeat(30) @(posedge mclk);
60 
      stimulus_done = 0;
61 
 
62 
      // SEND UART SYNCHRONIZATION FRAME
63 
      dbg_uart_tx(DBG_SYNC);
64 
 
65 106 olivier.gi 
   `ifdef DBG_RST_BRK_EN
66 
      dbg_uart_wr(CPU_CTL,  16'h0002);  // RUN
67 
   `endif
68 
 
69 2 olivier.gi 
      // TEST CPU REGISTERS
70 
      //--------------------------------------------------------
71 
 
72 111 olivier.gi 
      cpu_version  =  `CPU_VERSION;
73 
`ifdef ASIC
74 
      cpu_asic     =  1'b1;
75 
`else
76 
      cpu_asic     =  1'b0;
77 
`endif
78 
      user_version =  `USER_VERSION;
79 
      per_space    = (`PER_SIZE  >> 9);
80 
`ifdef MULTIPLIER
81 
      mpy_info     =  1'b1;
82 
`else
83 
      mpy_info     =  1'b0;
84 
`endif
85 
      dmem_size    = (`DMEM_SIZE >> 7);
86 
      pmem_size    = (`PMEM_SIZE >> 10);
87 
 
88 
      dbg_id       = {pmem_size,
89 
                      dmem_size,
90 
                      mpy_info,
91 
                      per_space,
92 
                      user_version,
93 
                      cpu_asic,
94 
                      cpu_version};
95 
 
96 2 olivier.gi 
      dbg_uart_wr(CPU_ID_LO  ,  16'hffff);
97 
      dbg_uart_rd(CPU_ID_LO);
98 
      if (dbg_uart_buf !== dbg_id[15:0])  tb_error("====== CPU_ID_LO uncorrect =====");
99 
      dbg_uart_wr(CPU_ID_LO  ,  16'h0000);
100 
      dbg_uart_rd(CPU_ID_LO);
101 
      if (dbg_uart_buf !== dbg_id[15:0])  tb_error("====== CPU_ID_LO uncorrect =====");
102 
 
103 
      dbg_uart_wr(CPU_ID_HI  ,  16'hffff);
104 
      dbg_uart_rd(CPU_ID_HI);
105 
      if (dbg_uart_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect =====");
106 
      dbg_uart_wr(CPU_ID_HI  ,  16'h0000);
107 
      dbg_uart_rd(CPU_ID_HI);
108 
      if (dbg_uart_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect =====");
109 
 
110 
      dbg_uart_wr(CPU_STAT   ,  16'hffff);
111 
      dbg_uart_rd(CPU_STAT);
112 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== CPU_STAT uncorrect =====");
113 
      dbg_uart_wr(CPU_STAT   ,  16'h0000);
114 
      dbg_uart_rd(CPU_STAT);
115 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== CPU_STAT uncorrect =====");
116 
 
117 
      dbg_uart_wr(CPU_CTL    ,  16'hffff);
118 
      dbg_uart_rd(CPU_CTL);
119 
      if (dbg_uart_buf !== 16'h0078)      tb_error("====== CPU_CTL uncorrect =====");
120 
      dbg_uart_wr(CPU_CTL    ,  16'h0000);
121 
      dbg_uart_rd(CPU_CTL);
122 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== CPU_CTL uncorrect =====");
123 
 
124 
 
125 
      // TEST MEMORY CONTROL REGISTERS
126 
      //--------------------------------------------------------
127 
 
128 
      dbg_uart_wr(MEM_CTL    ,  16'hfffe);
129 
      dbg_uart_rd(MEM_CTL);
130 
      if (dbg_uart_buf !== 16'h000E)      tb_error("====== MEM_CTL uncorrect =====");
131 
      dbg_uart_wr(MEM_CTL    ,  16'h0000);
132 
      dbg_uart_rd(MEM_CTL);
133 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_CTL uncorrect =====");
134 
 
135 
      dbg_uart_wr(MEM_ADDR   ,  16'hffff);
136 
      dbg_uart_rd(MEM_ADDR);
137 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== MEM_ADDR uncorrect =====");
138 
      dbg_uart_wr(MEM_ADDR   ,  16'h0000);
139 
      dbg_uart_rd(MEM_ADDR);
140 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_ADDR uncorrect =====");
141 
 
142 
      dbg_uart_wr(MEM_DATA   ,  16'hffff);
143 
      dbg_uart_rd(MEM_DATA);
144 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== MEM_DATA uncorrect =====");
145 
      dbg_uart_wr(MEM_DATA   ,  16'h0000);
146 
      dbg_uart_rd(MEM_DATA);
147 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_DATA uncorrect =====");
148 
 
149 
      dbg_uart_wr(MEM_CNT    ,  16'hffff);
150 
      dbg_uart_rd(MEM_CNT);
151 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== MEM_CNT uncorrect =====");
152 
      dbg_uart_wr(MEM_CNT    ,  16'h0000);
153 
      dbg_uart_rd(MEM_CNT);
154 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_CNT uncorrect =====");
155 
 
156 
 
157 
      // TEST HARDWARE BREAKPOINT 0 REGISTERS
158 
      //--------------------------------------------------------
159 111 olivier.gi 
`ifdef DBG_HWBRK_0
160 2 olivier.gi 
      dbg_uart_wr(BRK0_CTL   ,  16'hffff);
161 
      dbg_uart_rd(BRK0_CTL);
162 58 olivier.gi 
      if (`HWBRK_RANGE)
163 
        begin
164 
           if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK0_CTL uncorrect =====");
165 
        end
166 
      else
167 
        begin
168 
           if (dbg_uart_buf !== 16'h000F)      tb_error("====== BRK0_CTL uncorrect =====");
169 
        end
170 2 olivier.gi 
      dbg_uart_wr(BRK0_CTL   ,  16'h0000);
171 
      dbg_uart_rd(BRK0_CTL);
172 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_CTL uncorrect =====");
173 
 
174 
      dbg_uart_wr(BRK0_STAT  ,  16'hffff);
175 
      dbg_uart_rd(BRK0_STAT);
176 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_STAT uncorrect =====");
177 
      dbg_uart_wr(BRK0_STAT  ,  16'h0000);
178 
      dbg_uart_rd(BRK0_STAT);
179 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_STAT uncorrect =====");
180 
 
181 
      dbg_uart_wr(BRK0_ADDR0 ,  16'hffff);
182 
      dbg_uart_rd(BRK0_ADDR0);
183 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK0_ADDR0 uncorrect =====");
184 
      dbg_uart_wr(BRK0_ADDR0 ,  16'h0000);
185 
      dbg_uart_rd(BRK0_ADDR0);
186 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_ADDR0 uncorrect =====");
187 
 
188 
      dbg_uart_wr(BRK0_ADDR1 ,  16'hffff);
189 
      dbg_uart_rd(BRK0_ADDR1);
190 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK0_ADDR1 uncorrect =====");
191 
      dbg_uart_wr(BRK0_ADDR1 ,  16'h0000);
192 
      dbg_uart_rd(BRK0_ADDR1);
193 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_ADDR1 uncorrect =====");
194 111 olivier.gi 
`endif
195 2 olivier.gi 
 
196 
      // TEST HARDWARE BREAKPOINT 1 REGISTERS
197 
      //--------------------------------------------------------
198 111 olivier.gi 
`ifdef DBG_HWBRK_1
199 2 olivier.gi 
      dbg_uart_wr(BRK1_CTL   ,  16'hffff);
200 
      dbg_uart_rd(BRK1_CTL);
201 58 olivier.gi 
      if (`HWBRK_RANGE)
202 
        begin
203 
           if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK1_CTL uncorrect =====");
204 
        end
205 
      else
206 
        begin
207 
           if (dbg_uart_buf !== 16'h000F)      tb_error("====== BRK1_CTL uncorrect =====");
208 
        end
209 2 olivier.gi 
      dbg_uart_wr(BRK1_CTL   ,  16'h0000);
210 
      dbg_uart_rd(BRK1_CTL);
211 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_CTL uncorrect =====");
212 
 
213 
      dbg_uart_wr(BRK1_STAT  ,  16'hffff);
214 
      dbg_uart_rd(BRK1_STAT);
215 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_STAT uncorrect =====");
216 
      dbg_uart_wr(BRK1_STAT  ,  16'h0000);
217 
      dbg_uart_rd(BRK1_STAT);
218 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_STAT uncorrect =====");
219 
 
220 
      dbg_uart_wr(BRK1_ADDR0 ,  16'hffff);
221 
      dbg_uart_rd(BRK1_ADDR0);
222 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK1_ADDR0 uncorrect =====");
223 
      dbg_uart_wr(BRK1_ADDR0 ,  16'h0000);
224 
      dbg_uart_rd(BRK1_ADDR0);
225 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_ADDR0 uncorrect =====");
226 
 
227 
      dbg_uart_wr(BRK1_ADDR1 ,  16'hffff);
228 
      dbg_uart_rd(BRK1_ADDR1);
229 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK1_ADDR1 uncorrect =====");
230 
      dbg_uart_wr(BRK1_ADDR1 ,  16'h0000);
231 
      dbg_uart_rd(BRK1_ADDR1);
232 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_ADDR1 uncorrect =====");
233 111 olivier.gi 
`endif
234 2 olivier.gi 
 
235 
      // TEST HARDWARE BREAKPOINT 2 REGISTERS
236 
      //--------------------------------------------------------
237 111 olivier.gi 
`ifdef DBG_HWBRK_2
238 2 olivier.gi 
      dbg_uart_wr(BRK2_CTL   ,  16'hffff);
239 
      dbg_uart_rd(BRK2_CTL);
240 58 olivier.gi 
      if (`HWBRK_RANGE)
241 
        begin
242 
           if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK2_CTL uncorrect =====");
243 
        end
244 
      else
245 
        begin
246 
           if (dbg_uart_buf !== 16'h000F)      tb_error("====== BRK2_CTL uncorrect =====");
247 
        end
248 2 olivier.gi 
      dbg_uart_wr(BRK2_CTL   ,  16'h0000);
249 
      dbg_uart_rd(BRK2_CTL);
250 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_CTL uncorrect =====");
251 
 
252 
      dbg_uart_wr(BRK2_STAT  ,  16'hffff);
253 
      dbg_uart_rd(BRK2_STAT);
254 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_STAT uncorrect =====");
255 
      dbg_uart_wr(BRK2_STAT  ,  16'h0000);
256 
      dbg_uart_rd(BRK2_STAT);
257 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_STAT uncorrect =====");
258 
 
259 
      dbg_uart_wr(BRK2_ADDR0 ,  16'hffff);
260 
      dbg_uart_rd(BRK2_ADDR0);
261 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK2_ADDR0 uncorrect =====");
262 
      dbg_uart_wr(BRK2_ADDR0 ,  16'h0000);
263 
      dbg_uart_rd(BRK2_ADDR0);
264 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_ADDR0 uncorrect =====");
265 
 
266 
      dbg_uart_wr(BRK2_ADDR1 ,  16'hffff);
267 
      dbg_uart_rd(BRK2_ADDR1);
268 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK2_ADDR1 uncorrect =====");
269 
      dbg_uart_wr(BRK2_ADDR1 ,  16'h0000);
270 
      dbg_uart_rd(BRK2_ADDR1);
271 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_ADDR1 uncorrect =====");
272 111 olivier.gi 
`endif
273 2 olivier.gi 
 
274 
      // TEST HARDWARE BREAKPOINT 3 REGISTERS
275 
      //--------------------------------------------------------
276 111 olivier.gi 
`ifdef DBG_HWBRK_3
277 2 olivier.gi 
      dbg_uart_wr(BRK3_CTL   ,  16'hffff);
278 
      dbg_uart_rd(BRK3_CTL);
279 58 olivier.gi 
      if (`HWBRK_RANGE)
280 
        begin
281 
           if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK3_CTL uncorrect =====");
282 
        end
283 
      else
284 
        begin
285 
           if (dbg_uart_buf !== 16'h000F)      tb_error("====== BRK3_CTL uncorrect =====");
286 
        end
287 2 olivier.gi 
      dbg_uart_wr(BRK3_CTL   ,  16'h0000);
288 
      dbg_uart_rd(BRK3_CTL);
289 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_CTL uncorrect =====");
290 
 
291 
      dbg_uart_wr(BRK3_STAT  ,  16'hffff);
292 
      dbg_uart_rd(BRK3_STAT);
293 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_STAT uncorrect =====");
294 
      dbg_uart_wr(BRK3_STAT  ,  16'h0000);
295 
      dbg_uart_rd(BRK3_STAT);
296 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_STAT uncorrect =====");
297 
 
298 
      dbg_uart_wr(BRK3_ADDR0 ,  16'hffff);
299 
      dbg_uart_rd(BRK3_ADDR0);
300 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK3_ADDR0 uncorrect =====");
301 
      dbg_uart_wr(BRK3_ADDR0 ,  16'h0000);
302 
      dbg_uart_rd(BRK3_ADDR0);
303 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_ADDR0 uncorrect =====");
304 
 
305 
      dbg_uart_wr(BRK3_ADDR1 ,  16'hffff);
306 
      dbg_uart_rd(BRK3_ADDR1);
307 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK3_ADDR1 uncorrect =====");
308 
      dbg_uart_wr(BRK3_ADDR1 ,  16'h0000);
309 
      dbg_uart_rd(BRK3_ADDR1);
310 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_ADDR1 uncorrect =====");
311 111 olivier.gi 
`endif
312 2 olivier.gi 
 
313 
      // TEST 16B WRITE BURSTS (MEMORY)
314 
      //--------------------------------------------------------
315 
 
316 111 olivier.gi 
      dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
317 
      dbg_uart_wr(MEM_CNT,  16'h0004);             // 5 consecutive access
318 2 olivier.gi 
 
319 
      dbg_uart_wr(MEM_CTL,  16'h0003); // Start burst to 16 bit memory write
320 
      dbg_uart_tx16(16'h1234);         // write 1st data
321 95 olivier.gi 
      repeat(12) @(posedge mclk);
322 2 olivier.gi 
      if (mem200 !== 16'h1234)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
323 
      dbg_uart_tx16(16'h5678);         // write 2nd data
324 95 olivier.gi 
      repeat(12) @(posedge mclk);
325 2 olivier.gi 
      if (mem202 !== 16'h5678)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
326 
      dbg_uart_tx16(16'h9abc);         // write 3rd data
327 95 olivier.gi 
      repeat(12) @(posedge mclk);
328 2 olivier.gi 
      if (mem204 !== 16'h9abc)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
329 
      dbg_uart_tx16(16'hdef0);         // write 4th data
330 95 olivier.gi 
      repeat(12) @(posedge mclk);
331 2 olivier.gi 
      if (mem206 !== 16'hdef0)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
332 
      dbg_uart_tx16(16'h0fed);         // write 5th data
333 95 olivier.gi 
      repeat(12) @(posedge mclk);
334 2 olivier.gi 
      if (mem208 !== 16'h0fed)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
335 
 
336 111 olivier.gi 
      dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
337 
      dbg_uart_wr(MEM_CNT,  16'h0004);             // 5 consecutive access
338 2 olivier.gi 
 
339 
      dbg_uart_wr(MEM_CTL,  16'h0001); // Start burst to 16 bit registers read
340 134 olivier.gi 
      dbg_uart_rx16;                   // read 1st data
341 2 olivier.gi 
      if (dbg_uart_buf !== 16'h1234)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
342 134 olivier.gi 
      dbg_uart_rx16;                   // read 2nd data
343 2 olivier.gi 
      if (dbg_uart_buf !== 16'h5678)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
344 134 olivier.gi 
      dbg_uart_rx16;                   // read 3rd data
345 2 olivier.gi 
      if (dbg_uart_buf !== 16'h9abc)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
346 134 olivier.gi 
      dbg_uart_rx16;                   // read 4th data
347 2 olivier.gi 
      if (dbg_uart_buf !== 16'hdef0)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
348 134 olivier.gi 
      dbg_uart_rx16;                   // read 5th data
349 2 olivier.gi 
      if (dbg_uart_buf !== 16'h0fed)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
350 
 
351 
 
352 
      // TEST 16B WRITE BURSTS (CPU REGISTERS)
353 
      //--------------------------------------------------------
354 
 
355 
      dbg_uart_wr(MEM_ADDR, 16'h0005); // select R5
356 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
357 
 
358 
      dbg_uart_wr(MEM_CTL,  16'h0007); // Start burst to 16 bit cpu register write
359 
      dbg_uart_tx16(16'hcba9);         // write 1st data
360 95 olivier.gi 
      repeat(12) @(posedge mclk);
361 2 olivier.gi 
      if (r5 !== 16'hcba9)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 1st DATA =====");
362 
      dbg_uart_tx16(16'h8765);         // write 2nd data
363 95 olivier.gi 
      repeat(12) @(posedge mclk);
364 2 olivier.gi 
      if (r6 !== 16'h8765)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 2nd DATA =====");
365 
      dbg_uart_tx16(16'h4321);         // write 3rd data
366 95 olivier.gi 
      repeat(12) @(posedge mclk);
367 2 olivier.gi 
      if (r7 !== 16'h4321)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 3rd DATA =====");
368 
      dbg_uart_tx16(16'h0123);         // write 4th data
369 95 olivier.gi 
      repeat(12) @(posedge mclk);
370 2 olivier.gi 
      if (r8 !== 16'h0123)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 4th DATA =====");
371 
      dbg_uart_tx16(16'h4567);         // write 5th data
372 95 olivier.gi 
      repeat(12) @(posedge mclk);
373 2 olivier.gi 
      if (r9 !== 16'h4567)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 5th DATA =====");
374 
 
375 
      dbg_uart_wr(MEM_ADDR, 16'h0005); // select @0x0200
376 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
377 
 
378 
      dbg_uart_wr(MEM_CTL,  16'h0005); // Start burst to 16 bit cpu registers read
379 134 olivier.gi 
      dbg_uart_rx16;                   // read 1st data
380 2 olivier.gi 
      if (dbg_uart_buf !== 16'hcba9)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 1st DATA =====");
381 134 olivier.gi 
      dbg_uart_rx16;                   // read 2nd data
382 2 olivier.gi 
      if (dbg_uart_buf !== 16'h8765)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 2nd DATA =====");
383 134 olivier.gi 
      dbg_uart_rx16;                   // read 3rd data
384 2 olivier.gi 
      if (dbg_uart_buf !== 16'h4321)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 3rd DATA =====");
385 134 olivier.gi 
      dbg_uart_rx16;                   // read 4th data
386 2 olivier.gi 
      if (dbg_uart_buf !== 16'h0123)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 4th DATA =====");
387 134 olivier.gi 
      dbg_uart_rx16;                   // read 5th data
388 2 olivier.gi 
      if (dbg_uart_buf !== 16'h4567)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 5th DATA =====");
389 
 
390 
 
391 
      // TEST 8B WRITE BURSTS (MEMORY)
392 
      //--------------------------------------------------------
393 
 
394 111 olivier.gi 
      dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0210
395 2 olivier.gi 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
396 
 
397 
      dbg_uart_wr(MEM_CTL,  16'h000b); // Start burst to 8 bit memory write
398 
      dbg_uart_tx(8'h91);         // write 1st data
399 95 olivier.gi 
      repeat(12) @(posedge mclk);
400 2 olivier.gi 
      if (mem200 !== 16'h1291)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
401 
      dbg_uart_tx(8'h82);         // write 2nd data
402 95 olivier.gi 
      repeat(12) @(posedge mclk);
403 2 olivier.gi 
      if (mem200 !== 16'h8291)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
404 
      dbg_uart_tx(8'h73);         // write 3rd data
405 95 olivier.gi 
      repeat(12) @(posedge mclk);
406 2 olivier.gi 
      if (mem202 !== 16'h5673)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
407 
      dbg_uart_tx(8'h64);         // write 4th data
408 95 olivier.gi 
      repeat(12) @(posedge mclk);
409 2 olivier.gi 
      if (mem202 !== 16'h6473)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
410 
      dbg_uart_tx(8'h55);         // write 5th data
411 95 olivier.gi 
      repeat(12) @(posedge mclk);
412 2 olivier.gi 
      if (mem204 !== 16'h9a55)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
413 
 
414 111 olivier.gi 
      dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
415 2 olivier.gi 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
416 
 
417 
      dbg_uart_wr(MEM_CTL,  16'h0009); // Start burst to 8 bit registers read
418 134 olivier.gi 
      dbg_uart_rx8;                   // read 1st data
419 2 olivier.gi 
      if (dbg_uart_buf !== 16'h0091)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
420 134 olivier.gi 
      dbg_uart_rx8;                   // read 2nd data
421 2 olivier.gi 
      if (dbg_uart_buf !== 16'h0082)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
422 134 olivier.gi 
      dbg_uart_rx8;                   // read 3rd data
423 2 olivier.gi 
      if (dbg_uart_buf !== 16'h0073)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
424 134 olivier.gi 
      dbg_uart_rx8;                   // read 4th data
425 2 olivier.gi 
      if (dbg_uart_buf !== 16'h0064)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
426 134 olivier.gi 
      dbg_uart_rx8;                   // read 5th data
427 2 olivier.gi 
      if (dbg_uart_buf !== 16'h0055)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
428 
 
429 
 
430 
 
431 
 
432 
 
433 
      dbg_uart_wr(CPU_CTL    ,  16'h0002);
434 
      repeat(10) @(posedge mclk);
435 
 
436 
      stimulus_done = 1;
437 111 olivier.gi 
`else
438 
 
439 
       $display(" ===============================================");
440 
       $display("|               SIMULATION SKIPPED              |");
441 
       $display("|   (serial debug interface UART not included)  |");
442 
       $display(" ===============================================");
443 
       $finish;
444 
`endif
445 
`else
446 
 
447 
       $display(" ===============================================");
448 
       $display("|               SIMULATION SKIPPED              |");
449 
       $display("|      (serial debug interface not included)    |");
450 
       $display(" ===============================================");
451 
       $finish;
452 
`endif
453 2 olivier.gi 
   end
454 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.