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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart.v] - Blame information for rev 33

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1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                            DEBUG INTERFACE:  UART                         */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the UART debug interface:                                            */
27 
/*                        - Check RD/WR access to debugg registers.          */
28 
/*                        - Check RD Bursts.                                 */
29 
/*                        - Check WR Bursts.                                 */
30 18 olivier.gi 
/*                                                                           */
31 
/* Author(s):                                                                */
32 
/*             - Olivier Girard,    olgirard@gmail.com                       */
33 
/*                                                                           */
34 
/*---------------------------------------------------------------------------*/
35 19 olivier.gi 
/* $Rev: 33 $                                                                */
36 
/* $LastChangedBy: olivier.girard $                                          */
37 
/* $LastChangedDate: 2009-12-29 19:18:00 +0100 (Tue, 29 Dec 2009) $          */
38 2 olivier.gi 
/*===========================================================================*/
39 
 
40 
`define LONG_TIMEOUT
41 
 
42 33 olivier.gi 
reg  [3:0] dbg_id_pmem;
43 
reg  [3:0] dbg_id_dmem;
44 2 olivier.gi 
reg [31:0] dbg_id;
45 
 
46 
initial
47 
   begin
48 
      $display(" ===============================================");
49 
      $display("|                 START SIMULATION              |");
50 
      $display(" ===============================================");
51 
      repeat(30) @(posedge mclk);
52 
      stimulus_done = 0;
53 
 
54 
      // SEND UART SYNCHRONIZATION FRAME
55 
      dbg_uart_tx(DBG_SYNC);
56 
 
57 
      // TEST CPU REGISTERS
58 
      //--------------------------------------------------------
59 33 olivier.gi 
      dbg_id_pmem = `PMEM_AWIDTH;
60 
      dbg_id_dmem = `DMEM_AWIDTH;
61 
      dbg_id      = {`DBG_ID, dbg_id_pmem, dbg_id_dmem};
62 2 olivier.gi 
 
63 
      dbg_uart_wr(CPU_ID_LO  ,  16'hffff);
64 
      dbg_uart_rd(CPU_ID_LO);
65 
      if (dbg_uart_buf !== dbg_id[15:0])  tb_error("====== CPU_ID_LO uncorrect =====");
66 
      dbg_uart_wr(CPU_ID_LO  ,  16'h0000);
67 
      dbg_uart_rd(CPU_ID_LO);
68 
      if (dbg_uart_buf !== dbg_id[15:0])  tb_error("====== CPU_ID_LO uncorrect =====");
69 
 
70 
      dbg_uart_wr(CPU_ID_HI  ,  16'hffff);
71 
      dbg_uart_rd(CPU_ID_HI);
72 
      if (dbg_uart_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect =====");
73 
      dbg_uart_wr(CPU_ID_HI  ,  16'h0000);
74 
      dbg_uart_rd(CPU_ID_HI);
75 
      if (dbg_uart_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect =====");
76 
 
77 
      dbg_uart_wr(CPU_STAT   ,  16'hffff);
78 
      dbg_uart_rd(CPU_STAT);
79 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== CPU_STAT uncorrect =====");
80 
      dbg_uart_wr(CPU_STAT   ,  16'h0000);
81 
      dbg_uart_rd(CPU_STAT);
82 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== CPU_STAT uncorrect =====");
83 
 
84 
      dbg_uart_wr(CPU_CTL    ,  16'hffff);
85 
      dbg_uart_rd(CPU_CTL);
86 
      if (dbg_uart_buf !== 16'h0078)      tb_error("====== CPU_CTL uncorrect =====");
87 
      dbg_uart_wr(CPU_CTL    ,  16'h0000);
88 
      dbg_uart_rd(CPU_CTL);
89 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== CPU_CTL uncorrect =====");
90 
 
91 
 
92 
      // TEST MEMORY CONTROL REGISTERS
93 
      //--------------------------------------------------------
94 
 
95 
      dbg_uart_wr(MEM_CTL    ,  16'hfffe);
96 
      dbg_uart_rd(MEM_CTL);
97 
      if (dbg_uart_buf !== 16'h000E)      tb_error("====== MEM_CTL uncorrect =====");
98 
      dbg_uart_wr(MEM_CTL    ,  16'h0000);
99 
      dbg_uart_rd(MEM_CTL);
100 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_CTL uncorrect =====");
101 
 
102 
      dbg_uart_wr(MEM_ADDR   ,  16'hffff);
103 
      dbg_uart_rd(MEM_ADDR);
104 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== MEM_ADDR uncorrect =====");
105 
      dbg_uart_wr(MEM_ADDR   ,  16'h0000);
106 
      dbg_uart_rd(MEM_ADDR);
107 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_ADDR uncorrect =====");
108 
 
109 
      dbg_uart_wr(MEM_DATA   ,  16'hffff);
110 
      dbg_uart_rd(MEM_DATA);
111 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== MEM_DATA uncorrect =====");
112 
      dbg_uart_wr(MEM_DATA   ,  16'h0000);
113 
      dbg_uart_rd(MEM_DATA);
114 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_DATA uncorrect =====");
115 
 
116 
      dbg_uart_wr(MEM_CNT    ,  16'hffff);
117 
      dbg_uart_rd(MEM_CNT);
118 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== MEM_CNT uncorrect =====");
119 
      dbg_uart_wr(MEM_CNT    ,  16'h0000);
120 
      dbg_uart_rd(MEM_CNT);
121 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_CNT uncorrect =====");
122 
 
123 
 
124 
      // TEST HARDWARE BREAKPOINT 0 REGISTERS
125 
      //--------------------------------------------------------
126 
 
127 
      dbg_uart_wr(BRK0_CTL   ,  16'hffff);
128 
      dbg_uart_rd(BRK0_CTL);
129 
      if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK0_CTL uncorrect =====");
130 
      dbg_uart_wr(BRK0_CTL   ,  16'h0000);
131 
      dbg_uart_rd(BRK0_CTL);
132 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_CTL uncorrect =====");
133 
 
134 
      dbg_uart_wr(BRK0_STAT  ,  16'hffff);
135 
      dbg_uart_rd(BRK0_STAT);
136 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_STAT uncorrect =====");
137 
      dbg_uart_wr(BRK0_STAT  ,  16'h0000);
138 
      dbg_uart_rd(BRK0_STAT);
139 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_STAT uncorrect =====");
140 
 
141 
      dbg_uart_wr(BRK0_ADDR0 ,  16'hffff);
142 
      dbg_uart_rd(BRK0_ADDR0);
143 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK0_ADDR0 uncorrect =====");
144 
      dbg_uart_wr(BRK0_ADDR0 ,  16'h0000);
145 
      dbg_uart_rd(BRK0_ADDR0);
146 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_ADDR0 uncorrect =====");
147 
 
148 
      dbg_uart_wr(BRK0_ADDR1 ,  16'hffff);
149 
      dbg_uart_rd(BRK0_ADDR1);
150 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK0_ADDR1 uncorrect =====");
151 
      dbg_uart_wr(BRK0_ADDR1 ,  16'h0000);
152 
      dbg_uart_rd(BRK0_ADDR1);
153 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_ADDR1 uncorrect =====");
154 
 
155 
 
156 
      // TEST HARDWARE BREAKPOINT 1 REGISTERS
157 
      //--------------------------------------------------------
158 
 
159 
      dbg_uart_wr(BRK1_CTL   ,  16'hffff);
160 
      dbg_uart_rd(BRK1_CTL);
161 
      if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK1_CTL uncorrect =====");
162 
      dbg_uart_wr(BRK1_CTL   ,  16'h0000);
163 
      dbg_uart_rd(BRK1_CTL);
164 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_CTL uncorrect =====");
165 
 
166 
      dbg_uart_wr(BRK1_STAT  ,  16'hffff);
167 
      dbg_uart_rd(BRK1_STAT);
168 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_STAT uncorrect =====");
169 
      dbg_uart_wr(BRK1_STAT  ,  16'h0000);
170 
      dbg_uart_rd(BRK1_STAT);
171 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_STAT uncorrect =====");
172 
 
173 
      dbg_uart_wr(BRK1_ADDR0 ,  16'hffff);
174 
      dbg_uart_rd(BRK1_ADDR0);
175 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK1_ADDR0 uncorrect =====");
176 
      dbg_uart_wr(BRK1_ADDR0 ,  16'h0000);
177 
      dbg_uart_rd(BRK1_ADDR0);
178 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_ADDR0 uncorrect =====");
179 
 
180 
      dbg_uart_wr(BRK1_ADDR1 ,  16'hffff);
181 
      dbg_uart_rd(BRK1_ADDR1);
182 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK1_ADDR1 uncorrect =====");
183 
      dbg_uart_wr(BRK1_ADDR1 ,  16'h0000);
184 
      dbg_uart_rd(BRK1_ADDR1);
185 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_ADDR1 uncorrect =====");
186 
 
187 
 
188 
      // TEST HARDWARE BREAKPOINT 2 REGISTERS
189 
      //--------------------------------------------------------
190 
 
191 
      dbg_uart_wr(BRK2_CTL   ,  16'hffff);
192 
      dbg_uart_rd(BRK2_CTL);
193 
      if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK2_CTL uncorrect =====");
194 
      dbg_uart_wr(BRK2_CTL   ,  16'h0000);
195 
      dbg_uart_rd(BRK2_CTL);
196 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_CTL uncorrect =====");
197 
 
198 
      dbg_uart_wr(BRK2_STAT  ,  16'hffff);
199 
      dbg_uart_rd(BRK2_STAT);
200 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_STAT uncorrect =====");
201 
      dbg_uart_wr(BRK2_STAT  ,  16'h0000);
202 
      dbg_uart_rd(BRK2_STAT);
203 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_STAT uncorrect =====");
204 
 
205 
      dbg_uart_wr(BRK2_ADDR0 ,  16'hffff);
206 
      dbg_uart_rd(BRK2_ADDR0);
207 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK2_ADDR0 uncorrect =====");
208 
      dbg_uart_wr(BRK2_ADDR0 ,  16'h0000);
209 
      dbg_uart_rd(BRK2_ADDR0);
210 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_ADDR0 uncorrect =====");
211 
 
212 
      dbg_uart_wr(BRK2_ADDR1 ,  16'hffff);
213 
      dbg_uart_rd(BRK2_ADDR1);
214 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK2_ADDR1 uncorrect =====");
215 
      dbg_uart_wr(BRK2_ADDR1 ,  16'h0000);
216 
      dbg_uart_rd(BRK2_ADDR1);
217 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_ADDR1 uncorrect =====");
218 
 
219 
 
220 
      // TEST HARDWARE BREAKPOINT 3 REGISTERS
221 
      //--------------------------------------------------------
222 
 
223 
      dbg_uart_wr(BRK3_CTL   ,  16'hffff);
224 
      dbg_uart_rd(BRK3_CTL);
225 
      if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK3_CTL uncorrect =====");
226 
      dbg_uart_wr(BRK3_CTL   ,  16'h0000);
227 
      dbg_uart_rd(BRK3_CTL);
228 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_CTL uncorrect =====");
229 
 
230 
      dbg_uart_wr(BRK3_STAT  ,  16'hffff);
231 
      dbg_uart_rd(BRK3_STAT);
232 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_STAT uncorrect =====");
233 
      dbg_uart_wr(BRK3_STAT  ,  16'h0000);
234 
      dbg_uart_rd(BRK3_STAT);
235 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_STAT uncorrect =====");
236 
 
237 
      dbg_uart_wr(BRK3_ADDR0 ,  16'hffff);
238 
      dbg_uart_rd(BRK3_ADDR0);
239 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK3_ADDR0 uncorrect =====");
240 
      dbg_uart_wr(BRK3_ADDR0 ,  16'h0000);
241 
      dbg_uart_rd(BRK3_ADDR0);
242 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_ADDR0 uncorrect =====");
243 
 
244 
      dbg_uart_wr(BRK3_ADDR1 ,  16'hffff);
245 
      dbg_uart_rd(BRK3_ADDR1);
246 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK3_ADDR1 uncorrect =====");
247 
      dbg_uart_wr(BRK3_ADDR1 ,  16'h0000);
248 
      dbg_uart_rd(BRK3_ADDR1);
249 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_ADDR1 uncorrect =====");
250 
 
251 
 
252 
      // TEST 16B WRITE BURSTS (MEMORY)
253 
      //--------------------------------------------------------
254 
 
255 
      dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
256 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
257 
 
258 
      dbg_uart_wr(MEM_CTL,  16'h0003); // Start burst to 16 bit memory write
259 
      dbg_uart_tx16(16'h1234);         // write 1st data
260 
      repeat(10) @(posedge mclk);
261 
      if (mem200 !== 16'h1234)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
262 
      dbg_uart_tx16(16'h5678);         // write 2nd data
263 
      repeat(10) @(posedge mclk);
264 
      if (mem202 !== 16'h5678)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
265 
      dbg_uart_tx16(16'h9abc);         // write 3rd data
266 
      repeat(10) @(posedge mclk);
267 
      if (mem204 !== 16'h9abc)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
268 
      dbg_uart_tx16(16'hdef0);         // write 4th data
269 
      repeat(10) @(posedge mclk);
270 
      if (mem206 !== 16'hdef0)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
271 
      dbg_uart_tx16(16'h0fed);         // write 5th data
272 
      repeat(10) @(posedge mclk);
273 
      if (mem208 !== 16'h0fed)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
274 
 
275 
      dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
276 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
277 
 
278 
      dbg_uart_wr(MEM_CTL,  16'h0001); // Start burst to 16 bit registers read
279 
      dbg_uart_rx16();                 // read 1st data
280 
      if (dbg_uart_buf !== 16'h1234)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
281 
      dbg_uart_rx16();                 // read 2nd data
282 
      if (dbg_uart_buf !== 16'h5678)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
283 
      dbg_uart_rx16();                 // read 3rd data
284 
      if (dbg_uart_buf !== 16'h9abc)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
285 
      dbg_uart_rx16();                 // read 4th data
286 
      if (dbg_uart_buf !== 16'hdef0)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
287 
      dbg_uart_rx16();                 // read 5th data
288 
      if (dbg_uart_buf !== 16'h0fed)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
289 
 
290 
 
291 
      // TEST 16B WRITE BURSTS (CPU REGISTERS)
292 
      //--------------------------------------------------------
293 
 
294 
      dbg_uart_wr(MEM_ADDR, 16'h0005); // select R5
295 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
296 
 
297 
      dbg_uart_wr(MEM_CTL,  16'h0007); // Start burst to 16 bit cpu register write
298 
      dbg_uart_tx16(16'hcba9);         // write 1st data
299 
      repeat(10) @(posedge mclk);
300 
      if (r5 !== 16'hcba9)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 1st DATA =====");
301 
      dbg_uart_tx16(16'h8765);         // write 2nd data
302 
      repeat(10) @(posedge mclk);
303 
      if (r6 !== 16'h8765)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 2nd DATA =====");
304 
      dbg_uart_tx16(16'h4321);         // write 3rd data
305 
      repeat(10) @(posedge mclk);
306 
      if (r7 !== 16'h4321)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 3rd DATA =====");
307 
      dbg_uart_tx16(16'h0123);         // write 4th data
308 
      repeat(10) @(posedge mclk);
309 
      if (r8 !== 16'h0123)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 4th DATA =====");
310 
      dbg_uart_tx16(16'h4567);         // write 5th data
311 
      repeat(10) @(posedge mclk);
312 
      if (r9 !== 16'h4567)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 5th DATA =====");
313 
 
314 
      dbg_uart_wr(MEM_ADDR, 16'h0005); // select @0x0200
315 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
316 
 
317 
      dbg_uart_wr(MEM_CTL,  16'h0005); // Start burst to 16 bit cpu registers read
318 
      dbg_uart_rx16();                 // read 1st data
319 
      if (dbg_uart_buf !== 16'hcba9)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 1st DATA =====");
320 
      dbg_uart_rx16();                 // read 2nd data
321 
      if (dbg_uart_buf !== 16'h8765)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 2nd DATA =====");
322 
      dbg_uart_rx16();                 // read 3rd data
323 
      if (dbg_uart_buf !== 16'h4321)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 3rd DATA =====");
324 
      dbg_uart_rx16();                 // read 4th data
325 
      if (dbg_uart_buf !== 16'h0123)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 4th DATA =====");
326 
      dbg_uart_rx16();                 // read 5th data
327 
      if (dbg_uart_buf !== 16'h4567)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 5th DATA =====");
328 
 
329 
 
330 
      // TEST 8B WRITE BURSTS (MEMORY)
331 
      //--------------------------------------------------------
332 
 
333 
      dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0210
334 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
335 
 
336 
      dbg_uart_wr(MEM_CTL,  16'h000b); // Start burst to 8 bit memory write
337 
      dbg_uart_tx(8'h91);         // write 1st data
338 
      repeat(10) @(posedge mclk);
339 
      if (mem200 !== 16'h1291)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
340 
      dbg_uart_tx(8'h82);         // write 2nd data
341 
      repeat(10) @(posedge mclk);
342 
      if (mem200 !== 16'h8291)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
343 
      dbg_uart_tx(8'h73);         // write 3rd data
344 
      repeat(10) @(posedge mclk);
345 
      if (mem202 !== 16'h5673)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
346 
      dbg_uart_tx(8'h64);         // write 4th data
347 
      repeat(10) @(posedge mclk);
348 
      if (mem202 !== 16'h6473)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
349 
      dbg_uart_tx(8'h55);         // write 5th data
350 
      repeat(10) @(posedge mclk);
351 
      if (mem204 !== 16'h9a55)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
352 
 
353 
      dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
354 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
355 
 
356 
      dbg_uart_wr(MEM_CTL,  16'h0009); // Start burst to 8 bit registers read
357 
      dbg_uart_rx8();                 // read 1st data
358 
      if (dbg_uart_buf !== 16'h0091)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
359 
      dbg_uart_rx8();                 // read 2nd data
360 
      if (dbg_uart_buf !== 16'h0082)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
361 
      dbg_uart_rx8();                 // read 3rd data
362 
      if (dbg_uart_buf !== 16'h0073)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
363 
      dbg_uart_rx8();                 // read 4th data
364 
      if (dbg_uart_buf !== 16'h0064)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
365 
      dbg_uart_rx8();                 // read 5th data
366 
      if (dbg_uart_buf !== 16'h0055)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
367 
 
368 
 
369 
 
370 
 
371 
 
372 
      dbg_uart_wr(CPU_CTL    ,  16'h0002);
373 
      repeat(10) @(posedge mclk);
374 
 
375 
      stimulus_done = 1;
376 
   end
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