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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart.v] - Blame information for rev 74

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1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                            DEBUG INTERFACE:  UART                         */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the UART debug interface:                                            */
27 
/*                        - Check RD/WR access to debugg registers.          */
28 
/*                        - Check RD Bursts.                                 */
29 
/*                        - Check WR Bursts.                                 */
30 18 olivier.gi 
/*                                                                           */
31 
/* Author(s):                                                                */
32 
/*             - Olivier Girard,    olgirard@gmail.com                       */
33 
/*                                                                           */
34 
/*---------------------------------------------------------------------------*/
35 19 olivier.gi 
/* $Rev: 74 $                                                                */
36 
/* $LastChangedBy: olivier.girard $                                          */
37 
/* $LastChangedDate: 2010-08-28 21:53:08 +0200 (Sat, 28 Aug 2010) $          */
38 2 olivier.gi 
/*===========================================================================*/
39 
 
40 
`define LONG_TIMEOUT
41 
 
42 74 olivier.gi 
reg [15:0] dbg_id_pmem;
43 
reg [15:0] dbg_id_dmem;
44 2 olivier.gi 
reg [31:0] dbg_id;
45 
 
46 
initial
47 
   begin
48 
      $display(" ===============================================");
49 
      $display("|                 START SIMULATION              |");
50 
      $display(" ===============================================");
51 
      repeat(30) @(posedge mclk);
52 
      stimulus_done = 0;
53 
 
54 
      // SEND UART SYNCHRONIZATION FRAME
55 
      dbg_uart_tx(DBG_SYNC);
56 
 
57 
      // TEST CPU REGISTERS
58 
      //--------------------------------------------------------
59 74 olivier.gi 
      dbg_id_pmem = `PMEM_SIZE;
60 
      dbg_id_dmem = `DMEM_SIZE;
61 
      dbg_id      = {dbg_id_pmem, dbg_id_dmem};
62 2 olivier.gi 
 
63 
      dbg_uart_wr(CPU_ID_LO  ,  16'hffff);
64 
      dbg_uart_rd(CPU_ID_LO);
65 
      if (dbg_uart_buf !== dbg_id[15:0])  tb_error("====== CPU_ID_LO uncorrect =====");
66 
      dbg_uart_wr(CPU_ID_LO  ,  16'h0000);
67 
      dbg_uart_rd(CPU_ID_LO);
68 
      if (dbg_uart_buf !== dbg_id[15:0])  tb_error("====== CPU_ID_LO uncorrect =====");
69 
 
70 
      dbg_uart_wr(CPU_ID_HI  ,  16'hffff);
71 
      dbg_uart_rd(CPU_ID_HI);
72 
      if (dbg_uart_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect =====");
73 
      dbg_uart_wr(CPU_ID_HI  ,  16'h0000);
74 
      dbg_uart_rd(CPU_ID_HI);
75 
      if (dbg_uart_buf !== dbg_id[31:16]) tb_error("====== CPU_ID_HI uncorrect =====");
76 
 
77 
      dbg_uart_wr(CPU_STAT   ,  16'hffff);
78 
      dbg_uart_rd(CPU_STAT);
79 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== CPU_STAT uncorrect =====");
80 
      dbg_uart_wr(CPU_STAT   ,  16'h0000);
81 
      dbg_uart_rd(CPU_STAT);
82 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== CPU_STAT uncorrect =====");
83 
 
84 
      dbg_uart_wr(CPU_CTL    ,  16'hffff);
85 
      dbg_uart_rd(CPU_CTL);
86 
      if (dbg_uart_buf !== 16'h0078)      tb_error("====== CPU_CTL uncorrect =====");
87 
      dbg_uart_wr(CPU_CTL    ,  16'h0000);
88 
      dbg_uart_rd(CPU_CTL);
89 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== CPU_CTL uncorrect =====");
90 
 
91 
 
92 
      // TEST MEMORY CONTROL REGISTERS
93 
      //--------------------------------------------------------
94 
 
95 
      dbg_uart_wr(MEM_CTL    ,  16'hfffe);
96 
      dbg_uart_rd(MEM_CTL);
97 
      if (dbg_uart_buf !== 16'h000E)      tb_error("====== MEM_CTL uncorrect =====");
98 
      dbg_uart_wr(MEM_CTL    ,  16'h0000);
99 
      dbg_uart_rd(MEM_CTL);
100 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_CTL uncorrect =====");
101 
 
102 
      dbg_uart_wr(MEM_ADDR   ,  16'hffff);
103 
      dbg_uart_rd(MEM_ADDR);
104 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== MEM_ADDR uncorrect =====");
105 
      dbg_uart_wr(MEM_ADDR   ,  16'h0000);
106 
      dbg_uart_rd(MEM_ADDR);
107 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_ADDR uncorrect =====");
108 
 
109 
      dbg_uart_wr(MEM_DATA   ,  16'hffff);
110 
      dbg_uart_rd(MEM_DATA);
111 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== MEM_DATA uncorrect =====");
112 
      dbg_uart_wr(MEM_DATA   ,  16'h0000);
113 
      dbg_uart_rd(MEM_DATA);
114 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_DATA uncorrect =====");
115 
 
116 
      dbg_uart_wr(MEM_CNT    ,  16'hffff);
117 
      dbg_uart_rd(MEM_CNT);
118 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== MEM_CNT uncorrect =====");
119 
      dbg_uart_wr(MEM_CNT    ,  16'h0000);
120 
      dbg_uart_rd(MEM_CNT);
121 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== MEM_CNT uncorrect =====");
122 
 
123 
 
124 
      // TEST HARDWARE BREAKPOINT 0 REGISTERS
125 
      //--------------------------------------------------------
126 
 
127 
      dbg_uart_wr(BRK0_CTL   ,  16'hffff);
128 
      dbg_uart_rd(BRK0_CTL);
129 58 olivier.gi 
      if (`HWBRK_RANGE)
130 
        begin
131 
           if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK0_CTL uncorrect =====");
132 
        end
133 
      else
134 
        begin
135 
           if (dbg_uart_buf !== 16'h000F)      tb_error("====== BRK0_CTL uncorrect =====");
136 
        end
137 2 olivier.gi 
      dbg_uart_wr(BRK0_CTL   ,  16'h0000);
138 
      dbg_uart_rd(BRK0_CTL);
139 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_CTL uncorrect =====");
140 
 
141 
      dbg_uart_wr(BRK0_STAT  ,  16'hffff);
142 
      dbg_uart_rd(BRK0_STAT);
143 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_STAT uncorrect =====");
144 
      dbg_uart_wr(BRK0_STAT  ,  16'h0000);
145 
      dbg_uart_rd(BRK0_STAT);
146 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_STAT uncorrect =====");
147 
 
148 
      dbg_uart_wr(BRK0_ADDR0 ,  16'hffff);
149 
      dbg_uart_rd(BRK0_ADDR0);
150 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK0_ADDR0 uncorrect =====");
151 
      dbg_uart_wr(BRK0_ADDR0 ,  16'h0000);
152 
      dbg_uart_rd(BRK0_ADDR0);
153 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_ADDR0 uncorrect =====");
154 
 
155 
      dbg_uart_wr(BRK0_ADDR1 ,  16'hffff);
156 
      dbg_uart_rd(BRK0_ADDR1);
157 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK0_ADDR1 uncorrect =====");
158 
      dbg_uart_wr(BRK0_ADDR1 ,  16'h0000);
159 
      dbg_uart_rd(BRK0_ADDR1);
160 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK0_ADDR1 uncorrect =====");
161 
 
162 
 
163 
      // TEST HARDWARE BREAKPOINT 1 REGISTERS
164 
      //--------------------------------------------------------
165 
 
166 
      dbg_uart_wr(BRK1_CTL   ,  16'hffff);
167 
      dbg_uart_rd(BRK1_CTL);
168 58 olivier.gi 
      if (`HWBRK_RANGE)
169 
        begin
170 
           if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK1_CTL uncorrect =====");
171 
        end
172 
      else
173 
        begin
174 
           if (dbg_uart_buf !== 16'h000F)      tb_error("====== BRK1_CTL uncorrect =====");
175 
        end
176 2 olivier.gi 
      dbg_uart_wr(BRK1_CTL   ,  16'h0000);
177 
      dbg_uart_rd(BRK1_CTL);
178 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_CTL uncorrect =====");
179 
 
180 
      dbg_uart_wr(BRK1_STAT  ,  16'hffff);
181 
      dbg_uart_rd(BRK1_STAT);
182 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_STAT uncorrect =====");
183 
      dbg_uart_wr(BRK1_STAT  ,  16'h0000);
184 
      dbg_uart_rd(BRK1_STAT);
185 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_STAT uncorrect =====");
186 
 
187 
      dbg_uart_wr(BRK1_ADDR0 ,  16'hffff);
188 
      dbg_uart_rd(BRK1_ADDR0);
189 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK1_ADDR0 uncorrect =====");
190 
      dbg_uart_wr(BRK1_ADDR0 ,  16'h0000);
191 
      dbg_uart_rd(BRK1_ADDR0);
192 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_ADDR0 uncorrect =====");
193 
 
194 
      dbg_uart_wr(BRK1_ADDR1 ,  16'hffff);
195 
      dbg_uart_rd(BRK1_ADDR1);
196 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK1_ADDR1 uncorrect =====");
197 
      dbg_uart_wr(BRK1_ADDR1 ,  16'h0000);
198 
      dbg_uart_rd(BRK1_ADDR1);
199 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK1_ADDR1 uncorrect =====");
200 
 
201 
 
202 
      // TEST HARDWARE BREAKPOINT 2 REGISTERS
203 
      //--------------------------------------------------------
204 
 
205 
      dbg_uart_wr(BRK2_CTL   ,  16'hffff);
206 
      dbg_uart_rd(BRK2_CTL);
207 58 olivier.gi 
      if (`HWBRK_RANGE)
208 
        begin
209 
           if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK2_CTL uncorrect =====");
210 
        end
211 
      else
212 
        begin
213 
           if (dbg_uart_buf !== 16'h000F)      tb_error("====== BRK2_CTL uncorrect =====");
214 
        end
215 2 olivier.gi 
      dbg_uart_wr(BRK2_CTL   ,  16'h0000);
216 
      dbg_uart_rd(BRK2_CTL);
217 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_CTL uncorrect =====");
218 
 
219 
      dbg_uart_wr(BRK2_STAT  ,  16'hffff);
220 
      dbg_uart_rd(BRK2_STAT);
221 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_STAT uncorrect =====");
222 
      dbg_uart_wr(BRK2_STAT  ,  16'h0000);
223 
      dbg_uart_rd(BRK2_STAT);
224 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_STAT uncorrect =====");
225 
 
226 
      dbg_uart_wr(BRK2_ADDR0 ,  16'hffff);
227 
      dbg_uart_rd(BRK2_ADDR0);
228 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK2_ADDR0 uncorrect =====");
229 
      dbg_uart_wr(BRK2_ADDR0 ,  16'h0000);
230 
      dbg_uart_rd(BRK2_ADDR0);
231 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_ADDR0 uncorrect =====");
232 
 
233 
      dbg_uart_wr(BRK2_ADDR1 ,  16'hffff);
234 
      dbg_uart_rd(BRK2_ADDR1);
235 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK2_ADDR1 uncorrect =====");
236 
      dbg_uart_wr(BRK2_ADDR1 ,  16'h0000);
237 
      dbg_uart_rd(BRK2_ADDR1);
238 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK2_ADDR1 uncorrect =====");
239 
 
240 
 
241 
      // TEST HARDWARE BREAKPOINT 3 REGISTERS
242 
      //--------------------------------------------------------
243 
 
244 
      dbg_uart_wr(BRK3_CTL   ,  16'hffff);
245 
      dbg_uart_rd(BRK3_CTL);
246 58 olivier.gi 
      if (`HWBRK_RANGE)
247 
        begin
248 
           if (dbg_uart_buf !== 16'h001F)      tb_error("====== BRK3_CTL uncorrect =====");
249 
        end
250 
      else
251 
        begin
252 
           if (dbg_uart_buf !== 16'h000F)      tb_error("====== BRK3_CTL uncorrect =====");
253 
        end
254 2 olivier.gi 
      dbg_uart_wr(BRK3_CTL   ,  16'h0000);
255 
      dbg_uart_rd(BRK3_CTL);
256 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_CTL uncorrect =====");
257 
 
258 
      dbg_uart_wr(BRK3_STAT  ,  16'hffff);
259 
      dbg_uart_rd(BRK3_STAT);
260 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_STAT uncorrect =====");
261 
      dbg_uart_wr(BRK3_STAT  ,  16'h0000);
262 
      dbg_uart_rd(BRK3_STAT);
263 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_STAT uncorrect =====");
264 
 
265 
      dbg_uart_wr(BRK3_ADDR0 ,  16'hffff);
266 
      dbg_uart_rd(BRK3_ADDR0);
267 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK3_ADDR0 uncorrect =====");
268 
      dbg_uart_wr(BRK3_ADDR0 ,  16'h0000);
269 
      dbg_uart_rd(BRK3_ADDR0);
270 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_ADDR0 uncorrect =====");
271 
 
272 
      dbg_uart_wr(BRK3_ADDR1 ,  16'hffff);
273 
      dbg_uart_rd(BRK3_ADDR1);
274 
      if (dbg_uart_buf !== 16'hffff)      tb_error("====== BRK3_ADDR1 uncorrect =====");
275 
      dbg_uart_wr(BRK3_ADDR1 ,  16'h0000);
276 
      dbg_uart_rd(BRK3_ADDR1);
277 
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== BRK3_ADDR1 uncorrect =====");
278 
 
279 
 
280 
      // TEST 16B WRITE BURSTS (MEMORY)
281 
      //--------------------------------------------------------
282 
 
283 
      dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
284 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
285 
 
286 
      dbg_uart_wr(MEM_CTL,  16'h0003); // Start burst to 16 bit memory write
287 
      dbg_uart_tx16(16'h1234);         // write 1st data
288 
      repeat(10) @(posedge mclk);
289 
      if (mem200 !== 16'h1234)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
290 
      dbg_uart_tx16(16'h5678);         // write 2nd data
291 
      repeat(10) @(posedge mclk);
292 
      if (mem202 !== 16'h5678)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
293 
      dbg_uart_tx16(16'h9abc);         // write 3rd data
294 
      repeat(10) @(posedge mclk);
295 
      if (mem204 !== 16'h9abc)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
296 
      dbg_uart_tx16(16'hdef0);         // write 4th data
297 
      repeat(10) @(posedge mclk);
298 
      if (mem206 !== 16'hdef0)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
299 
      dbg_uart_tx16(16'h0fed);         // write 5th data
300 
      repeat(10) @(posedge mclk);
301 
      if (mem208 !== 16'h0fed)      tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
302 
 
303 
      dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
304 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
305 
 
306 
      dbg_uart_wr(MEM_CTL,  16'h0001); // Start burst to 16 bit registers read
307 
      dbg_uart_rx16();                 // read 1st data
308 
      if (dbg_uart_buf !== 16'h1234)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
309 
      dbg_uart_rx16();                 // read 2nd data
310 
      if (dbg_uart_buf !== 16'h5678)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
311 
      dbg_uart_rx16();                 // read 3rd data
312 
      if (dbg_uart_buf !== 16'h9abc)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
313 
      dbg_uart_rx16();                 // read 4th data
314 
      if (dbg_uart_buf !== 16'hdef0)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
315 
      dbg_uart_rx16();                 // read 5th data
316 
      if (dbg_uart_buf !== 16'h0fed)      tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
317 
 
318 
 
319 
      // TEST 16B WRITE BURSTS (CPU REGISTERS)
320 
      //--------------------------------------------------------
321 
 
322 
      dbg_uart_wr(MEM_ADDR, 16'h0005); // select R5
323 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
324 
 
325 
      dbg_uart_wr(MEM_CTL,  16'h0007); // Start burst to 16 bit cpu register write
326 
      dbg_uart_tx16(16'hcba9);         // write 1st data
327 
      repeat(10) @(posedge mclk);
328 
      if (r5 !== 16'hcba9)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 1st DATA =====");
329 
      dbg_uart_tx16(16'h8765);         // write 2nd data
330 
      repeat(10) @(posedge mclk);
331 
      if (r6 !== 16'h8765)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 2nd DATA =====");
332 
      dbg_uart_tx16(16'h4321);         // write 3rd data
333 
      repeat(10) @(posedge mclk);
334 
      if (r7 !== 16'h4321)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 3rd DATA =====");
335 
      dbg_uart_tx16(16'h0123);         // write 4th data
336 
      repeat(10) @(posedge mclk);
337 
      if (r8 !== 16'h0123)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 4th DATA =====");
338 
      dbg_uart_tx16(16'h4567);         // write 5th data
339 
      repeat(10) @(posedge mclk);
340 
      if (r9 !== 16'h4567)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 5th DATA =====");
341 
 
342 
      dbg_uart_wr(MEM_ADDR, 16'h0005); // select @0x0200
343 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
344 
 
345 
      dbg_uart_wr(MEM_CTL,  16'h0005); // Start burst to 16 bit cpu registers read
346 
      dbg_uart_rx16();                 // read 1st data
347 
      if (dbg_uart_buf !== 16'hcba9)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 1st DATA =====");
348 
      dbg_uart_rx16();                 // read 2nd data
349 
      if (dbg_uart_buf !== 16'h8765)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 2nd DATA =====");
350 
      dbg_uart_rx16();                 // read 3rd data
351 
      if (dbg_uart_buf !== 16'h4321)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 3rd DATA =====");
352 
      dbg_uart_rx16();                 // read 4th data
353 
      if (dbg_uart_buf !== 16'h0123)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 4th DATA =====");
354 
      dbg_uart_rx16();                 // read 5th data
355 
      if (dbg_uart_buf !== 16'h4567)      tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) RD ERROR: 5th DATA =====");
356 
 
357 
 
358 
      // TEST 8B WRITE BURSTS (MEMORY)
359 
      //--------------------------------------------------------
360 
 
361 
      dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0210
362 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
363 
 
364 
      dbg_uart_wr(MEM_CTL,  16'h000b); // Start burst to 8 bit memory write
365 
      dbg_uart_tx(8'h91);         // write 1st data
366 
      repeat(10) @(posedge mclk);
367 
      if (mem200 !== 16'h1291)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
368 
      dbg_uart_tx(8'h82);         // write 2nd data
369 
      repeat(10) @(posedge mclk);
370 
      if (mem200 !== 16'h8291)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
371 
      dbg_uart_tx(8'h73);         // write 3rd data
372 
      repeat(10) @(posedge mclk);
373 
      if (mem202 !== 16'h5673)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
374 
      dbg_uart_tx(8'h64);         // write 4th data
375 
      repeat(10) @(posedge mclk);
376 
      if (mem202 !== 16'h6473)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
377 
      dbg_uart_tx(8'h55);         // write 5th data
378 
      repeat(10) @(posedge mclk);
379 
      if (mem204 !== 16'h9a55)      tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
380 
 
381 
      dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
382 
      dbg_uart_wr(MEM_CNT,  16'h0004); // 5 consecutive access
383 
 
384 
      dbg_uart_wr(MEM_CTL,  16'h0009); // Start burst to 8 bit registers read
385 
      dbg_uart_rx8();                 // read 1st data
386 
      if (dbg_uart_buf !== 16'h0091)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
387 
      dbg_uart_rx8();                 // read 2nd data
388 
      if (dbg_uart_buf !== 16'h0082)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 2nd DATA =====");
389 
      dbg_uart_rx8();                 // read 3rd data
390 
      if (dbg_uart_buf !== 16'h0073)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 3rd DATA =====");
391 
      dbg_uart_rx8();                 // read 4th data
392 
      if (dbg_uart_buf !== 16'h0064)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 4th DATA =====");
393 
      dbg_uart_rx8();                 // read 5th data
394 
      if (dbg_uart_buf !== 16'h0055)      tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 5th DATA =====");
395 
 
396 
 
397 
 
398 
 
399 
 
400 
      dbg_uart_wr(CPU_CTL    ,  16'h0002);
401 
      repeat(10) @(posedge mclk);
402 
 
403 
      stimulus_done = 1;
404 
   end
405 
 

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