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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart_cpu.v] - Blame information for rev 162

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            DEBUG INTERFACE                                */
/*---------------------------------------------------------------------------*/
/* Test the debug interface:                                                 */
/*                           - CPU Control features.                         */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 154 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2012-10-15 22:44:20 +0200 (Mon, 15 Oct 2012) $          */
/*===========================================================================*/
 
 
   integer my_test;
   integer test_var;
 
 
initial
   begin
      $display(" ===============================================");
      $display("|                 START SIMULATION              |");
      $display(" ===============================================");
`ifdef DBG_EN
`ifdef DBG_UART
      #1 dbg_en = 1;
      repeat(30) @(posedge mclk);
      stimulus_done = 0;
 
      // SEND UART SYNCHRONIZATION FRAME
      dbg_uart_tx(DBG_SYNC);
 
   `ifdef DBG_RST_BRK_EN
      dbg_uart_wr(CPU_CTL,  16'h0002);  // RUN
   `endif
 
 
      // STOP, FREEZE, ISTEP, RUN
      //--------------------------------------------------------
 
      dbg_uart_wr(CPU_STAT,  16'h00ff); // HALT
      dbg_uart_rd(CPU_STAT);            // READ STATUS
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== STOP, FREEZE, ISTEP, RUN: status test 1 =====");
 
      dbg_uart_wr(CPU_CTL,  16'h0001);  // HALT
      repeat(10) @(posedge mclk);
      test_var = inst_number;
      repeat(50) @(posedge mclk);
      if (test_var !== inst_number)       tb_error("====== STOP, FREEZE, ISTEP, RUN: HALT function =====");
 
      dbg_uart_rd(CPU_STAT);            // READ STATUS
      if (dbg_uart_buf !== 16'h0001)      tb_error("====== STOP, FREEZE, ISTEP, RUN: HALT status - test 1 =====");
 
      if (dbg_freeze !== 1'b0)            tb_error("====== STOP, FREEZE, ISTEP, RUN: FREEZE value - test 1 =====");
      dbg_uart_wr(CPU_CTL,  16'h0010);  // FREEZE WITH BREAK
      repeat(10) @(posedge mclk);
      if (dbg_freeze !== 1'b1)            tb_error("====== STOP, FREEZE, ISTEP, RUN: FREEZE value - test 2 =====");
 
 
      test_var = r14;
      dbg_uart_wr(CPU_CTL,  16'h0004); // ISTEP
      dbg_uart_wr(CPU_CTL,  16'h0004); // ISTEP
      repeat(12) @(posedge mclk);
      if (test_var !== (r14+1))           tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 1 =====");
      dbg_uart_wr(CPU_CTL,  16'h0004); // ISTEP
      dbg_uart_wr(CPU_CTL,  16'h0004); // ISTEP
      repeat(12) @(posedge mclk);
      if (test_var !== (r14+2))           tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 2 =====");
      dbg_uart_wr(CPU_CTL,  16'h0004); // ISTEP
      dbg_uart_wr(CPU_CTL,  16'h0004); // ISTEP
      repeat(12) @(posedge mclk);
      if (test_var !== (r14+3))           tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 3 =====");
 
 
      test_var = inst_number;
      dbg_uart_wr(CPU_CTL,  16'h0002); // RUN
      repeat(50) @(posedge mclk);
      if (test_var === inst_number)       tb_error("====== STOP, FREEZE, ISTEP, RUN: RUN function - test 1 =====");
      test_var = inst_number;
      repeat(50) @(posedge mclk);
      if (test_var === inst_number)       tb_error("====== STOP, FREEZE, ISTEP, RUN: RUN function - test 2 =====");
 
      dbg_uart_rd(CPU_STAT);           // READ STATUS
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== STOP/RUN, ISTEP: HALT status - test 2 =====");
 
 
 
      // RESET / BREAK ON RESET
      //--------------------------------------------------------
 
      test_var = r14;
      dbg_uart_wr(CPU_CTL,  16'h0040); // RESET CPU
      dbg_uart_rd(CPU_STAT);           // READ STATUS
      if (dbg_uart_buf !== 16'h0004)      tb_error("====== RESET / BREAK ON RESET: RESET error- test 1 =====");
      if (puc_rst      !== 1'b1)          tb_error("====== RESET / BREAK ON RESET: RESET error- test 2 =====");
      dbg_uart_wr(CPU_CTL,  16'h0000); // RELEASE RESET
      dbg_uart_rd(CPU_STAT);           // READ STATUS
      if (dbg_uart_buf !== 16'h0004)      tb_error("====== RESET / BREAK ON RESET: RESET error- test 3 =====");
      if (puc_rst      !== 1'b0)          tb_error("====== RESET / BREAK ON RESET: RESET error- test 4 =====");
      if (test_var >= r14)                tb_error("====== RESET / BREAK ON RESET: RESET error- test 5 =====");
      dbg_uart_wr(CPU_STAT,  16'h0004); // CLEAR STATUS
      dbg_uart_rd(CPU_STAT);            // READ STATUS
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== RESET / BREAK ON RESET: RESET error- test 6 =====");
 
 
      test_var = r14;
      dbg_uart_wr(CPU_CTL,  16'h0060); // RESET & BREAK ON RESET
      dbg_uart_rd(CPU_STAT);           // READ STATUS
      if (dbg_uart_buf !== 16'h0004)      tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 1 =====");
      if (puc_rst      !== 1'b1)          tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 2 =====");
      dbg_uart_wr(CPU_CTL,  16'h0020); // RELEASE RESET
      dbg_uart_rd(CPU_STAT);           // READ STATUS
      if (dbg_uart_buf !== 16'h0005)      tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 3 =====");
      if (puc_rst      !== 1'b0)          tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 4 =====");
      repeat(10) @(posedge mclk);
      test_var = inst_number;
      repeat(50) @(posedge mclk);
      if (test_var !== inst_number)       tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 5 =====");
      if (r0       !== irq_vect_15)       tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 6 =====");
 
      dbg_uart_wr(CPU_STAT,  16'h0004); // CLEAR STATUS
      dbg_uart_rd(CPU_STAT);            // READ STATUS
      if (dbg_uart_buf !== 16'h0001)      tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 7 =====");
 
      dbg_uart_wr(CPU_CTL,  16'h0002);  // RUN
      dbg_uart_rd(CPU_STAT);            // READ STATUS
      if (dbg_uart_buf !== 16'h0000)      tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 8 =====");
 
 
      // SOFTWARE BREAKPOINT
      //--------------------------------------------------------
 
      dbg_uart_wr(CPU_CTL,  16'h0048);  // RESET & ENABLE SOFTWARE BREAKPOINT
      dbg_uart_wr(CPU_CTL,  16'h0008);  // RELEASE RESET
      dbg_uart_rd(CPU_STAT);            // READ STATUS
      if (dbg_uart_buf !== 16'h000D)      tb_error("====== SOFTWARE BREAKPOINT: test 1 =====");
      if (r0           !== ('h10000-`PMEM_SIZE+'h12))      tb_error("====== SOFTWARE BREAKPOINT: test 2 =====");
      dbg_uart_wr(CPU_STAT,  16'h000C); // CLEAR STATUS
      dbg_uart_rd(CPU_STAT);            // READ STATUS
      if (dbg_uart_buf !== 16'h0001)      tb_error("====== SOFTWARE BREAKPOINT: test 3 =====");
 
      // Replace software breakpoint with a mov #2, r15 (opcode=0x432f)
      dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h12));
      dbg_uart_wr(MEM_DATA, 16'h432f);
      dbg_uart_wr(MEM_CTL,  16'h0003);
 
      // Dummy write
      dbg_uart_wr(MEM_ADDR, 16'hff00);
      dbg_uart_wr(MEM_DATA, 16'h1234);
      dbg_uart_wr(MEM_CTL,  16'h0003);
 
      // RUN
      dbg_uart_wr(CPU_CTL,  16'h000A);
      repeat(20) @(posedge mclk);
      if (r15     !== 16'h0002)           tb_error("====== SOFTWARE BREAKPOINT: test 4 =====");
 
      dbg_uart_rd(CPU_STAT);            // READ STATUS
      if (dbg_uart_buf !== 16'h0009)      tb_error("====== SOFTWARE BREAKPOINT: test 5 =====");
      if (r0           !== ('h10000-`PMEM_SIZE+'h16))      tb_error("====== SOFTWARE BREAKPOINT: test 6 =====");
      dbg_uart_wr(CPU_STAT,  16'h0008); // CLEAR STATUS
      dbg_uart_rd(CPU_STAT);            // READ STATUS
      if (dbg_uart_buf !== 16'h0001)      tb_error("====== SOFTWARE BREAKPOINT: test 7 =====");
 
 
      // Replace software breakpoint with a mov #4, r15 (opcode=0x422f)
      dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h16));
      dbg_uart_wr(MEM_DATA, 16'h422f);
      dbg_uart_wr(MEM_CTL,  16'h0003);
 
      // Dummy write
      dbg_uart_wr(MEM_ADDR, 16'hff00);
      dbg_uart_wr(MEM_DATA, 16'h5678);
      dbg_uart_wr(MEM_CTL,  16'h0003);
 
      // RUN
      dbg_uart_wr(CPU_CTL,  16'h000A);
      repeat(20) @(posedge mclk);
      if (r15     !== 16'h0004)           tb_error("====== SOFTWARE BREAKPOINT: test 8 =====");
 
 
      stimulus_done = 1;
`else
 
       $display(" ===============================================");
       $display("|               SIMULATION SKIPPED              |");
       $display("|   (serial debug interface UART not included)  |");
       $display(" ===============================================");
       $finish;
`endif
`else
 
       $display(" ===============================================");
       $display("|               SIMULATION SKIPPED              |");
       $display("|      (serial debug interface not included)    |");
       $display(" ===============================================");
       $finish;
`endif
   end
 

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* DEBUG INTERFACE */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the debug interface: */`
27			`/* - CPU Control features. */`
28	18	olivier.gi	`/* */`
29			`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32			`/---------------------------------------------------------------------------/`
33	19	olivier.gi	`/* $Rev: 154 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2012-10-15 22:44:20 +0200 (Mon, 15 Oct 2012) $ */`
36	2	olivier.gi	`/===========================================================================/`
37
38
39			`integer my_test;`
40			`integer test_var;`
41
42
43			`initial`
44			`begin`
45			`$display(" ===============================================");`
46			`$display("\| START SIMULATION \|");`
47			`$display(" ===============================================");`
48	111	olivier.gi	`ifdef DBG_EN
49	154	olivier.gi	`ifdef DBG_UART
50	106	olivier.gi	`#1 dbg_en = 1;`
51	2	olivier.gi	`repeat(30) @(posedge mclk);`
52			`stimulus_done = 0;`
53
54			`// SEND UART SYNCHRONIZATION FRAME`
55			`dbg_uart_tx(DBG_SYNC);`
56
57	106	olivier.gi	`ifdef DBG_RST_BRK_EN
58			`dbg_uart_wr(CPU_CTL, 16'h0002); // RUN`
59			`endif
60
61
62	2	olivier.gi	`// STOP, FREEZE, ISTEP, RUN`
63			`//--------------------------------------------------------`
64
65			`dbg_uart_wr(CPU_STAT, 16'h00ff); // HALT`
66			`dbg_uart_rd(CPU_STAT); // READ STATUS`
67			`if (dbg_uart_buf !== 16'h0000) tb_error("====== STOP, FREEZE, ISTEP, RUN: status test 1 =====");`
68
69			`dbg_uart_wr(CPU_CTL, 16'h0001); // HALT`
70			`repeat(10) @(posedge mclk);`
71			`test_var = inst_number;`
72			`repeat(50) @(posedge mclk);`
73			`if (test_var !== inst_number) tb_error("====== STOP, FREEZE, ISTEP, RUN: HALT function =====");`
74
75			`dbg_uart_rd(CPU_STAT); // READ STATUS`
76			`if (dbg_uart_buf !== 16'h0001) tb_error("====== STOP, FREEZE, ISTEP, RUN: HALT status - test 1 =====");`
77
78			`if (dbg_freeze !== 1'b0) tb_error("====== STOP, FREEZE, ISTEP, RUN: FREEZE value - test 1 =====");`
79			`dbg_uart_wr(CPU_CTL, 16'h0010); // FREEZE WITH BREAK`
80			`repeat(10) @(posedge mclk);`
81			`if (dbg_freeze !== 1'b1) tb_error("====== STOP, FREEZE, ISTEP, RUN: FREEZE value - test 2 =====");`
82
83
84			`test_var = r14;`
85			`dbg_uart_wr(CPU_CTL, 16'h0004); // ISTEP`
86			`dbg_uart_wr(CPU_CTL, 16'h0004); // ISTEP`
87	95	olivier.gi	`repeat(12) @(posedge mclk);`
88	2	olivier.gi	`if (test_var !== (r14+1)) tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 1 =====");`
89			`dbg_uart_wr(CPU_CTL, 16'h0004); // ISTEP`
90			`dbg_uart_wr(CPU_CTL, 16'h0004); // ISTEP`
91	95	olivier.gi	`repeat(12) @(posedge mclk);`
92	2	olivier.gi	`if (test_var !== (r14+2)) tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 2 =====");`
93			`dbg_uart_wr(CPU_CTL, 16'h0004); // ISTEP`
94			`dbg_uart_wr(CPU_CTL, 16'h0004); // ISTEP`
95	95	olivier.gi	`repeat(12) @(posedge mclk);`
96	2	olivier.gi	`if (test_var !== (r14+3)) tb_error("====== STOP, FREEZE, ISTEP, RUN: ISTEP test 3 =====");`
97
98
99			`test_var = inst_number;`
100			`dbg_uart_wr(CPU_CTL, 16'h0002); // RUN`
101			`repeat(50) @(posedge mclk);`
102			`if (test_var === inst_number) tb_error("====== STOP, FREEZE, ISTEP, RUN: RUN function - test 1 =====");`
103			`test_var = inst_number;`
104			`repeat(50) @(posedge mclk);`
105			`if (test_var === inst_number) tb_error("====== STOP, FREEZE, ISTEP, RUN: RUN function - test 2 =====");`
106
107			`dbg_uart_rd(CPU_STAT); // READ STATUS`
108			`if (dbg_uart_buf !== 16'h0000) tb_error("====== STOP/RUN, ISTEP: HALT status - test 2 =====");`
109
110
111
112			`// RESET / BREAK ON RESET`
113			`//--------------------------------------------------------`
114
115			`test_var = r14;`
116			`dbg_uart_wr(CPU_CTL, 16'h0040); // RESET CPU`
117			`dbg_uart_rd(CPU_STAT); // READ STATUS`
118			`if (dbg_uart_buf !== 16'h0004) tb_error("====== RESET / BREAK ON RESET: RESET error- test 1 =====");`
119	111	olivier.gi	`if (puc_rst !== 1'b1) tb_error("====== RESET / BREAK ON RESET: RESET error- test 2 =====");`
120	2	olivier.gi	`dbg_uart_wr(CPU_CTL, 16'h0000); // RELEASE RESET`
121			`dbg_uart_rd(CPU_STAT); // READ STATUS`
122			`if (dbg_uart_buf !== 16'h0004) tb_error("====== RESET / BREAK ON RESET: RESET error- test 3 =====");`
123	111	olivier.gi	`if (puc_rst !== 1'b0) tb_error("====== RESET / BREAK ON RESET: RESET error- test 4 =====");`
124	2	olivier.gi	`if (test_var >= r14) tb_error("====== RESET / BREAK ON RESET: RESET error- test 5 =====");`
125			`dbg_uart_wr(CPU_STAT, 16'h0004); // CLEAR STATUS`
126			`dbg_uart_rd(CPU_STAT); // READ STATUS`
127			`if (dbg_uart_buf !== 16'h0000) tb_error("====== RESET / BREAK ON RESET: RESET error- test 6 =====");`
128
129
130			`test_var = r14;`
131			`dbg_uart_wr(CPU_CTL, 16'h0060); // RESET & BREAK ON RESET`
132			`dbg_uart_rd(CPU_STAT); // READ STATUS`
133			`if (dbg_uart_buf !== 16'h0004) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 1 =====");`
134	111	olivier.gi	`if (puc_rst !== 1'b1) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 2 =====");`
135	2	olivier.gi	`dbg_uart_wr(CPU_CTL, 16'h0020); // RELEASE RESET`
136			`dbg_uart_rd(CPU_STAT); // READ STATUS`
137			`if (dbg_uart_buf !== 16'h0005) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 3 =====");`
138	111	olivier.gi	`if (puc_rst !== 1'b0) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 4 =====");`
139	2	olivier.gi	`repeat(10) @(posedge mclk);`
140			`test_var = inst_number;`
141			`repeat(50) @(posedge mclk);`
142			`if (test_var !== inst_number) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 5 =====");`
143			`if (r0 !== irq_vect_15) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 6 =====");`
144
145			`dbg_uart_wr(CPU_STAT, 16'h0004); // CLEAR STATUS`
146			`dbg_uart_rd(CPU_STAT); // READ STATUS`
147			`if (dbg_uart_buf !== 16'h0001) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 7 =====");`
148
149			`dbg_uart_wr(CPU_CTL, 16'h0002); // RUN`
150			`dbg_uart_rd(CPU_STAT); // READ STATUS`
151			`if (dbg_uart_buf !== 16'h0000) tb_error("====== RESET / BREAK ON RESET: BREAK ON RESET error- test 8 =====");`
152
153
154			`// SOFTWARE BREAKPOINT`
155			`//--------------------------------------------------------`
156
157			`dbg_uart_wr(CPU_CTL, 16'h0048); // RESET & ENABLE SOFTWARE BREAKPOINT`
158			`dbg_uart_wr(CPU_CTL, 16'h0008); // RELEASE RESET`
159			`dbg_uart_rd(CPU_STAT); // READ STATUS`
160			`if (dbg_uart_buf !== 16'h000D) tb_error("====== SOFTWARE BREAKPOINT: test 1 =====");`
161	86	olivier.gi	if (r0 !== ('h10000-`PMEM_SIZE+'h12)) tb_error("====== SOFTWARE BREAKPOINT: test 2 =====");
162	2	olivier.gi	`dbg_uart_wr(CPU_STAT, 16'h000C); // CLEAR STATUS`
163			`dbg_uart_rd(CPU_STAT); // READ STATUS`
164			`if (dbg_uart_buf !== 16'h0001) tb_error("====== SOFTWARE BREAKPOINT: test 3 =====");`
165
166			`// Replace software breakpoint with a mov #2, r15 (opcode=0x432f)`
167	86	olivier.gi	dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h12));
168	2	olivier.gi	`dbg_uart_wr(MEM_DATA, 16'h432f);`
169			`dbg_uart_wr(MEM_CTL, 16'h0003);`
170
171			`// Dummy write`
172			`dbg_uart_wr(MEM_ADDR, 16'hff00);`
173			`dbg_uart_wr(MEM_DATA, 16'h1234);`
174			`dbg_uart_wr(MEM_CTL, 16'h0003);`
175
176			`// RUN`
177			`dbg_uart_wr(CPU_CTL, 16'h000A);`
178			`repeat(20) @(posedge mclk);`
179			`if (r15 !== 16'h0002) tb_error("====== SOFTWARE BREAKPOINT: test 4 =====");`
180
181			`dbg_uart_rd(CPU_STAT); // READ STATUS`
182			`if (dbg_uart_buf !== 16'h0009) tb_error("====== SOFTWARE BREAKPOINT: test 5 =====");`
183	86	olivier.gi	if (r0 !== ('h10000-`PMEM_SIZE+'h16)) tb_error("====== SOFTWARE BREAKPOINT: test 6 =====");
184	2	olivier.gi	`dbg_uart_wr(CPU_STAT, 16'h0008); // CLEAR STATUS`
185			`dbg_uart_rd(CPU_STAT); // READ STATUS`
186			`if (dbg_uart_buf !== 16'h0001) tb_error("====== SOFTWARE BREAKPOINT: test 7 =====");`
187
188
189			`// Replace software breakpoint with a mov #4, r15 (opcode=0x422f)`
190	86	olivier.gi	dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h16));
191	2	olivier.gi	`dbg_uart_wr(MEM_DATA, 16'h422f);`
192			`dbg_uart_wr(MEM_CTL, 16'h0003);`
193
194			`// Dummy write`
195			`dbg_uart_wr(MEM_ADDR, 16'hff00);`
196			`dbg_uart_wr(MEM_DATA, 16'h5678);`
197			`dbg_uart_wr(MEM_CTL, 16'h0003);`
198
199			`// RUN`
200			`dbg_uart_wr(CPU_CTL, 16'h000A);`
201			`repeat(20) @(posedge mclk);`
202			`if (r15 !== 16'h0004) tb_error("====== SOFTWARE BREAKPOINT: test 8 =====");`
203
204
205			`stimulus_done = 1;`
206	111	olivier.gi	`else
207
208			`$display(" ===============================================");`
209			`$display("\| SIMULATION SKIPPED \|");`
210	154	olivier.gi	`$display("\| (serial debug interface UART not included) \|");`
211			`$display(" ===============================================");`
212			`$finish;`
213			`endif
214			`else
215
216			`$display(" ===============================================");`
217			`$display("\| SIMULATION SKIPPED \|");`
218	111	olivier.gi	`$display("\| (serial debug interface not included) \|");`
219			`$display(" ===============================================");`
220			`$finish;`
221			`endif
222	2	olivier.gi	`end`
223

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart_cpu.v] - Blame information for rev 162