OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart_hwbrk2.v] - Blame information for rev 219

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                            DEBUG INTERFACE                                */
25
/*---------------------------------------------------------------------------*/
26
/* Test the debug interface:                                                 */
27
/*                        - Check Hardware breakpoint unit 2.                */
28 18 olivier.gi
/*                                                                           */
29
/* Author(s):                                                                */
30
/*             - Olivier Girard,    olgirard@gmail.com                       */
31
/*                                                                           */
32
/*---------------------------------------------------------------------------*/
33 19 olivier.gi
/* $Rev: 202 $                                                                */
34
/* $LastChangedBy: olivier.girard $                                          */
35
/* $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $          */
36 2 olivier.gi
/*===========================================================================*/
37
 
38
`define LONG_TIMEOUT
39 202 olivier.gi
 
40 2 olivier.gi
initial
41
   begin
42
      $display(" ===============================================");
43
      $display("|                 START SIMULATION              |");
44
      $display(" ===============================================");
45 111 olivier.gi
`ifdef DBG_EN
46 154 olivier.gi
`ifdef DBG_UART
47 111 olivier.gi
`ifdef DBG_HWBRK_2
48 106 olivier.gi
      #1 dbg_en = 1;
49 2 olivier.gi
      repeat(30) @(posedge mclk);
50
      stimulus_done = 0;
51
 
52
      // SEND UART SYNCHRONIZATION FRAME
53
      dbg_uart_tx(DBG_SYNC);
54
 
55 106 olivier.gi
   `ifdef DBG_RST_BRK_EN
56
      dbg_uart_wr(CPU_CTL,  16'h0002);  // RUN
57
   `endif
58
 
59 202 olivier.gi
 
60 2 olivier.gi
      // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES
61
      //----------------------------------------------------------------------
62
 
63
      // RESET & BREAK
64
      dbg_uart_wr(CPU_CTL, 16'h0060);
65
      dbg_uart_wr(CPU_CTL, 16'h0020);
66
 
67
      // CONFIGURE BREAKPOINT (DISABLED) & RUN
68 86 olivier.gi
      dbg_uart_wr(BRK2_ADDR0, ('h10000-`PMEM_SIZE+'h04));
69
      dbg_uart_wr(BRK2_ADDR1, ('h10000-`PMEM_SIZE+'h18));
70 2 olivier.gi
      dbg_uart_wr(BRK2_CTL,   16'h000C);
71
      dbg_uart_wr(CPU_CTL,    16'h0002);
72
      repeat(100) @(posedge mclk);
73
 
74
      // RESET & BREAK
75
      dbg_uart_wr(CPU_CTL,  16'h0060);
76
      dbg_uart_wr(CPU_CTL,  16'h0020);
77
      dbg_uart_wr(CPU_STAT, 16'h00ff);
78
 
79
      // CHECK
80
      if (mem200 === 16'h0000)  tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 1 =====");
81 202 olivier.gi
 
82 2 olivier.gi
      // CONFIGURE BREAKPOINT (ENABLED) & RUN
83 86 olivier.gi
      dbg_uart_wr(BRK2_ADDR0, ('h10000-`PMEM_SIZE+'h04));
84
      dbg_uart_wr(BRK2_ADDR1, ('h10000-`PMEM_SIZE+'h18));
85 2 olivier.gi
      dbg_uart_wr(BRK2_CTL,   16'h000D);
86
      dbg_uart_wr(CPU_CTL,    16'h0002);
87
      repeat(100) @(posedge mclk);
88
 
89
      // CHECK
90 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h04))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 2 =====");
91 2 olivier.gi
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 3 =====");
92
      dbg_uart_rd(CPU_STAT);
93
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 4 =====");
94
      dbg_uart_rd(BRK2_STAT);
95
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 5 =====");
96
      dbg_uart_wr(BRK2_STAT, 16'h0001);
97
      dbg_uart_rd(CPU_STAT);
98
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 6 =====");
99 202 olivier.gi
 
100 2 olivier.gi
      // RE-RUN
101
      dbg_uart_wr(BRK2_ADDR0, 16'h0000);
102
      dbg_uart_wr(CPU_CTL,    16'h0002);
103
      repeat(100) @(posedge mclk);
104
 
105
      // RE-CHECK
106 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h18))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 7 =====");
107 2 olivier.gi
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 8 =====");
108
      dbg_uart_rd(CPU_STAT);
109
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 9 =====");
110
      dbg_uart_rd(BRK2_STAT);
111
      if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 10 =====");
112
      dbg_uart_wr(BRK2_STAT, 16'h0004);
113
      dbg_uart_rd(CPU_STAT);
114
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES: test 11 =====");
115
 
116
 
117
 
118
      // HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE
119
      //----------------------------------------------------------------------
120 58 olivier.gi
      if (`HWBRK_RANGE)
121
        begin
122 202 olivier.gi
 
123 2 olivier.gi
      // RESET, BREAK & CLEAR STATUS
124
      dbg_uart_wr(CPU_CTL,    16'h0060);
125
      dbg_uart_wr(CPU_CTL,    16'h0020);
126
      dbg_uart_wr(BRK2_STAT,  16'h00ff);
127
      dbg_uart_wr(CPU_STAT,   16'h00ff);
128
 
129
      // CONFIGURE BREAKPOINT(ENABLED) & RUN
130 86 olivier.gi
      dbg_uart_wr(BRK2_ADDR0, ('h10000-`PMEM_SIZE-'h100));
131
      dbg_uart_wr(BRK2_ADDR1, ('h10000-`PMEM_SIZE+'h20));
132 2 olivier.gi
      dbg_uart_wr(BRK2_CTL,   16'h001D);
133
      dbg_uart_wr(CPU_CTL,    16'h0002);
134
      repeat(100) @(posedge mclk);
135
 
136
      // CHECK
137 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 1 =====");
138 2 olivier.gi
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 2 =====");
139
      dbg_uart_rd(CPU_STAT);
140
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 3 =====");
141
      dbg_uart_rd(BRK2_STAT);
142
      if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 4 =====");
143
      dbg_uart_wr(BRK2_STAT, 16'h0010);
144
      dbg_uart_rd(CPU_STAT);
145
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE: test 5 =====");
146 58 olivier.gi
        end
147 202 olivier.gi
 
148
 
149 2 olivier.gi
      // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ
150
      //----------------------------------------------------------------------------
151
 
152
      // RESET, BREAK & CLEAR STATUS
153
      dbg_uart_wr(CPU_CTL,    16'h0060);
154
      dbg_uart_wr(CPU_CTL,    16'h0020);
155
      dbg_uart_wr(BRK2_STAT,  16'h00ff);
156
      dbg_uart_wr(CPU_STAT,   16'h00ff);
157
 
158 202 olivier.gi
 
159 2 olivier.gi
      // CONFIGURE BREAKPOINT (ENABLED) & RUN
160 111 olivier.gi
      dbg_uart_wr(BRK2_ADDR0, (`PER_SIZE+16'h0004));
161
      dbg_uart_wr(BRK2_ADDR1, (`PER_SIZE+16'h0008));
162 2 olivier.gi
      dbg_uart_wr(BRK2_CTL,   16'h0005);
163
      dbg_uart_wr(CPU_CTL,    16'h0002);
164
      repeat(100) @(posedge mclk);
165
 
166
      // CHECK
167 175 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h0c))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
168
      if (mem200 !== 16'h0000)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
169 2 olivier.gi
      dbg_uart_rd(CPU_STAT);
170
      if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 =====");
171
      dbg_uart_rd(BRK2_STAT);
172
      if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 4 =====");
173
      dbg_uart_wr(BRK2_STAT, 16'h0001);
174
      dbg_uart_rd(CPU_STAT);
175
      if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 5 =====");
176 202 olivier.gi
 
177 2 olivier.gi
      // RE-RUN
178
      dbg_uart_wr(CPU_CTL,    16'h0002);
179
      repeat(100) @(posedge mclk);
180
 
181
      // RE-CHECK
182 175 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h14))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
183 2 olivier.gi
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 =====");
184
      dbg_uart_rd(CPU_STAT);
185
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 =====");
186
      dbg_uart_rd(BRK2_STAT);
187
      if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 9 =====");
188
      dbg_uart_wr(BRK2_STAT, 16'h0004);
189
      dbg_uart_rd(CPU_STAT);
190
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 10 =====");
191
 
192
      // RE-RUN
193
      dbg_uart_wr(CPU_CTL,    16'h0002);
194
      repeat(100) @(posedge mclk);
195
 
196
      // CHECK
197 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h18))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 =====");
198 175 olivier.gi
      if (mem200 !== 16'h0001)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
199 2 olivier.gi
      dbg_uart_rd(CPU_STAT);
200
      if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 =====");
201
      dbg_uart_rd(BRK2_STAT);
202
      if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 14 =====");
203
      dbg_uart_wr(BRK2_STAT, 16'h0001);
204
      dbg_uart_rd(CPU_STAT);
205
      if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 15 =====");
206 202 olivier.gi
 
207
 
208 2 olivier.gi
      // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE
209
      //-----------------------------------------------------------------------------
210
 
211
      // RESET, BREAK & CLEAR STATUS
212
      dbg_uart_wr(CPU_CTL,    16'h0060);
213
      dbg_uart_wr(CPU_CTL,    16'h0020);
214
      dbg_uart_wr(BRK2_STAT,  16'h00ff);
215
      dbg_uart_wr(CPU_STAT,   16'h00ff);
216
 
217 202 olivier.gi
 
218 2 olivier.gi
      // CONFIGURE BREAKPOINT (ENABLED) & RUN
219 111 olivier.gi
      dbg_uart_wr(BRK2_ADDR0, (`PER_SIZE+16'h0004));
220
      dbg_uart_wr(BRK2_ADDR1, (`PER_SIZE+16'h0008));
221 2 olivier.gi
      dbg_uart_wr(BRK2_CTL,   16'h0006);
222
      dbg_uart_wr(CPU_CTL,    16'h0002);
223
      repeat(100) @(posedge mclk);
224
 
225
      // CHECK
226 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h3a))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 1 =====");
227 2 olivier.gi
      if (mem200 !== 16'h0000)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 2 =====");
228
      dbg_uart_rd(CPU_STAT);
229
      if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 3 =====");
230
      dbg_uart_rd(BRK2_STAT);
231
      if (dbg_uart_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 4 =====");
232
      dbg_uart_wr(BRK2_STAT, 16'h0002);
233
      dbg_uart_rd(CPU_STAT);
234
      if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - WRITE: test 5 =====");
235 202 olivier.gi
 
236 2 olivier.gi
      // RE-RUN
237
      dbg_uart_wr(CPU_CTL,    16'h0002);
238
      repeat(100) @(posedge mclk);
239
 
240
      // RE-CHECK
241 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h44))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 6 =====");
242 2 olivier.gi
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 7 =====");
243
      dbg_uart_rd(CPU_STAT);
244
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 8 =====");
245
      dbg_uart_rd(BRK2_STAT);
246
      if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 9 =====");
247
      dbg_uart_wr(BRK2_STAT, 16'h0008);
248
      dbg_uart_rd(CPU_STAT);
249
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 10 =====");
250
 
251
      // RE-RUN
252
      dbg_uart_wr(CPU_CTL,    16'h0002);
253
      repeat(100) @(posedge mclk);
254
 
255
      // RE-CHECK
256 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h0c))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 11 =====");
257 2 olivier.gi
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 12 =====");
258
      dbg_uart_rd(CPU_STAT);
259
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 13 =====");
260
      dbg_uart_rd(BRK2_STAT);
261
      if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 14 =====");
262
      dbg_uart_wr(BRK2_STAT, 16'h0002);
263
      dbg_uart_rd(CPU_STAT);
264
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 15 =====");
265
 
266
      // RE-RUN
267
      dbg_uart_wr(CPU_CTL,    16'h0002);
268
      repeat(100) @(posedge mclk);
269
 
270
      // RE-CHECK
271 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h14))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 16 =====");
272 2 olivier.gi
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 17 =====");
273
      dbg_uart_rd(CPU_STAT);
274
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 18 =====");
275
      dbg_uart_rd(BRK2_STAT);
276
      if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 19 =====");
277
      dbg_uart_wr(BRK2_STAT, 16'h0008);
278
      dbg_uart_rd(CPU_STAT);
279
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 20 =====");
280
 
281
      // RE-RUN
282
      dbg_uart_wr(CPU_CTL,    16'h0002);
283
      repeat(100) @(posedge mclk);
284
 
285
      // RE-CHECK
286 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h0c))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 21 =====");
287 2 olivier.gi
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 22 =====");
288
      dbg_uart_rd(CPU_STAT);
289
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 23 =====");
290
      dbg_uart_rd(BRK2_STAT);
291
      if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 24 =====");
292
      dbg_uart_wr(BRK2_STAT, 16'h0002);
293
      dbg_uart_rd(CPU_STAT);
294
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - WRITE: test 25 =====");
295
 
296 202 olivier.gi
 
297 2 olivier.gi
      // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE
298
      //----------------------------------------------------------------------------------
299
 
300
      // RESET, BREAK & CLEAR STATUS
301
      dbg_uart_wr(CPU_CTL,    16'h0060);
302
      dbg_uart_wr(CPU_CTL,    16'h0020);
303
      dbg_uart_wr(BRK2_STAT,  16'h00ff);
304
      dbg_uart_wr(CPU_STAT,   16'h00ff);
305
 
306 202 olivier.gi
 
307 2 olivier.gi
      // CONFIGURE BREAKPOINT (ENABLED) & RUN
308 111 olivier.gi
      dbg_uart_wr(BRK2_ADDR0, (`PER_SIZE+16'h0004));
309
      dbg_uart_wr(BRK2_ADDR1, (`PER_SIZE+16'h0008));
310 2 olivier.gi
      dbg_uart_wr(BRK2_CTL,   16'h0007);
311
      dbg_uart_wr(CPU_CTL,    16'h0002);
312
      repeat(100) @(posedge mclk);
313
 
314
      // CHECK
315 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h3a))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 1 =====");
316 2 olivier.gi
      if (mem200 !== 16'h0000)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 2 =====");
317
      dbg_uart_rd(CPU_STAT);
318
      if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 3 =====");
319
      dbg_uart_rd(BRK2_STAT);
320
      if (dbg_uart_buf !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 4 =====");
321
      dbg_uart_wr(BRK2_STAT, 16'h0002);
322
      dbg_uart_rd(CPU_STAT);
323
      if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 5 =====");
324 202 olivier.gi
 
325 2 olivier.gi
      // RE-RUN
326
      dbg_uart_wr(CPU_CTL,    16'h0002);
327
      repeat(100) @(posedge mclk);
328
 
329
      // RE-CHECK
330 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h44))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 6 =====");
331 2 olivier.gi
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 7 =====");
332
      dbg_uart_rd(CPU_STAT);
333
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 8 =====");
334
      dbg_uart_rd(BRK2_STAT);
335
      if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 9 =====");
336
      dbg_uart_wr(BRK2_STAT, 16'h0008);
337
      dbg_uart_rd(CPU_STAT);
338
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 10 =====");
339
 
340
      // RE-RUN
341
      dbg_uart_wr(CPU_CTL,    16'h0002);
342
      repeat(100) @(posedge mclk);
343
 
344
      // RE-CHECK
345 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h0c))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 11 =====");
346 2 olivier.gi
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 12 =====");
347
      dbg_uart_rd(CPU_STAT);
348
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 =====");
349
      dbg_uart_rd(BRK2_STAT);
350 175 olivier.gi
      if (dbg_uart_buf !== 16'h0003) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
351
      dbg_uart_wr(BRK2_STAT, 16'h0003);
352 2 olivier.gi
      dbg_uart_rd(CPU_STAT);
353
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 =====");
354
 
355
      // RE-RUN
356
      dbg_uart_wr(CPU_CTL,    16'h0002);
357
      repeat(100) @(posedge mclk);
358
 
359
      // RE-CHECK
360 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h14))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 16 =====");
361 2 olivier.gi
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 17 =====");
362
      dbg_uart_rd(CPU_STAT);
363
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 =====");
364
      dbg_uart_rd(BRK2_STAT);
365 175 olivier.gi
      if (dbg_uart_buf !== 16'h000C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
366
      dbg_uart_wr(BRK2_STAT, 16'h000C);
367 2 olivier.gi
      dbg_uart_rd(CPU_STAT);
368
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 =====");
369
 
370
      // RE-RUN
371
      dbg_uart_wr(CPU_CTL,    16'h0002);
372
      repeat(100) @(posedge mclk);
373
 
374
      // CHECK
375 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h18))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 21 =====");
376 2 olivier.gi
      if (mem200 !== 16'h0001)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 22 =====");
377
      dbg_uart_rd(CPU_STAT);
378
      if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 23 =====");
379
      dbg_uart_rd(BRK2_STAT);
380
      if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 24 =====");
381
      dbg_uart_wr(BRK2_STAT, 16'h0001);
382
      dbg_uart_rd(CPU_STAT);
383
      if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ/WRITE: test 25 =====");
384 202 olivier.gi
 
385 2 olivier.gi
      // RE-RUN
386
      dbg_uart_wr(CPU_CTL,    16'h0002);
387
      repeat(100) @(posedge mclk);
388
 
389
      // RE-CHECK
390 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h1C))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 26 =====");
391 2 olivier.gi
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 27 =====");
392
      dbg_uart_rd(CPU_STAT);
393
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 28 =====");
394
      dbg_uart_rd(BRK2_STAT);
395
      if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 29 =====");
396
      dbg_uart_wr(BRK2_STAT, 16'h0004);
397
      dbg_uart_rd(CPU_STAT);
398
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 30 =====");
399
 
400 202 olivier.gi
 
401 2 olivier.gi
      // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ
402
      //----------------------------------------------------------------------------
403 58 olivier.gi
      if (`HWBRK_RANGE)
404
        begin
405 2 olivier.gi
 
406
      // RESET, BREAK & CLEAR STATUS
407
      dbg_uart_wr(CPU_CTL,    16'h0060);
408
      dbg_uart_wr(CPU_CTL,    16'h0020);
409
      dbg_uart_wr(BRK2_STAT,  16'h00ff);
410
      dbg_uart_wr(CPU_STAT,   16'h00ff);
411
 
412 202 olivier.gi
 
413 2 olivier.gi
      // CONFIGURE BREAKPOINT (ENABLED) & RUN
414 111 olivier.gi
      dbg_uart_wr(BRK2_ADDR0, (`PER_SIZE+16'h0001));
415
      dbg_uart_wr(BRK2_ADDR1, (`PER_SIZE+16'h0005));
416 2 olivier.gi
      dbg_uart_wr(BRK2_CTL,   16'h0015);
417
      dbg_uart_wr(CPU_CTL,    16'h0002);
418
      repeat(100) @(posedge mclk);
419
 
420
      // CHECK
421 175 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h08))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
422
      if (mem200 !== 16'h0000)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
423 2 olivier.gi
      dbg_uart_rd(CPU_STAT);
424
      if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 =====");
425
      dbg_uart_rd(BRK2_STAT);
426
      if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 4 =====");
427
      dbg_uart_wr(BRK2_STAT, 16'h0010);
428
      dbg_uart_rd(CPU_STAT);
429
      if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 5 =====");
430 202 olivier.gi
 
431 2 olivier.gi
      // RE-RUN
432
      dbg_uart_wr(CPU_CTL,    16'h0002);
433
      repeat(100) @(posedge mclk);
434
 
435
      // RE-CHECK
436 175 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h0C))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
437
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
438 2 olivier.gi
      dbg_uart_rd(CPU_STAT);
439
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 =====");
440
      dbg_uart_rd(BRK2_STAT);
441
      if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 9 =====");
442
      dbg_uart_wr(BRK2_STAT, 16'h0010);
443
      dbg_uart_rd(CPU_STAT);
444
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 10 =====");
445 58 olivier.gi
        end
446 2 olivier.gi
 
447 202 olivier.gi
 
448 58 olivier.gi
      // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE
449 2 olivier.gi
      //-----------------------------------------------------------------------------
450 58 olivier.gi
      if (`HWBRK_RANGE)
451
        begin
452 2 olivier.gi
 
453 58 olivier.gi
 
454 2 olivier.gi
      // RESET, BREAK & CLEAR STATUS
455
      dbg_uart_wr(CPU_CTL,    16'h0060);
456
      dbg_uart_wr(CPU_CTL,    16'h0020);
457
      dbg_uart_wr(BRK2_STAT,  16'h00ff);
458
      dbg_uart_wr(CPU_STAT,   16'h00ff);
459
 
460 202 olivier.gi
 
461 2 olivier.gi
      // CONFIGURE BREAKPOINT (ENABLED) & RUN
462 111 olivier.gi
      dbg_uart_wr(BRK2_ADDR0, (`PER_SIZE+16'h0001));
463
      dbg_uart_wr(BRK2_ADDR1, (`PER_SIZE+16'h0005));
464 2 olivier.gi
      dbg_uart_wr(BRK2_CTL,   16'h0016);
465
      dbg_uart_wr(CPU_CTL,    16'h0002);
466
      repeat(100) @(posedge mclk);
467
 
468
      // CHECK
469 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h36))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 1 =====");
470 58 olivier.gi
      if (mem200 !== 16'h0000)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 2 =====");
471 2 olivier.gi
      dbg_uart_rd(CPU_STAT);
472 58 olivier.gi
      if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 3 =====");
473 2 olivier.gi
      dbg_uart_rd(BRK2_STAT);
474 58 olivier.gi
      if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 4 =====");
475 2 olivier.gi
      dbg_uart_wr(BRK2_STAT, 16'h0020);
476
      dbg_uart_rd(CPU_STAT);
477 58 olivier.gi
      if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - WRITE: test 5 =====");
478 202 olivier.gi
 
479 2 olivier.gi
      // RE-RUN
480
      dbg_uart_wr(CPU_CTL,    16'h0002);
481
      repeat(100) @(posedge mclk);
482
 
483
      // RE-CHECK
484 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h3a))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 6 =====");
485 58 olivier.gi
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 7 =====");
486 2 olivier.gi
      dbg_uart_rd(CPU_STAT);
487 58 olivier.gi
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 8 =====");
488 2 olivier.gi
      dbg_uart_rd(BRK2_STAT);
489 58 olivier.gi
      if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 9 =====");
490 2 olivier.gi
      dbg_uart_wr(BRK2_STAT, 16'h0020);
491
      dbg_uart_rd(CPU_STAT);
492 58 olivier.gi
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 10 =====");
493 2 olivier.gi
 
494
      // RE-RUN
495
      dbg_uart_wr(CPU_CTL,    16'h0002);
496
      repeat(100) @(posedge mclk);
497
 
498
      // RE-CHECK
499 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h08))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 11 =====");
500 58 olivier.gi
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 12 =====");
501 2 olivier.gi
      dbg_uart_rd(CPU_STAT);
502 58 olivier.gi
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 13 =====");
503 2 olivier.gi
      dbg_uart_rd(BRK2_STAT);
504 58 olivier.gi
      if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 14 =====");
505 2 olivier.gi
      dbg_uart_wr(BRK2_STAT, 16'h0020);
506
      dbg_uart_rd(CPU_STAT);
507 58 olivier.gi
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 15 =====");
508 2 olivier.gi
 
509
      // RE-RUN
510
      dbg_uart_wr(CPU_CTL,    16'h0002);
511
      repeat(100) @(posedge mclk);
512
 
513
      // RE-CHECK
514 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h0C))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 16 =====");
515 58 olivier.gi
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 17 =====");
516 2 olivier.gi
      dbg_uart_rd(CPU_STAT);
517 58 olivier.gi
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 18 =====");
518 2 olivier.gi
      dbg_uart_rd(BRK2_STAT);
519 58 olivier.gi
      if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 19 =====");
520 2 olivier.gi
      dbg_uart_wr(BRK2_STAT, 16'h0020);
521
      dbg_uart_rd(CPU_STAT);
522 58 olivier.gi
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 20 =====");
523 2 olivier.gi
 
524
      // RE-RUN
525
      dbg_uart_wr(CPU_CTL,    16'h0002);
526
      repeat(100) @(posedge mclk);
527
 
528
      // RE-CHECK
529 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h08))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 21 =====");
530 58 olivier.gi
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 22 =====");
531 2 olivier.gi
      dbg_uart_rd(CPU_STAT);
532 58 olivier.gi
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 23 =====");
533 2 olivier.gi
      dbg_uart_rd(BRK2_STAT);
534 58 olivier.gi
      if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 24 =====");
535 2 olivier.gi
      dbg_uart_wr(BRK2_STAT, 16'h0020);
536
      dbg_uart_rd(CPU_STAT);
537 58 olivier.gi
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - WRITE: test 25 =====");
538
        end
539 2 olivier.gi
 
540 202 olivier.gi
 
541 2 olivier.gi
      // HARDWARE BREAKPOINTS: DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE
542
      //----------------------------------------------------------------------------------
543 58 olivier.gi
      if (`HWBRK_RANGE)
544
        begin
545 2 olivier.gi
 
546
      // RESET, BREAK & CLEAR STATUS
547
      dbg_uart_wr(CPU_CTL,    16'h0060);
548
      dbg_uart_wr(CPU_CTL,    16'h0020);
549
      dbg_uart_wr(BRK2_STAT,  16'h00ff);
550
      dbg_uart_wr(CPU_STAT,   16'h00ff);
551
 
552 202 olivier.gi
 
553 2 olivier.gi
      // CONFIGURE BREAKPOINT (ENABLED) & RUN
554 111 olivier.gi
      dbg_uart_wr(BRK2_ADDR0, (`PER_SIZE+16'h0001));
555
      dbg_uart_wr(BRK2_ADDR1, (`PER_SIZE+16'h0005));
556 2 olivier.gi
      dbg_uart_wr(BRK2_CTL,   16'h0017);
557
      dbg_uart_wr(CPU_CTL,    16'h0002);
558
      repeat(100) @(posedge mclk);
559
 
560
      // CHECK
561 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h36))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 1 =====");
562 2 olivier.gi
      if (mem200 !== 16'h0000)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 2 =====");
563
      dbg_uart_rd(CPU_STAT);
564
      if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 3 =====");
565
      dbg_uart_rd(BRK2_STAT);
566
      if (dbg_uart_buf !== 16'h0020) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 4 =====");
567
      dbg_uart_wr(BRK2_STAT, 16'h0020);
568
      dbg_uart_rd(CPU_STAT);
569
      if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 5 =====");
570 202 olivier.gi
 
571 2 olivier.gi
      // RE-RUN
572
      dbg_uart_wr(CPU_CTL,    16'h0002);
573
      repeat(100) @(posedge mclk);
574
 
575
      // RE-CHECK
576 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h3a))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 6 =====");
577 2 olivier.gi
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 7 =====");
578
      dbg_uart_rd(CPU_STAT);
579
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 8 =====");
580
      dbg_uart_rd(BRK2_STAT);
581
      if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 9 =====");
582
      dbg_uart_wr(BRK2_STAT, 16'h0020);
583
      dbg_uart_rd(CPU_STAT);
584
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 10 =====");
585
 
586
      // RE-RUN
587
      dbg_uart_wr(CPU_CTL,    16'h0002);
588
      repeat(100) @(posedge mclk);
589
 
590
      // RE-CHECK
591 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h08))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 11 =====");
592 2 olivier.gi
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 12 =====");
593
      dbg_uart_rd(CPU_STAT);
594
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 =====");
595
      dbg_uart_rd(BRK2_STAT);
596 175 olivier.gi
      if (dbg_uart_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
597
      dbg_uart_wr(BRK2_STAT, 16'h0030);
598 2 olivier.gi
      dbg_uart_rd(CPU_STAT);
599
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 =====");
600
 
601
      // RE-RUN
602
      dbg_uart_wr(CPU_CTL,    16'h0002);
603
      repeat(100) @(posedge mclk);
604
 
605
      // RE-CHECK
606 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h0C))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 16 =====");
607 2 olivier.gi
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 17 =====");
608
      dbg_uart_rd(CPU_STAT);
609
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 =====");
610
      dbg_uart_rd(BRK2_STAT);
611 175 olivier.gi
      if (dbg_uart_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
612
      dbg_uart_wr(BRK2_STAT, 16'h0030);
613 2 olivier.gi
      dbg_uart_rd(CPU_STAT);
614
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 =====");
615
 
616
      // RE-RUN
617
      dbg_uart_wr(CPU_CTL,    16'h0002);
618
      repeat(100) @(posedge mclk);
619
 
620
      // CHECK
621 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h18))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 21 =====");
622 2 olivier.gi
      if (mem200 !== 16'h0001)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 22 =====");
623
      dbg_uart_rd(CPU_STAT);
624
      if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 23 =====");
625
      dbg_uart_rd(BRK2_STAT);
626
      if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 24 =====");
627
      dbg_uart_wr(BRK2_STAT, 16'h0010);
628
      dbg_uart_rd(CPU_STAT);
629
      if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ/WRITE: test 25 =====");
630 202 olivier.gi
 
631 2 olivier.gi
      // RE-RUN
632
      dbg_uart_wr(CPU_CTL,    16'h0002);
633
      repeat(100) @(posedge mclk);
634
 
635
      // RE-CHECK
636 86 olivier.gi
      if (r0 !== ('h10000-`PMEM_SIZE+'h08))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 26 =====");
637 2 olivier.gi
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 27 =====");
638
      dbg_uart_rd(CPU_STAT);
639
      if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 =====");
640
      dbg_uart_rd(BRK2_STAT);
641 175 olivier.gi
      if (dbg_uart_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
642
      dbg_uart_wr(BRK2_STAT, 16'h0030);
643 2 olivier.gi
      dbg_uart_rd(CPU_STAT);
644
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 =====");
645
 
646 58 olivier.gi
        end
647 2 olivier.gi
 
648
       // RE-RUN UNTIL END OF PATTERN
649
      dbg_uart_wr(BRK2_CTL,   16'h0000);
650
      dbg_uart_wr(CPU_CTL,    16'h0002);
651
      repeat(100) @(posedge mclk);
652
 
653 202 olivier.gi
 
654 2 olivier.gi
      stimulus_done = 1;
655 111 olivier.gi
`else
656
 
657 202 olivier.gi
       tb_skip_finish("|   (hardware breakpoint unit 2 not included)   |");
658 111 olivier.gi
`endif
659
`else
660 202 olivier.gi
       tb_skip_finish("|   (serial debug interface UART not included)  |");
661 154 olivier.gi
`endif
662
`else
663 202 olivier.gi
       tb_skip_finish("|      (serial debug interface not included)    |");
664 111 olivier.gi
`endif
665 2 olivier.gi
   end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.