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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart_onoff.v] - Blame information for rev 219

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1 106 olivier.gi
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                            DEBUG INTERFACE                                */
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/*---------------------------------------------------------------------------*/
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/* Test the debug interface:                                                 */
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/*                           - CPU Control features.                         */
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/*                                                                           */
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/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 95 $                                                                */
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/* $LastChangedBy: olivier.girard $                                          */
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/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $          */
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/*===========================================================================*/
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38
 
39 111 olivier.gi
   integer test_nr;
40 106 olivier.gi
   integer test_var;
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42 202 olivier.gi
 
43 106 olivier.gi
initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
48 111 olivier.gi
`ifdef DBG_EN
49 154 olivier.gi
`ifdef DBG_UART
50 180 olivier.gi
  `ifdef ASIC_CLOCKING
51 202 olivier.gi
      tb_skip_finish("|   (this test is not supported in ASIC mode)   |");
52 134 olivier.gi
  `else
53 111 olivier.gi
      test_nr = 0;
54 106 olivier.gi
      #1 dbg_en = 0;
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      repeat(30) @(posedge mclk);
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      stimulus_done = 0;
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58
      // Make sure the CPU always starts executing when the
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      // debug interface is disabled during POR.
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      //--------------------------------------------------------
61 111 olivier.gi
      dbg_en  = 0;
62
      test_nr = 1;
63 106 olivier.gi
 
64
      repeat(300) @(posedge mclk);
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      if (r14 === 16'h0000)       tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 =====");
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      test_var = r14;
67 202 olivier.gi
 
68
 
69 106 olivier.gi
      // Make sure that enabling the debug interface after the POR
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      // don't stop the cpu
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      //--------------------------------------------------------
72 111 olivier.gi
      dbg_en  = 1;
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      test_nr = 2;
74 202 olivier.gi
 
75 106 olivier.gi
      repeat(300) @(posedge mclk);
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      if (r14 === test_var[15:0]) tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 2 =====");
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78 202 olivier.gi
 
79 106 olivier.gi
      // Create POR with debug enable and observe the
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      // behavior depending on the DBG_RST_BRK_EN define
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      //--------------------------------------------------------
82 111 olivier.gi
      dbg_en  = 1;
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      test_nr = 3;
84 202 olivier.gi
 
85 106 olivier.gi
      @(posedge mclk); // Generate POR
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      reset_n = 1'b0;
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      @(posedge mclk);
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      reset_n = 1'b1;
89 202 olivier.gi
 
90 106 olivier.gi
      repeat(300) @(posedge mclk);
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`ifdef DBG_RST_BRK_EN
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      if (r14 !== 16'h0000)       tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 =====");
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`else
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      if (r14 === 16'h0000)       tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 =====");
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`endif
96
 
97
      // Send uart synchronization frame
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      dbg_uart_tx(DBG_SYNC);
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100
      // Check CPU_CTL reset value
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      dbg_uart_rd(CPU_CTL);
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`ifdef DBG_RST_BRK_EN
103 134 olivier.gi
      if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value -  test 4 =====");
104 106 olivier.gi
`else
105 202 olivier.gi
      if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value -  test 4 =====");
106 106 olivier.gi
`endif
107
 
108
 
109
      // Make sure that DBG_EN resets the debug interface
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      //--------------------------------------------------------
111 111 olivier.gi
      test_nr = 4;
112 106 olivier.gi
 
113
      // Let the CPU run
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      dbg_uart_wr(CPU_CTL,  16'h0002);
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116
      repeat(300) @(posedge mclk);
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      dbg_uart_wr(CPU_CTL,   16'h0000);
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      dbg_uart_wr(MEM_DATA,  16'haa55);
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      dbg_uart_rd(CPU_CTL);
120
      if (dbg_uart_buf !== 16'h0000)  tb_error("====== CPU_CTL write access failed  - test 5 =====");
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      dbg_uart_rd(MEM_DATA);
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      if (dbg_uart_buf !== 16'haa55)  tb_error("====== MEM_DATA write access failed - test 6 =====");
123
 
124 202 olivier.gi
 
125 106 olivier.gi
      test_var = r14;  // Backup the current register value
126
 
127 202 olivier.gi
 
128 106 olivier.gi
      @(posedge mclk); // Resets the debug interface
129
      dbg_en = 1'b0;
130
      repeat(2) @(posedge mclk);
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      dbg_en = 1'b1;
132
 
133
      // Make sure that the register was not reseted
134
      if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN -  test 7 =====");
135 202 olivier.gi
      repeat(2) @(posedge mclk);
136
 
137 106 olivier.gi
      // Send uart synchronization frame
138
      dbg_uart_tx(DBG_SYNC);
139
 
140
      // Check CPU_CTL reset value
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      dbg_uart_rd(CPU_CTL);
142
`ifdef DBG_RST_BRK_EN
143 134 olivier.gi
      if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value -  test 8 =====");
144 106 olivier.gi
`else
145 202 olivier.gi
      if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value -  test 8 =====");
146 106 olivier.gi
`endif
147
      dbg_uart_rd(MEM_DATA);
148
      if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
149
 
150
 
151
      // Make sure that RESET_N resets the debug interface
152
      //--------------------------------------------------------
153 111 olivier.gi
      test_nr = 5;
154 106 olivier.gi
 
155
      // Let the CPU run
156
      dbg_uart_wr(CPU_CTL,  16'h0002);
157
 
158
      repeat(300) @(posedge mclk);
159
      dbg_uart_wr(CPU_CTL,   16'h0000);
160
      dbg_uart_wr(MEM_DATA,  16'haa55);
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      dbg_uart_rd(CPU_CTL);
162
      if (dbg_uart_buf !== 16'h0000)  tb_error("====== CPU_CTL write access failed  - test 10 =====");
163
      dbg_uart_rd(MEM_DATA);
164
      if (dbg_uart_buf !== 16'haa55)  tb_error("====== MEM_DATA write access failed - test 11 =====");
165
 
166 111 olivier.gi
      test_nr = 6;
167 106 olivier.gi
 
168
      @(posedge mclk); // Generates POR
169
      reset_n = 1'b0;
170
      repeat(2) @(posedge mclk);
171
      reset_n = 1'b1;
172
 
173
      // Make sure that the register was reseted
174
      if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N -  test 12 =====");
175
      repeat(2) @(posedge mclk);
176 202 olivier.gi
 
177 106 olivier.gi
      // Send uart synchronization frame
178
      dbg_uart_tx(DBG_SYNC);
179
 
180 111 olivier.gi
      test_nr = 7;
181
 
182 106 olivier.gi
      // Check CPU_CTL reset value
183
      dbg_uart_rd(CPU_CTL);
184
`ifdef DBG_RST_BRK_EN
185 134 olivier.gi
      if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value -  test 8 =====");
186 106 olivier.gi
`else
187 202 olivier.gi
      if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value -  test 8 =====");
188 106 olivier.gi
`endif
189
      dbg_uart_rd(MEM_DATA);
190
      if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
191
 
192 202 olivier.gi
 
193 106 olivier.gi
      // Let the CPU run
194
      dbg_uart_wr(CPU_CTL,  16'h0002);
195
 
196 111 olivier.gi
      test_nr = 8;
197
 
198 106 olivier.gi
      // Generate IRQ to terminate the test pattern
199 192 olivier.gi
      irq[`IRQ_NR-15] = 1'b1;
200 106 olivier.gi
      @(r13);
201 192 olivier.gi
      irq[`IRQ_NR-15] = 1'b0;
202 202 olivier.gi
 
203 106 olivier.gi
      stimulus_done = 1;
204 134 olivier.gi
 
205
  `endif
206 111 olivier.gi
`else
207
 
208 202 olivier.gi
       tb_skip_finish("|   (serial debug interface UART not included)  |");
209 154 olivier.gi
`endif
210
`else
211 202 olivier.gi
       tb_skip_finish("|      (serial debug interface not included)    |");
212 111 olivier.gi
`endif
213 106 olivier.gi
   end

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