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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart_onoff_asic.v] - Blame information for rev 202

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            DEBUG INTERFACE                                */
/*---------------------------------------------------------------------------*/
/* Test the debug interface:                                                 */
/*                           - CPU Control features.                         */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 95 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $          */
/*===========================================================================*/
 
 
   integer test_nr;
   integer test_var;
 
   integer dco_clk_counter;
   always @ (negedge dco_clk)
     dco_clk_counter <=  dco_clk_counter+1;
 
   integer dbg_clk_counter;
   always @ (negedge dbg_clk)
     dbg_clk_counter <=  dbg_clk_counter+1;
 
 
initial
   begin
      $display(" ===============================================");
      $display("|                 START SIMULATION              |");
      $display(" ===============================================");
`ifdef DBG_EN
`ifdef DBG_UART
  `ifdef ASIC_CLOCKING
      test_nr = 0;
      #1 dbg_en = 0;
      repeat(30) @(posedge dco_clk);
      stimulus_done = 0;
 
      // Make sure the CPU always starts executing when the
      // debug interface is disabled during POR.
      // Also make sure that the debug interface clock is stopped
      // and that it is under reset
      //--------------------------------------------------------
      dbg_en  = 0;
      test_nr = 1;
 
      @(negedge dco_clk) dbg_clk_counter = 0;
 
      repeat(300) @(posedge dco_clk);
      if (r14 === 16'h0000)         tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 =====");
      if (dbg_clk_counter !== 0)    tb_error("====== DBG_CLK is not stopped (test 1) =====");
      if (dbg_rst          == 1'b0) tb_error("====== DBG_RST signal is not active (test 3) =====");
      test_var = r14;
 
 
      // Make sure that enabling the debug interface after the POR
      // don't stop the cpu
      // Also make sure that the debug interface clock is running
      // and that its reset is released
      //--------------------------------------------------------
      dbg_en  = 1;
      test_nr = 2;
 
      @(negedge dco_clk) dbg_clk_counter = 0;
 
      repeat(300) @(posedge dco_clk);
      if (r14 === test_var[15:0])   tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 4 =====");
      if (dbg_clk_counter  == 0)    tb_error("====== DBG_CLK is not running (test 5) =====");
      if (dbg_rst         !== 1'b0) tb_error("====== DBG_RST signal is active (test 6) =====");
 
 
      // Make sure that disabling the CPU with debug enabled
      // will stop the CPU
      // Also make sure that the debug interface clock is stopped
      // and that it is NOT under reset
      //--------------------------------------------------------
      cpu_en  = 0;
      dbg_en  = 1;
      test_nr = 3;
 
      #(6*50);
      test_var = r14;
      dbg_clk_counter = 0;
 
      #(300*50);
      if (r14 !== test_var[15:0])   tb_error("====== CPU is not stopped (test 7) =====");
      if (dbg_clk_counter !== 0)    tb_error("====== DBG_CLK is not running (test 8) =====");
      if (dbg_rst         !== 1'b0) tb_error("====== DBG_RST signal is active (test 9) =====");
 
      cpu_en  = 1;
      repeat(6) @(negedge dco_clk);
 
 
      // Create POR with debug enable and observe the
      // behavior depending on the DBG_RST_BRK_EN define
      //--------------------------------------------------------
      dbg_en  = 1;
      test_nr = 4;
 
      @(posedge dco_clk); // Generate POR
      reset_n = 1'b0;
      @(posedge dco_clk);
      reset_n = 1'b1;
 
      repeat(300) @(posedge dco_clk);
  `ifdef DBG_RST_BRK_EN
      if (r14 !== 16'h0000)       tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 =====");
  `else
      if (r14 === 16'h0000)       tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 =====");
  `endif
 
      // Send uart synchronization frame
      dbg_uart_tx(DBG_SYNC);
 
      // Check CPU_CTL reset value
      dbg_uart_rd(CPU_CTL);
  `ifdef DBG_RST_BRK_EN
      if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value -  test 4 =====");
  `else
      if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value -  test 4 =====");
  `endif
 
 
      // Make sure that DBG_EN resets the debug interface
      //--------------------------------------------------------
      test_nr = 5;
 
      // Let the CPU run
      dbg_uart_wr(CPU_CTL,  16'h0002);
 
      repeat(300) @(posedge dco_clk);
      dbg_uart_wr(CPU_CTL,   16'h0000);
      dbg_uart_wr(MEM_DATA,  16'haa55);
      dbg_uart_rd(CPU_CTL);
      if (dbg_uart_buf !== 16'h0000)  tb_error("====== CPU_CTL write access failed  - test 5 =====");
      dbg_uart_rd(MEM_DATA);
      if (dbg_uart_buf !== 16'haa55)  tb_error("====== MEM_DATA write access failed - test 6 =====");
 
 
      test_var = r14;  // Backup the current register value
 
 
      @(posedge dco_clk); // Resets the debug interface
      dbg_en = 1'b0;
      repeat(2) @(posedge dco_clk);
      dbg_en = 1'b1;
 
      // Make sure that the register was not reseted
      if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN -  test 7 =====");
      repeat(2) @(posedge dco_clk);
 
      // Send uart synchronization frame
      dbg_uart_tx(DBG_SYNC);
 
      // Check CPU_CTL reset value
      dbg_uart_rd(CPU_CTL);
  `ifdef DBG_RST_BRK_EN
      if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value -  test 8 =====");
  `else
      if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value -  test 8 =====");
  `endif
      dbg_uart_rd(MEM_DATA);
      if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
 
 
      // Make sure that RESET_N resets the debug interface
      //--------------------------------------------------------
      test_nr = 6;
 
      // Let the CPU run
      dbg_uart_wr(CPU_CTL,  16'h0002);
 
      repeat(300) @(posedge dco_clk);
      dbg_uart_wr(CPU_CTL,   16'h0000);
      dbg_uart_wr(MEM_DATA,  16'haa55);
      dbg_uart_rd(CPU_CTL);
      if (dbg_uart_buf !== 16'h0000)  tb_error("====== CPU_CTL write access failed  - test 10 =====");
      dbg_uart_rd(MEM_DATA);
      if (dbg_uart_buf !== 16'haa55)  tb_error("====== MEM_DATA write access failed - test 11 =====");
 
      test_nr = 7;
 
      @(posedge dco_clk); // Generates POR
      reset_n = 1'b0;
      repeat(2) @(posedge dco_clk);
      reset_n = 1'b1;
 
      // Make sure that the register was reseted
      if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N -  test 12 =====");
      repeat(2) @(posedge dco_clk);
 
      // Send uart synchronization frame
      dbg_uart_tx(DBG_SYNC);
 
      test_nr = 8;
 
      // Check CPU_CTL reset value
      dbg_uart_rd(CPU_CTL);
  `ifdef DBG_RST_BRK_EN
      if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value -  test 8 =====");
  `else
      if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value -  test 8 =====");
  `endif
      dbg_uart_rd(MEM_DATA);
      if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
 
 
      // Let the CPU run
      dbg_uart_wr(CPU_CTL,  16'h0002);
 
      test_nr = 9;
 
      // Generate IRQ to terminate the test pattern
      irq[`IRQ_NR-15] = 1'b1;
      @(r13);
      irq[`IRQ_NR-15] = 1'b0;
 
      stimulus_done = 1;
 
  `else
      tb_skip_finish("|   (this test is not supported in FPGA mode)   |");
  `endif
`else
      tb_skip_finish("|   (serial debug interface UART not included)  |");
`endif
`else
      tb_skip_finish("|      (serial debug interface not included)    |");
`endif
   end

Line No.	Rev	Author	Line
1	134	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* DEBUG INTERFACE */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the debug interface: */`
27			`/* - CPU Control features. */`
28			`/* */`
29			`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32			`/---------------------------------------------------------------------------/`
33			`/* $Rev: 95 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */`
36			`/===========================================================================/`
37
38
39			`integer test_nr;`
40			`integer test_var;`
41
42			`integer dco_clk_counter;`
43			`always @ (negedge dco_clk)`
44			`dco_clk_counter <= dco_clk_counter+1;`
45
46			`integer dbg_clk_counter;`
47			`always @ (negedge dbg_clk)`
48			`dbg_clk_counter <= dbg_clk_counter+1;`
49
50	202	olivier.gi
51	134	olivier.gi	`initial`
52			`begin`
53			`$display(" ===============================================");`
54			`$display("\| START SIMULATION \|");`
55			`$display(" ===============================================");`
56			`ifdef DBG_EN
57	154	olivier.gi	`ifdef DBG_UART
58	180	olivier.gi	`ifdef ASIC_CLOCKING
59	134	olivier.gi	`test_nr = 0;`
60			`#1 dbg_en = 0;`
61			`repeat(30) @(posedge dco_clk);`
62			`stimulus_done = 0;`
63
64			`// Make sure the CPU always starts executing when the`
65			`// debug interface is disabled during POR.`
66			`// Also make sure that the debug interface clock is stopped`
67			`// and that it is under reset`
68			`//--------------------------------------------------------`
69			`dbg_en = 0;`
70			`test_nr = 1;`
71
72			`@(negedge dco_clk) dbg_clk_counter = 0;`
73
74			`repeat(300) @(posedge dco_clk);`
75			`if (r14 === 16'h0000) tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 =====");`
76			`if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not stopped (test 1) =====");`
77			`if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 3) =====");`
78			`test_var = r14;`
79	202	olivier.gi
80
81	134	olivier.gi	`// Make sure that enabling the debug interface after the POR`
82			`// don't stop the cpu`
83			`// Also make sure that the debug interface clock is running`
84			`// and that its reset is released`
85			`//--------------------------------------------------------`
86			`dbg_en = 1;`
87			`test_nr = 2;`
88	202	olivier.gi
89	134	olivier.gi	`@(negedge dco_clk) dbg_clk_counter = 0;`
90
91			`repeat(300) @(posedge dco_clk);`
92			`if (r14 === test_var[15:0]) tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 4 =====");`
93			`if (dbg_clk_counter == 0) tb_error("====== DBG_CLK is not running (test 5) =====");`
94			`if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 6) =====");`
95
96	202	olivier.gi
97	134	olivier.gi	`// Make sure that disabling the CPU with debug enabled`
98			`// will stop the CPU`
99			`// Also make sure that the debug interface clock is stopped`
100			`// and that it is NOT under reset`
101			`//--------------------------------------------------------`
102			`cpu_en = 0;`
103			`dbg_en = 1;`
104			`test_nr = 3;`
105	202	olivier.gi
106	134	olivier.gi	`#(6*50);`
107			`test_var = r14;`
108			`dbg_clk_counter = 0;`
109
110			`#(300*50);`
111			`if (r14 !== test_var[15:0]) tb_error("====== CPU is not stopped (test 7) =====");`
112			`if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not running (test 8) =====");`
113			`if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 9) =====");`
114
115			`cpu_en = 1;`
116			`repeat(6) @(negedge dco_clk);`
117
118	202	olivier.gi
119	134	olivier.gi	`// Create POR with debug enable and observe the`
120			`// behavior depending on the DBG_RST_BRK_EN define`
121			`//--------------------------------------------------------`
122			`dbg_en = 1;`
123			`test_nr = 4;`
124	202	olivier.gi
125	134	olivier.gi	`@(posedge dco_clk); // Generate POR`
126			`reset_n = 1'b0;`
127			`@(posedge dco_clk);`
128			`reset_n = 1'b1;`
129	202	olivier.gi
130	134	olivier.gi	`repeat(300) @(posedge dco_clk);`
131			`ifdef DBG_RST_BRK_EN
132			`if (r14 !== 16'h0000) tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 =====");`
133			`else
134			`if (r14 === 16'h0000) tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 =====");`
135			`endif
136
137			`// Send uart synchronization frame`
138			`dbg_uart_tx(DBG_SYNC);`
139
140			`// Check CPU_CTL reset value`
141			`dbg_uart_rd(CPU_CTL);`
142			`ifdef DBG_RST_BRK_EN
143			`if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 4 =====");`
144			`else
145	202	olivier.gi	`if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 4 =====");`
146	134	olivier.gi	`endif
147
148
149			`// Make sure that DBG_EN resets the debug interface`
150			`//--------------------------------------------------------`
151			`test_nr = 5;`
152
153			`// Let the CPU run`
154			`dbg_uart_wr(CPU_CTL, 16'h0002);`
155
156			`repeat(300) @(posedge dco_clk);`
157			`dbg_uart_wr(CPU_CTL, 16'h0000);`
158			`dbg_uart_wr(MEM_DATA, 16'haa55);`
159			`dbg_uart_rd(CPU_CTL);`
160			`if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 5 =====");`
161			`dbg_uart_rd(MEM_DATA);`
162			`if (dbg_uart_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 6 =====");`
163
164	202	olivier.gi
165	134	olivier.gi	`test_var = r14; // Backup the current register value`
166
167	202	olivier.gi
168	134	olivier.gi	`@(posedge dco_clk); // Resets the debug interface`
169			`dbg_en = 1'b0;`
170			`repeat(2) @(posedge dco_clk);`
171			`dbg_en = 1'b1;`
172
173			`// Make sure that the register was not reseted`
174			`if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN - test 7 =====");`
175	202	olivier.gi	`repeat(2) @(posedge dco_clk);`
176
177	134	olivier.gi	`// Send uart synchronization frame`
178			`dbg_uart_tx(DBG_SYNC);`
179
180			`// Check CPU_CTL reset value`
181			`dbg_uart_rd(CPU_CTL);`
182			`ifdef DBG_RST_BRK_EN
183			`if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 =====");`
184			`else
185	202	olivier.gi	`if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 =====");`
186	134	olivier.gi	`endif
187			`dbg_uart_rd(MEM_DATA);`
188			`if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");`
189
190
191			`// Make sure that RESET_N resets the debug interface`
192			`//--------------------------------------------------------`
193			`test_nr = 6;`
194
195			`// Let the CPU run`
196			`dbg_uart_wr(CPU_CTL, 16'h0002);`
197
198			`repeat(300) @(posedge dco_clk);`
199			`dbg_uart_wr(CPU_CTL, 16'h0000);`
200			`dbg_uart_wr(MEM_DATA, 16'haa55);`
201			`dbg_uart_rd(CPU_CTL);`
202			`if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 10 =====");`
203			`dbg_uart_rd(MEM_DATA);`
204			`if (dbg_uart_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 11 =====");`
205
206			`test_nr = 7;`
207
208			`@(posedge dco_clk); // Generates POR`
209			`reset_n = 1'b0;`
210			`repeat(2) @(posedge dco_clk);`
211			`reset_n = 1'b1;`
212
213			`// Make sure that the register was reseted`
214			`if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N - test 12 =====");`
215			`repeat(2) @(posedge dco_clk);`
216	202	olivier.gi
217	134	olivier.gi	`// Send uart synchronization frame`
218			`dbg_uart_tx(DBG_SYNC);`
219
220			`test_nr = 8;`
221
222			`// Check CPU_CTL reset value`
223			`dbg_uart_rd(CPU_CTL);`
224			`ifdef DBG_RST_BRK_EN
225			`if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 =====");`
226			`else
227	202	olivier.gi	`if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 =====");`
228	134	olivier.gi	`endif
229			`dbg_uart_rd(MEM_DATA);`
230			`if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");`
231
232	202	olivier.gi
233	134	olivier.gi	`// Let the CPU run`
234			`dbg_uart_wr(CPU_CTL, 16'h0002);`
235
236			`test_nr = 9;`
237
238			`// Generate IRQ to terminate the test pattern`
239	200	olivier.gi	irq[`IRQ_NR-15] = 1'b1;
240	134	olivier.gi	`@(r13);`
241	200	olivier.gi	irq[`IRQ_NR-15] = 1'b0;
242	202	olivier.gi
243	134	olivier.gi	`stimulus_done = 1;`
244
245			`else
246	202	olivier.gi	`tb_skip_finish("\| (this test is not supported in FPGA mode) \|");`
247	134	olivier.gi	`endif
248			`else
249	202	olivier.gi	`tb_skip_finish("\| (serial debug interface UART not included) \|");`
250	154	olivier.gi	`endif
251			`else
252	202	olivier.gi	`tb_skip_finish("\| (serial debug interface not included) \|");`
253	134	olivier.gi	`endif
254			`end`

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart_onoff_asic.v] - Blame information for rev 202