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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart_rdwr.v] - Blame information for rev 202

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            DEBUG INTERFACE:  RD / WR                      */
/*---------------------------------------------------------------------------*/
/* Test the UART debug interface:                                            */
/*                        - Check RD/WR access to all adressable             */
/*                          debug registers.                                 */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 95 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $          */
/*===========================================================================*/
 
`define LONG_TIMEOUT
 
reg  [2:0] cpu_version;
reg        cpu_asic;
reg  [4:0] user_version;
reg  [6:0] per_space;
reg        mpy_info;
reg  [8:0] dmem_size;
reg  [5:0] pmem_size;
reg [31:0] dbg_id;
 
// Set oMSP parameters for later check
defparam dut.INST_NR  = 8'h12;
defparam dut.TOTAL_NR = 8'h34;
 
integer    ii;
 
 
initial
   begin
      $display(" ===============================================");
      $display("|                 START SIMULATION              |");
      $display(" ===============================================");
`ifdef DBG_EN
`ifdef DBG_UART
    #1 dbg_en = 1;
      repeat(30) @(posedge mclk);
      stimulus_done = 0;
 
      // SEND UART SYNCHRONIZATION FRAME
      dbg_uart_tx(DBG_SYNC);
 
      // STOP CPU
      dbg_uart_wr(CPU_CTL ,  16'h0001);
 
      // TEST READ/WR TO ALL DEBUG REGISTERS
      //--------------------------------------------------------
 
      cpu_version  =  `CPU_VERSION;
`ifdef ASIC
      cpu_asic     =  1'b1;
`else
      cpu_asic     =  1'b0;
`endif
      user_version =  `USER_VERSION;
      per_space    = (`PER_SIZE  >> 9);
`ifdef MULTIPLIER
      mpy_info     =  1'b1;
`else
      mpy_info     =  1'b0;
`endif
      dmem_size    = (`DMEM_SIZE >> 7);
      pmem_size    = (`PMEM_SIZE >> 10);
 
      dbg_id       = {pmem_size,
                      dmem_size,
                      mpy_info,
                      per_space,
                      user_version,
                      cpu_asic,
                      cpu_version};
 
      // Check reset value
      for ( ii=0; ii < 64; ii=ii+1)
        begin
           dbg_uart_rd(ii[7:0]);
 
           case(ii)
 
             1       : if (dbg_uart_buf !== dbg_id[31:16]) tb_error("READ 1 ERROR (CPU_ID_HI)");
             2       : if (dbg_uart_buf !== 16'h0000)      tb_error("READ 1 ERROR (CPU_CTL)");
             3       : if (dbg_uart_buf !== 16'h0005)      tb_error("READ 1 ERROR (CPU_STAT)");
            24       : if (dbg_uart_buf !== 16'h3412)      tb_error("READ 1 ERROR (CPU_NR)");
             default : if (dbg_uart_buf !== 16'h0000)      tb_error("READ 1 ERROR");
           endcase
        end
 
      // Write access
      for ( ii=0; ii < 64; ii=ii+1)
        begin
           // Skip write for MEM_CNT
           if (ii!=7)
             dbg_uart_wr(ii[7:0] ,  16'hffff);
        end
 
      // Read value back
      for ( ii=0; ii < 64; ii=ii+1)
        begin
           dbg_uart_rd(ii[7:0]);
 
           case(ii)
 
             1       : if (dbg_uart_buf !== dbg_id[31:16]) tb_error("READ 2 ERROR (CPU_ID_HI)");
             2       : if (dbg_uart_buf !== 16'h0078)      tb_error("READ 2 ERROR (CPU_CTL)");
             3       : if ((dbg_uart_buf !== 16'h0004)&0)  tb_error("READ 2 ERROR (CPU_STAT)");
             4       : if (dbg_uart_buf !== 16'h000E)      tb_error("READ 2 ERROR (MEM_CTL)");
             5       : if (dbg_uart_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (MEM_ADDR)");
             6       : if (dbg_uart_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (MEM_DATA)");
             7       : if (dbg_uart_buf !== 16'h0000)      tb_error("READ 2 ERROR (MEM_CNT)");
`ifdef DBG_HWBRK_0
   `ifdef DBG_HWBRK_RANGE
             8       : if (dbg_uart_buf !== 16'h001F)      tb_error("READ 2 ERROR (BRK0_CTL)");
   `else
             8       : if (dbg_uart_buf !== 16'h000F)      tb_error("READ 2 ERROR (BRK0_CTL)");
   `endif
             9       : if (dbg_uart_buf !== 16'h0000)      tb_error("READ 2 ERROR (BRK0_STAT)");
            10       : if (dbg_uart_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (BRK0_ADDR0)");
            11       : if (dbg_uart_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (BRK0_ADDR1)");
`endif
`ifdef DBG_HWBRK_1
   `ifdef DBG_HWBRK_RANGE
            12       : if (dbg_uart_buf !== 16'h001F)      tb_error("READ 2 ERROR (BRK1_CTL)");
   `else
            12       : if (dbg_uart_buf !== 16'h000F)      tb_error("READ 2 ERROR (BRK1_CTL)");
   `endif
            13       : if (dbg_uart_buf !== 16'h0000)      tb_error("READ 2 ERROR (BRK1_STAT)");
            14       : if (dbg_uart_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (BRK1_ADDR0)");
            15       : if (dbg_uart_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (BRK1_ADDR1)");
`endif
`ifdef DBG_HWBRK_2
   `ifdef DBG_HWBRK_RANGE
            16       : if (dbg_uart_buf !== 16'h001F)      tb_error("READ 2 ERROR (BRK2_CTL)");
   `else
            16       : if (dbg_uart_buf !== 16'h000F)      tb_error("READ 2 ERROR (BRK2_CTL)");
   `endif
            17       : if (dbg_uart_buf !== 16'h0000)      tb_error("READ 2 ERROR (BRK2_STAT)");
            18       : if (dbg_uart_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (BRK2_ADDR0)");
            19       : if (dbg_uart_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (BRK2_ADDR1)");
`endif
`ifdef DBG_HWBRK_3
   `ifdef DBG_HWBRK_RANGE
            20       : if (dbg_uart_buf !== 16'h001F)      tb_error("READ 2 ERROR (BRK3_CTL)");
   `else
            20       : if (dbg_uart_buf !== 16'h000F)      tb_error("READ 2 ERROR (BRK3_CTL)");
   `endif
            21       : if (dbg_uart_buf !== 16'h0000)      tb_error("READ 2 ERROR (BRK3_STAT)");
            22       : if (dbg_uart_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (BRK3_ADDR0)");
            23       : if (dbg_uart_buf !== 16'hFFFF)      tb_error("READ 2 ERROR (BRK3_ADDR1)");
`endif
            24       : if (dbg_uart_buf !== 16'h3412)      tb_error("READ 2 ERROR (CPU_NR)");
             default : if (dbg_uart_buf !== 16'h0000)      tb_error("READ 2 ERROR");
           endcase
        end
 
 
      dbg_uart_wr(CPU_CTL    ,  16'h0002);
      repeat(10) @(posedge mclk);
 
      stimulus_done = 1;
`else
 
       tb_skip_finish("|   (serial debug interface UART not included)  |");
`endif
`else
       tb_skip_finish("|      (serial debug interface not included)    |");
`endif
   end

Line No.	Rev	Author	Line
1	134	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* DEBUG INTERFACE: RD / WR */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the UART debug interface: */`
27			`/* - Check RD/WR access to all adressable */`
28			`/* debug registers. */`
29			`/* */`
30			`/* Author(s): */`
31			`/* - Olivier Girard, olgirard@gmail.com */`
32			`/* */`
33			`/---------------------------------------------------------------------------/`
34			`/* $Rev: 95 $ */`
35			`/* $LastChangedBy: olivier.girard $ */`
36			`/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */`
37			`/===========================================================================/`
38
39			`define LONG_TIMEOUT
40
41			`reg [2:0] cpu_version;`
42			`reg cpu_asic;`
43			`reg [4:0] user_version;`
44			`reg [6:0] per_space;`
45			`reg mpy_info;`
46			`reg [8:0] dmem_size;`
47			`reg [5:0] pmem_size;`
48			`reg [31:0] dbg_id;`
49
50	154	olivier.gi	`// Set oMSP parameters for later check`
51			`defparam dut.INST_NR = 8'h12;`
52			`defparam dut.TOTAL_NR = 8'h34;`
53
54	134	olivier.gi	`integer ii;`
55
56
57			`initial`
58			`begin`
59			`$display(" ===============================================");`
60			`$display("\| START SIMULATION \|");`
61			`$display(" ===============================================");`
62			`ifdef DBG_EN
63			`ifdef DBG_UART
64			`#1 dbg_en = 1;`
65			`repeat(30) @(posedge mclk);`
66			`stimulus_done = 0;`
67
68			`// SEND UART SYNCHRONIZATION FRAME`
69			`dbg_uart_tx(DBG_SYNC);`
70
71			`// STOP CPU`
72			`dbg_uart_wr(CPU_CTL , 16'h0001);`
73
74			`// TEST READ/WR TO ALL DEBUG REGISTERS`
75			`//--------------------------------------------------------`
76
77			cpu_version = `CPU_VERSION;
78			`ifdef ASIC
79			`cpu_asic = 1'b1;`
80			`else
81			`cpu_asic = 1'b0;`
82			`endif
83			user_version = `USER_VERSION;
84			per_space = (`PER_SIZE >> 9);
85			`ifdef MULTIPLIER
86			`mpy_info = 1'b1;`
87			`else
88			`mpy_info = 1'b0;`
89			`endif
90			dmem_size = (`DMEM_SIZE >> 7);
91			pmem_size = (`PMEM_SIZE >> 10);
92
93			`dbg_id = {pmem_size,`
94			`dmem_size,`
95			`mpy_info,`
96			`per_space,`
97			`user_version,`
98			`cpu_asic,`
99			`cpu_version};`
100
101			`// Check reset value`
102			`for ( ii=0; ii < 64; ii=ii+1)`
103			`begin`
104			`dbg_uart_rd(ii[7:0]);`
105
106			`case(ii)`
107
108			`1 : if (dbg_uart_buf !== dbg_id[31:16]) tb_error("READ 1 ERROR (CPU_ID_HI)");`
109			`2 : if (dbg_uart_buf !== 16'h0000) tb_error("READ 1 ERROR (CPU_CTL)");`
110			`3 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 1 ERROR (CPU_STAT)");`
111	154	olivier.gi	`24 : if (dbg_uart_buf !== 16'h3412) tb_error("READ 1 ERROR (CPU_NR)");`
112	134	olivier.gi	`default : if (dbg_uart_buf !== 16'h0000) tb_error("READ 1 ERROR");`
113			`endcase`
114			`end`
115
116			`// Write access`
117			`for ( ii=0; ii < 64; ii=ii+1)`
118			`begin`
119			`// Skip write for MEM_CNT`
120			`if (ii!=7)`
121			`dbg_uart_wr(ii[7:0] , 16'hffff);`
122			`end`
123	202	olivier.gi
124	134	olivier.gi	`// Read value back`
125			`for ( ii=0; ii < 64; ii=ii+1)`
126			`begin`
127			`dbg_uart_rd(ii[7:0]);`
128
129			`case(ii)`
130
131			`1 : if (dbg_uart_buf !== dbg_id[31:16]) tb_error("READ 2 ERROR (CPU_ID_HI)");`
132			`2 : if (dbg_uart_buf !== 16'h0078) tb_error("READ 2 ERROR (CPU_CTL)");`
133			`3 : if ((dbg_uart_buf !== 16'h0004)&0) tb_error("READ 2 ERROR (CPU_STAT)");`
134			`4 : if (dbg_uart_buf !== 16'h000E) tb_error("READ 2 ERROR (MEM_CTL)");`
135			`5 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (MEM_ADDR)");`
136			`6 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (MEM_DATA)");`
137			`7 : if (dbg_uart_buf !== 16'h0000) tb_error("READ 2 ERROR (MEM_CNT)");`
138			`ifdef DBG_HWBRK_0
139			`ifdef DBG_HWBRK_RANGE
140			`8 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK0_CTL)");`
141			`else
142			`8 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK0_CTL)");`
143			`endif
144	175	olivier.gi	`9 : if (dbg_uart_buf !== 16'h0000) tb_error("READ 2 ERROR (BRK0_STAT)");`
145	134	olivier.gi	`10 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK0_ADDR0)");`
146			`11 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK0_ADDR1)");`
147			`endif
148			`ifdef DBG_HWBRK_1
149			`ifdef DBG_HWBRK_RANGE
150			`12 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK1_CTL)");`
151			`else
152			`12 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK1_CTL)");`
153			`endif
154	175	olivier.gi	`13 : if (dbg_uart_buf !== 16'h0000) tb_error("READ 2 ERROR (BRK1_STAT)");`
155	134	olivier.gi	`14 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK1_ADDR0)");`
156			`15 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK1_ADDR1)");`
157			`endif
158			`ifdef DBG_HWBRK_2
159			`ifdef DBG_HWBRK_RANGE
160			`16 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK2_CTL)");`
161			`else
162			`16 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK2_CTL)");`
163			`endif
164	175	olivier.gi	`17 : if (dbg_uart_buf !== 16'h0000) tb_error("READ 2 ERROR (BRK2_STAT)");`
165	134	olivier.gi	`18 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK2_ADDR0)");`
166			`19 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK2_ADDR1)");`
167			`endif
168			`ifdef DBG_HWBRK_3
169			`ifdef DBG_HWBRK_RANGE
170			`20 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK3_CTL)");`
171			`else
172			`20 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK3_CTL)");`
173			`endif
174	175	olivier.gi	`21 : if (dbg_uart_buf !== 16'h0000) tb_error("READ 2 ERROR (BRK3_STAT)");`
175	134	olivier.gi	`22 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK3_ADDR0)");`
176			`23 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK3_ADDR1)");`
177			`endif
178	154	olivier.gi	`24 : if (dbg_uart_buf !== 16'h3412) tb_error("READ 2 ERROR (CPU_NR)");`
179	134	olivier.gi	`default : if (dbg_uart_buf !== 16'h0000) tb_error("READ 2 ERROR");`
180			`endcase`
181			`end`
182
183	202	olivier.gi
184			`dbg_uart_wr(CPU_CTL , 16'h0002);`
185	134	olivier.gi	`repeat(10) @(posedge mclk);`
186
187			`stimulus_done = 1;`
188			`else
189
190	202	olivier.gi	`tb_skip_finish("\| (serial debug interface UART not included) \|");`
191	134	olivier.gi	`endif
192			`else
193	202	olivier.gi	`tb_skip_finish("\| (serial debug interface not included) \|");`
194	134	olivier.gi	`endif
195			`end`

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart_rdwr.v] - Blame information for rev 202