OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart_sync.s43] - Blame information for rev 219

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 134 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                            DEBUG INTERFACE:  UART                         */
25
/*---------------------------------------------------------------------------*/
26
/* Test the UART debug interface:                                            */
27
/*                        - Check synchronization of the serial              */
28
/*                          debug interface input.                           */
29
/*                                                                           */
30
/* Author(s):                                                                */
31
/*             - Olivier Girard,    olgirard@gmail.com                       */
32
/*                                                                           */
33
/*---------------------------------------------------------------------------*/
34
/* $Rev: 19 $                                                                */
35
/* $LastChangedBy: olivier.girard $                                          */
36
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
37
/*===========================================================================*/
38
 
39 141 olivier.gi
.include "pmem_defs.asm"
40 134 olivier.gi
 
41
.global main
42
 
43
.macro LPM0
44
 bis    #0x0010, r2
45
.endm
46
 
47
main:
48
        mov #DMEM_250, r1       ; # Initialize stack pointer
49
        mov   #0x0000, &DMEM_200
50
        mov   #0x0000, r15
51
 
52
        eint
53
        LPM0
54
 
55
        mov   #0x1000, r15
56
 
57
 
58
 
59
 
60
        /* ----------------------         END OF TEST        --------------- */
61
end_of_test:
62
        mov #0x0010, r14
63
  wait_loop:
64
        dec r14
65
        jnz wait_loop
66
        nop
67
        br #0xffff
68
 
69
 
70
        /* ----------------------         INTERRUPT VECTORS  --------------- */
71
 
72
.section .vectors, "a"
73
.word end_of_test        ; Interrupt  0 (lowest priority)    
74
.word end_of_test        ; Interrupt  1                      
75
.word end_of_test        ; Interrupt  2                      
76
.word end_of_test        ; Interrupt  3                      
77
.word end_of_test        ; Interrupt  4                      
78
.word end_of_test        ; Interrupt  5                      
79
.word end_of_test        ; Interrupt  6                      
80
.word end_of_test        ; Interrupt  7                      
81
.word end_of_test        ; Interrupt  8                      
82
.word end_of_test        ; Interrupt  9                      
83
.word end_of_test        ; Interrupt 10                      Watchdog timer
84
.word end_of_test        ; Interrupt 11                      
85
.word end_of_test        ; Interrupt 12                      
86
.word end_of_test        ; Interrupt 13                      
87
.word end_of_test        ; Interrupt 14                      NMI
88
.word main               ; Interrupt 15 (highest priority)   RESET

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.