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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dma_dbg_arbiter.v] - Blame information for rev 219

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Line No. Rev Author Line
1 202 olivier.gi
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                            DMA INTERFACE                                  */
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/*---------------------------------------------------------------------------*/
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/* Test the DMA interface:                                                   */
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/*                        - Check DMA and Debug interface arbitration.       */
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/*                                                                           */
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/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
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/*---------------------------------------------------------------------------*/
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/* $Rev$                                                                */
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/* $LastChangedBy$                                          */
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/* $LastChangedDate$          */
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/*===========================================================================*/
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`define VERY_LONG_TIMEOUT
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integer    dbg_cnt_wr;
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integer    dbg_cnt_rd;
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integer    dbg_wr_error;
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integer    dbg_rd_error;
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integer    dbg_mem_ref_idx;
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reg [15:0] dbg_pmem_reference[0:128];
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reg [15:0] dbg_dmem_reference[0:128];
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reg [15:0] dbg_if_buf;
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reg  [7:0] kk;
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reg [15:0] dbg_rand_val;
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reg        dbg_rand_rd_wr;
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reg        dbg_rand_mem_sel;
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reg  [7:0] dbg_rand_offset;
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reg  [7:0] dbg_rand_size;
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initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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`ifdef DMA_IF_EN
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`ifdef DBG_EN
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      // Skip verification if memory configuration is too small
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      if (~((`PMEM_SIZE>=4092) && (`DMEM_SIZE>=1024)))
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        begin
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           tb_skip_finish("|  (PMEM size less than 4kB or DMEM size is less than 1kB)  |");
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        end
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      #1 dbg_en    = 1;
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      dbg_if_buf   = 16'h0000;
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      dma_verif_on = 1;
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      dbg_cnt_wr   = 0;
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      dbg_cnt_rd   = 0;
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      dbg_wr_error = 0;
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      dbg_rd_error = 0;
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      repeat(30) @(posedge mclk);
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      stimulus_done = 0;
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      // Disable random delay on DMA inteface to maximize the number of transfer
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      dma_rand_wait_disable = 1;
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      // Initialize memory for debug interface random accesses
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      for (dbg_mem_ref_idx=0; dbg_mem_ref_idx < 128; dbg_mem_ref_idx=dbg_mem_ref_idx+1)
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        begin
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           dbg_rand_val                        = $urandom;
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           dbg_pmem_reference[dbg_mem_ref_idx] = dbg_rand_val;
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           pmem_0.mem[128+dbg_mem_ref_idx]     = dbg_rand_val;
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           dbg_rand_val                        = $urandom;
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           dbg_dmem_reference[dbg_mem_ref_idx] = dbg_rand_val;
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           dmem_0.mem[128+dbg_mem_ref_idx]     = dbg_rand_val;
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        end
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      // SEND UART SYNCHRONIZATION FRAME
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   `ifdef DBG_UART
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      dbg_uart_tx(DBG_SYNC);
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   `endif
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      // RUN CPU
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      dbg_if_wr(CPU_CTL,  16'h0002);
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      // Let CPU execute a bit before enabling the priority DMA
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      // (this will let the firmware enough time to disable the watchdog)
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      repeat(30) @(posedge mclk);
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      dma_priority = 1;
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      //--------------------------------
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      // Debug interface transfer
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      //--------------------------------
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      for (kk=0; kk < 50; kk=kk+1)
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        begin
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           // Ramdomly choose:
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           //                 - read or write access
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           //                 - Program or Data memory
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           //                 - transfer size
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           //                 - memory offset
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           dbg_rand_rd_wr   = $urandom_range(0,1);
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           dbg_rand_mem_sel = $urandom_range(0,1);
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           dbg_rand_size    = $urandom_range(10,63);
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           dbg_rand_offset  = $urandom_range(0,63);
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           $display("START DBG BURST %d:   write=%h  /  pmem_sel=%h  /  size=%d  /  offset=%d", kk, dbg_rand_rd_wr, dbg_rand_mem_sel, dbg_rand_size, dbg_rand_offset);
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           if (dbg_rand_rd_wr) dbg_if_burst_write_16b(dbg_rand_mem_sel, dbg_rand_offset, dbg_rand_size);
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           else                dbg_if_burst_read_16b( dbg_rand_mem_sel, dbg_rand_offset, dbg_rand_size);
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        end
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      //--------------------------------
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      // End of test
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      //--------------------------------
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      // Remove DMA priority to let the CPU execute some code
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      dma_priority = 0;
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      // Update variable to let firmware finish execution
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      dbg_if_wr(MEM_ADDR, (16'h0000-`PMEM_SIZE));
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      dbg_if_wr(MEM_DATA,  16'h0001);
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      dbg_if_wr(MEM_CTL,   16'h0003);
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      $display("\n");
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      $display("DBG REPORT: Total Accesses: %-d Total RD: %-d Total WR: %-d", dbg_cnt_rd+dbg_cnt_wr,     dbg_cnt_rd,   dbg_cnt_wr);
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      $display("            Total Errors:   %-d Error RD: %-d Error WR: %-d", dbg_rd_error+dbg_wr_error, dbg_rd_error, dbg_wr_error);
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      $display("\n");
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      stimulus_done = 1;
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`else
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       tb_skip_finish("|      (serial debug interface not included)    |");
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`endif
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`else
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       tb_skip_finish("|      (DMA interface support not included)    |");
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`endif
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   end
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//-----------------------------------------------------
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// Generic debug interface tasks
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//-----------------------------------------------------
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task dbg_if_wr;
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   input  [7:0] dbg_reg;
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   input [15:0] dbg_data;
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   begin
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   `ifdef DBG_UART
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      dbg_uart_wr(dbg_reg, dbg_data);
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   `else
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      dbg_i2c_wr(dbg_reg, dbg_data);
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   `endif
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   end
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endtask
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task dbg_if_tx16;
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   input [15:0] dbg_data;
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   input        is_last;
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   begin
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   `ifdef DBG_UART
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      dbg_uart_tx16(dbg_data);
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   `else
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      dbg_i2c_tx16(dbg_data, is_last);
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   `endif
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   end
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endtask
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task dbg_if_rx16;
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   input        is_last;
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   begin
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   `ifdef DBG_UART
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      dbg_uart_rx16;
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      dbg_if_buf = dbg_uart_buf;
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   `else
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      repeat(30) @(posedge mclk);
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      dbg_i2c_rx16(is_last);
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      dbg_if_buf = dbg_i2c_buf;
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   `endif
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   end
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endtask
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//-----------------------------------------------------
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// Debug interface burst tasks
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//-----------------------------------------------------
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task dbg_if_burst_write_16b;
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   input        mem_sel;  // 1: Program memory / 0: Data memory
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   input [15:0] offset;
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   input [15:0] size;
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   integer     idx;
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   reg  [15:0] data_val;
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   begin
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      if (mem_sel) dbg_if_wr(MEM_ADDR, ('h0000-`PMEM_SIZE+256+offset*2));
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      else         dbg_if_wr(MEM_ADDR, (`PER_SIZE+256+offset*2));
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      dbg_if_wr(MEM_CNT,  size-1);
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      dbg_if_wr(MEM_CTL,  16'h0003); // Start burst to 16 bit memory write
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   `ifdef DBG_I2C
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      dbg_i2c_burst_start(0);
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   `endif
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      for (idx=0; idx < size; idx=idx+1)
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        begin
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           data_val = $urandom;
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           if (mem_sel) dbg_pmem_reference[offset+idx] = data_val;
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           else         dbg_dmem_reference[offset+idx] = data_val;
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           if (idx!=(size-1)) dbg_if_tx16(data_val, 0);
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           else               dbg_if_tx16(data_val, 1);
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           dbg_cnt_wr = dbg_cnt_wr+1;
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        end
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      repeat(12) @(posedge mclk);
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      for (idx=0; idx < size; idx=idx+1)
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        begin
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           if      ( mem_sel & (pmem_0.mem[128+offset+idx] !== dbg_pmem_reference[offset+idx])) begin dbg_wr_error=dbg_wr_error+1; tb_error("====== DBG INTERFACE PMEM WRITE ERROR ====="); end
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           else if (~mem_sel & (dmem_0.mem[128+offset+idx] !== dbg_dmem_reference[offset+idx])) begin dbg_wr_error=dbg_wr_error+1; tb_error("====== DBG INTERFACE DMEM WRITE ERROR ====="); end
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        end
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   end
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endtask
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task dbg_if_burst_read_16b;
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   input        mem_sel;  // 1: Program memory / 0: Data memory
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   input [15:0] offset;
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   input [15:0] size;
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   integer     idx;
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   begin
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      if (mem_sel) dbg_if_wr(MEM_ADDR, ('h0000-`PMEM_SIZE+256+offset*2));
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      else         dbg_if_wr(MEM_ADDR, (`PER_SIZE+256+offset*2));
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      dbg_if_wr(MEM_CNT,  size-1);
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      dbg_if_wr(MEM_CTL,  16'h0001);              // Start burst to 16 bit registers read
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   `ifdef DBG_I2C
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      dbg_i2c_burst_start(1);
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   `endif
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      for (idx=0; idx < size; idx=idx+1)
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        begin
262
           if (idx!=(size-1)) dbg_if_rx16(0);
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           else               dbg_if_rx16(1);
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           dbg_cnt_rd = dbg_cnt_rd+1;
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           // Make sure we don't read an X
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           if      ( mem_sel & (dbg_if_buf === 16'hxxxx)) begin dbg_rd_error=dbg_rd_error+1; tb_error("====== DBG INTERFACE PMEM READ XXXXX ====="); end
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           else if (~mem_sel & (dbg_if_buf === 16'hxxxx)) begin dbg_rd_error=dbg_rd_error+1; tb_error("====== DBG INTERFACE DMEM READ XXXXX ====="); end
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           // Check result
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           if      ( mem_sel & (dbg_if_buf !== dbg_pmem_reference[offset+idx]))  begin dbg_rd_error=dbg_rd_error+1; tb_error("====== DBG INTERFACE PMEM  READ ERROR ====="); end
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           else if (~mem_sel & (dbg_if_buf !== dbg_dmem_reference[offset+idx]))  begin dbg_rd_error=dbg_rd_error+1; tb_error("====== DBG INTERFACE DMEM  READ ERROR ====="); end
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        end
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   end
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endtask

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