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olivier.gi |
/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/*===========================================================================*/
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/* CPU LOW POWER MODES & DMA TRANSFER */
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/*---------------------------------------------------------------------------*/
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/* Test DMA transfer with the CPU Low Power modes: */
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/* */
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/* - LPM0 <=> CPUOFF */
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/* - LPM1 <=> CPUOFF + SCG0 */
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/* - LPM2 <=> CPUOFF + SCG1 */
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/* - LPM3 <=> CPUOFF + SCG0 + SCG1 */
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/* - LPM4 <=> CPUOFF + SCG0 + SCG1 + OSCOFF */
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/* */
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/* */
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/* Reminder about config registers: */
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/* */
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/* - CPUOFF <=> turns off CPU. */
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/* - SCG0 <=> turns off DCO. */
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/* - SCG1 <=> turns off SMCLK. */
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/* - OSCOFF <=> turns off LFXT_CLK. */
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/* */
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/* - DMA_CPUOFF <=> allow DMA to turn on MCLK */
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/* - DMA_SCG0 <=> allow DMA to turn on DCO */
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/* - DMA_SCG1 <=> allow DMA to turn on SMCLK */
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/* - DMA_OSCOFF <=> allow DMA to turn on LFXT_CLK */
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/* */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 95 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
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/*===========================================================================*/
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`define VERY_LONG_TIMEOUT
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reg dma_loop_enable;
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integer dma_loop_nr;
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integer cfg_idx;
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integer dco_clk_cnt;
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always @(negedge dco_clk)
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dco_clk_cnt <= dco_clk_cnt+1;
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integer mclk_dma_cnt;
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always @(negedge mclk)
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mclk_dma_cnt <= mclk_dma_cnt+1;
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integer mclk_cpu_cnt;
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always @(negedge tb_openMSP430.dut.cpu_mclk)
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mclk_cpu_cnt <= mclk_cpu_cnt+1;
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integer smclk_cnt;
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always @(negedge smclk)
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smclk_cnt <= smclk_cnt+1;
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integer aclk_cnt;
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always @(negedge aclk)
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aclk_cnt <= aclk_cnt+1;
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integer inst_cnt;
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always @(inst_number)
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inst_cnt <= inst_cnt+1;
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// Wakeup synchronizer to generate IRQ
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reg [1:0] wkup2_sync;
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always @(posedge mclk or posedge puc_rst)
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if (puc_rst) wkup2_sync <= 2'b00;
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else wkup2_sync <= {wkup2_sync[0], wkup[2]};
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always @(wkup2_sync)
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irq[`IRQ_NR-14] = wkup2_sync[1]; // IRQ-2
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// Wakeup synchronizer to generate IRQ
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reg [1:0] wkup3_sync;
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always @(posedge mclk or posedge puc_rst)
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if (puc_rst) wkup3_sync <= 2'b00;
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else wkup3_sync <= {wkup3_sync[0], wkup[3]};
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always @(wkup3_sync)
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irq[`IRQ_NR-13] = wkup3_sync[1]; // IRQ-3
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initial
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begin
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$display(" ===============================================");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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`ifdef DMA_IF_EN
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// Disable automatic DMA verification
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#10;
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dma_verif_on = 0;
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repeat(5) @(posedge mclk);
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stimulus_done = 0;
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irq[`IRQ_NR-14] = 0; // IRQ-2
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wkup[2] = 0;
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irq[`IRQ_NR-13] = 0; // IRQ-3
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wkup[3] = 0;
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`ifdef ASIC_CLOCKING
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`ifdef CPUOFF_EN
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//--------------------------------------------------------
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// ACTIVE
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//--------------------------------------------------------
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@(r15==16'h1001);
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$display("");
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$display("\nACTIVE - NO DMA");
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// DCO_CLK, MCLK_CPU, MCLK_DMA, SMCLK, ACLK1, ACLK2, INST, DMA_NR
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clock_check( 100 , 100 , 100 , 100 , 4 , 100 , 60 , 0 );
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// Check clocks for each possible DMA wakeup configuration
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for ( cfg_idx=0; cfg_idx < 16; cfg_idx=cfg_idx+1)
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begin
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@(r15==(16'h3000 + cfg_idx));
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$display("\nLPM2 (CPUOFF+SCG1) - {DMA_SCG1, DMA_SCG0, DMA_OSCOFF, DMA_CPUOFF}={%d, %d, %d, %d}\n", cfg_idx[3], cfg_idx[2], cfg_idx[1], cfg_idx[0]);
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// {SCG1 , SCG0 , OSCOFF }
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full_lpm_clock_check ( lpm_clocks_status ({1'b1 , 1'b0 , 1'b0 }), // Get running clocks in low power mode
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// {SCG1 , SCG0 , OSCOFF } { DMA_SCG1 , DMA_SCG0 , DMA_OSCOFF, DMA_CPUOFF }
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lmp_clocks_status_dma_wkup({1'b1 , 1'b0 , 1'b0 }, {cfg_idx[3],cfg_idx[2], cfg_idx[1], cfg_idx[0] })); // Get running clocks in low power mode with DMA wake-up
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end
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$display("");
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`else
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tb_skip_finish("| (CPUOFF low power mode should be enabled) |");
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`endif
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`else
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tb_skip_finish("| (this test is not supported in FPGA mode) |");
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`endif
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`else
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tb_skip_finish("| (DMA interface support not included) |");
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`endif
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stimulus_done = 1;
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end
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//------------------------------------------------------
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// Clock check function
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//------------------------------------------------------
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task clock_check;
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input integer dco_val;
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input integer mclk_cpu_val;
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input integer mclk_dma_val;
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input integer smclk_val;
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input integer aclk_val1;
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input integer aclk_val2;
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input integer inst_val;
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input integer dma_val;
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begin
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`ifdef LFXT_DOMAIN
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if (aclk_val1 != 0) @(posedge aclk);
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`endif
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tb_idx = 777;
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#(100*50);
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dco_clk_cnt = 0;
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mclk_cpu_cnt = 0;
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mclk_dma_cnt = 0;
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smclk_cnt = 0;
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tb_idx = 888;
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aclk_cnt = 0;
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inst_cnt = 0;
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dma_loop_nr = 0;
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#(100*50);
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if (dco_clk_cnt !== dco_val) tb_error("====== DCO_CLK CHECK FAILED =====");
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if (mclk_cpu_cnt !== mclk_cpu_val) tb_error("====== MCLK CPU CHECK FAILED =====");
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if (mclk_dma_cnt !== mclk_dma_val) tb_error("====== MCLK DMA CHECK FAILED =====");
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if (smclk_cnt !== smclk_val) tb_error("====== SMCLK CHECK FAILED =====");
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`ifdef LFXT_DOMAIN
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if (aclk_cnt !== aclk_val1) tb_error("====== ACLK1 CHECK FAILED =====");
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`else
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if (aclk_cnt !== aclk_val2) tb_error("====== ACLK2 CHECK FAILED =====");
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`endif
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if (inst_cnt < inst_val) tb_error("====== INST_NR CHECK FAILED =====");
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if (dma_loop_nr !== dma_val) tb_error("====== DMA_NR CHECK FAILED =====");
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dco_clk_cnt = 0;
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mclk_cpu_cnt = 0;
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mclk_dma_cnt = 0;
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smclk_cnt = 0;
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aclk_cnt = 0;
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inst_cnt = 0;
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dma_loop_nr = 0;
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end
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endtask
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//------------------------------------------------------
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// Check Clocks for the whole LPM sequence
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//------------------------------------------------------
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task full_lpm_clock_check;
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input [2:0] lpm_clock_status; // { SMCLK , DCO_CLK , ACLK }
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input [3:0] lpm_clock_status_dma_wkup; // { SMCLK , DCO_CLK , ACLK , MCLK_DMA }
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integer lpm_dco , lpm_mclk_cpu , lpm_mclk_dma , lpm_smclk , lpm_aclk1 , lpm_aclk2 , lpm_inst , lpm_dma_nr ;
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integer dma_nowkup_dco, dma_nowkup_mclk_cpu, dma_nowkup_mclk_dma, dma_nowkup_smclk, dma_nowkup_aclk1, dma_nowkup_aclk2, dma_nowkup_inst, dma_nowkup_dma_nr;
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integer dma_wkup_dco , dma_wkup_mclk_cpu , dma_wkup_mclk_dma , dma_wkup_smclk , dma_wkup_aclk1 , dma_wkup_aclk2 , dma_wkup_inst , dma_wkup_dma_nr ;
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begin
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// Initialize target values
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lpm_dco =0; lpm_mclk_cpu =0; lpm_mclk_dma =0; lpm_smclk =0; lpm_aclk1 =0; lpm_aclk2 =0; lpm_inst =0; lpm_dma_nr =0;
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dma_nowkup_dco=0; dma_nowkup_mclk_cpu=0; dma_nowkup_mclk_dma=0; dma_nowkup_smclk=0; dma_nowkup_aclk1=0; dma_nowkup_aclk2=0; dma_nowkup_inst=0; dma_nowkup_dma_nr=0;
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dma_wkup_dco =0; dma_wkup_mclk_cpu =0; dma_wkup_mclk_dma =0; dma_wkup_smclk =0; dma_wkup_aclk1 =0; dma_wkup_aclk2 =0; dma_wkup_inst =0; dma_wkup_dma_nr =0;
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// Update depending on running clocks during the low-power mode (no DMA)
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if (lpm_clock_status[0]) begin lpm_aclk1 = 4; lpm_aclk2 = 100; end
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if (lpm_clock_status[1]) begin lpm_dco = 100; lpm_mclk_cpu = 0; end
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if (lpm_clock_status[2]) begin lpm_smclk = 100; end
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// Update depending on running clocks during the low-power mode (with DMA, with wakeup)
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if (lpm_clock_status_dma_wkup[0]) begin dma_wkup_mclk_dma = 100; end else begin dma_wkup_mclk_dma = lpm_mclk_dma; end
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if (lpm_clock_status_dma_wkup[1]) begin dma_wkup_aclk1 = 4; dma_wkup_aclk2 = 100; end else begin dma_wkup_aclk1 = lpm_aclk1 ; dma_wkup_aclk2 = lpm_aclk2 ; end
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if (lpm_clock_status_dma_wkup[2]) begin dma_wkup_dco = 100; dma_wkup_mclk_cpu = 0; end else begin dma_wkup_dco = lpm_dco ; dma_wkup_mclk_cpu = lpm_mclk_cpu; end
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if (lpm_clock_status_dma_wkup[3]) begin dma_wkup_smclk = 100; end else begin dma_wkup_smclk = lpm_smclk ; end
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if (dma_wkup_smclk == 100) begin dma_wkup_dma_nr = dma_wkup_mclk_dma; end
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// Update depending on running clocks during the low-power mode (with DMA, no wakeup)
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if ((lpm_smclk == 100) &
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lpm_clock_status_dma_wkup[0]) begin dma_nowkup_mclk_dma = 100; end
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if (lpm_smclk == 100) begin dma_nowkup_dma_nr = dma_nowkup_mclk_dma; end
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if (lpm_smclk == 100) begin dma_nowkup_aclk1 = dma_wkup_aclk1; dma_nowkup_aclk2 = dma_wkup_aclk2; end
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else begin dma_nowkup_aclk1 = lpm_aclk1; dma_nowkup_aclk2 = lpm_aclk2; end
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//---------- NO DMA - CHECK CLOCK STATUS -------------//
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$display(" - NO DMA");
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clock_check(lpm_dco, lpm_mclk_cpu, lpm_mclk_dma, lpm_smclk, lpm_aclk1, lpm_aclk2, lpm_inst, lpm_dma_nr );
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//---------- PERFORM DMA TRANSFER NO WAKEUP - CHECK CLOCK STATUS -------------//
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$display(" - WITH DMA, NO WAKE-UP");
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dma_wkup = 0;
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dma_loop_enable = 1;
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tb_idx = 666;
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clock_check(lpm_dco, lpm_mclk_cpu, dma_nowkup_mclk_dma, lpm_smclk, dma_nowkup_aclk1, dma_nowkup_aclk2, lpm_inst, dma_nowkup_dma_nr );
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tb_idx = 999;
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dma_loop_enable = 0;
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dma_wkup = 0;
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#100;
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dma_tfx_cancel = 1;
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#100;
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dma_tfx_cancel = 0;
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#100;
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//---------- NO DMA - CHECK CLOCK STATUS -------------//
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$display(" - NO DMA");
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clock_check(lpm_dco, lpm_mclk_cpu, lpm_mclk_dma, lpm_smclk, lpm_aclk1, lpm_aclk2, lpm_inst, lpm_dma_nr );
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//---------- PERFORM DMA TRANSFER WITH WAKEUP - CHECK CLOCK STATUS -------------//
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$display(" - WITH DMA, WITH WAKE-UP");
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dma_wkup = 1;
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dma_loop_enable = 1;
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clock_check(dma_wkup_dco, dma_wkup_mclk_cpu, dma_wkup_mclk_dma, dma_wkup_smclk, dma_wkup_aclk1, dma_wkup_aclk2, dma_wkup_inst, dma_wkup_dma_nr );
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dma_loop_enable = 0;
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dma_wkup = 0;
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#100;
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dma_tfx_cancel = 1;
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#100;
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dma_tfx_cancel = 0;
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#100;
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//---------- NO DMA - CHECK CLOCK STATUS -------------//
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$display(" - NO DMA");
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clock_check(lpm_dco, lpm_mclk_cpu, lpm_mclk_dma, lpm_smclk, lpm_aclk1, lpm_aclk2, lpm_inst, lpm_dma_nr );
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//---------- PORT2 IRQ - EXITING POWER MODE -------------//
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irq_exit_lp_mode;
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end
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|
296 |
|
|
endtask
|
297 |
|
|
|
298 |
|
|
//------------------------------------------------------
|
299 |
|
|
// ENABLE DISABLE DMA TRANSFERS
|
300 |
|
|
//------------------------------------------------------
|
301 |
|
|
// Note that we synchronize DMA transfer with SMCLK
|
302 |
|
|
|
303 |
|
|
reg [15:0] dma_loop_val;
|
304 |
|
|
reg dma_loop_enable_old;
|
305 |
|
|
initial
|
306 |
|
|
begin
|
307 |
|
|
dma_loop_enable=0;
|
308 |
|
|
dma_loop_val=0;
|
309 |
|
|
dma_loop_nr=0;
|
310 |
|
|
forever
|
311 |
|
|
begin
|
312 |
|
|
dma_loop_enable_old=dma_loop_enable;
|
313 |
|
|
if (~dma_loop_enable) @(posedge dma_loop_enable);
|
314 |
|
|
if (dma_loop_enable_old==0) @(posedge smclk or posedge dma_tfx_cancel);
|
315 |
|
|
if (~dma_tfx_cancel) dma_write_16b(16'h0000-`PMEM_SIZE, dma_loop_val, 1'b0);
|
316 |
|
|
if (~dma_tfx_cancel) dma_loop_nr=dma_loop_nr+1;
|
317 |
|
|
if (~dma_tfx_cancel)
|
318 |
|
|
begin
|
319 |
|
|
dma_loop_enable_old=dma_loop_enable;
|
320 |
|
|
if (~dma_loop_enable) @(posedge dma_loop_enable);
|
321 |
|
|
if (dma_loop_enable_old==0) @(posedge smclk or posedge dma_tfx_cancel);
|
322 |
|
|
if (~dma_tfx_cancel) dma_read_16b(16'h0000-`PMEM_SIZE, dma_loop_val, 1'b0);
|
323 |
|
|
if (~dma_tfx_cancel) dma_loop_nr=dma_loop_nr+1;
|
324 |
|
|
end
|
325 |
|
|
dma_loop_val=dma_loop_val+1;
|
326 |
|
|
end
|
327 |
|
|
end
|
328 |
|
|
|
329 |
|
|
//------------------------------------------------------
|
330 |
|
|
// IRQ to exit Low Power Mode
|
331 |
|
|
//------------------------------------------------------
|
332 |
|
|
task irq_exit_lp_mode;
|
333 |
|
|
|
334 |
|
|
begin
|
335 |
|
|
wkup[3] = 1'b1;
|
336 |
|
|
@(posedge irq_acc[`IRQ_NR-13]); // IRQ_ACC-3
|
337 |
|
|
#(10*50);
|
338 |
|
|
@(r13==16'hbbbb);
|
339 |
|
|
wkup[3] = 1'b0;
|
340 |
|
|
end
|
341 |
|
|
|
342 |
|
|
endtask
|
343 |
|
|
|
344 |
|
|
|
345 |
|
|
//----------------------------------------------------------------------------------//
|
346 |
|
|
// DETECT CLOCKS RESTORED WITH DMA WAKEUP //
|
347 |
|
|
//----------------------------------------------------------------------------------//
|
348 |
|
|
function [3:0] lmp_clocks_status_dma_wkup;
|
349 |
|
|
|
350 |
|
|
input [3:0] lpm_config; // { SCG1 , SCG0 , OSCOFF }
|
351 |
|
|
input [3:0] dma_lpm_config; // {DMA_SCG1, DMA_SCG0, DMA_OSCOFF, DMA_CPUOFF }
|
352 |
|
|
|
353 |
|
|
reg [3:0] combined_lpm_config; // {DMA_SCG1, DMA_SCG0, DMA_OSCOFF, DMA_CPUOFF }
|
354 |
|
|
reg [2:0] lpm_rtl_support; // { SCG1 , SCG0 , OSCOFF }
|
355 |
|
|
begin
|
356 |
|
|
|
357 |
|
|
// Combine low power configuration with the DMA wakeup one
|
358 |
|
|
assign combined_lpm_config = dma_lpm_config | {~lpm_config, 1'b0};
|
359 |
|
|
|
360 |
|
|
// Get supported RTL configuration
|
361 |
|
|
lpm_rtl_support = 3'h0;
|
362 |
|
|
`ifdef OSCOFF_EN
|
363 |
|
|
lpm_rtl_support = lpm_rtl_support | 3'h1;
|
364 |
|
|
`endif
|
365 |
|
|
`ifdef SCG0_EN
|
366 |
|
|
lpm_rtl_support = lpm_rtl_support | 3'h2;
|
367 |
|
|
`endif
|
368 |
|
|
`ifdef SCG1_EN
|
369 |
|
|
lpm_rtl_support = lpm_rtl_support | 3'h4;
|
370 |
|
|
`endif
|
371 |
|
|
|
372 |
|
|
// Depending on RTL configuration, figure out which clocks are running when a DMA wakeup is applied
|
373 |
|
|
case(lpm_rtl_support)
|
374 |
|
|
// SMCLK , DCO_CLK , ACLK , MCLK_DMA
|
375 |
|
|
4'b000 : lmp_clocks_status_dma_wkup = { 1'b1 , 1'b1 , 1'b1 , combined_lpm_config[0] };
|
376 |
|
|
|
377 |
|
|
4'b001 : lmp_clocks_status_dma_wkup = { 1'b1 , 1'b1 , combined_lpm_config[1] , combined_lpm_config[0] };
|
378 |
|
|
|
379 |
|
|
4'b010 : begin
|
380 |
|
|
lmp_clocks_status_dma_wkup = { combined_lpm_config[2] , combined_lpm_config[2] , 1'b1 , combined_lpm_config[0] };
|
381 |
|
|
lmp_clocks_status_dma_wkup = { 1'b1 , 1'b1 , 1'b1 , combined_lpm_config[2] } & lmp_clocks_status_dma_wkup;
|
382 |
|
|
end
|
383 |
|
|
4'b011 : begin
|
384 |
|
|
lmp_clocks_status_dma_wkup = { combined_lpm_config[2] , combined_lpm_config[2] , combined_lpm_config[1] , combined_lpm_config[0] };
|
385 |
|
|
lmp_clocks_status_dma_wkup = { 1'b1 , 1'b1 , 1'b1 , combined_lpm_config[2] } & lmp_clocks_status_dma_wkup;
|
386 |
|
|
end
|
387 |
|
|
4'b100 : lmp_clocks_status_dma_wkup = { combined_lpm_config[3] , 1'b1 , 1'b1 , combined_lpm_config[0] };
|
388 |
|
|
|
389 |
|
|
4'b101 : lmp_clocks_status_dma_wkup = { combined_lpm_config[3] , 1'b1 , combined_lpm_config[1] , combined_lpm_config[0] };
|
390 |
|
|
|
391 |
|
|
4'b110 : begin
|
392 |
|
|
lmp_clocks_status_dma_wkup = { combined_lpm_config[3] , combined_lpm_config[2] , 1'b1 , combined_lpm_config[0] };
|
393 |
|
|
lmp_clocks_status_dma_wkup = { combined_lpm_config[2] , 1'b1 , 1'b1 , combined_lpm_config[2] } & lmp_clocks_status_dma_wkup;
|
394 |
|
|
end
|
395 |
|
|
4'b111 : begin
|
396 |
|
|
lmp_clocks_status_dma_wkup = { combined_lpm_config[3] , combined_lpm_config[2] , combined_lpm_config[1] , combined_lpm_config[0] };
|
397 |
|
|
lmp_clocks_status_dma_wkup = { combined_lpm_config[2] , 1'b1 , 1'b1 , combined_lpm_config[2] } & lmp_clocks_status_dma_wkup;
|
398 |
|
|
end
|
399 |
|
|
endcase
|
400 |
|
|
|
401 |
|
|
// If Low-Frequency oscillator is not supported, ACLK is then clocked by DCO
|
402 |
|
|
`ifdef LFXT_DOMAIN
|
403 |
|
|
`else
|
404 |
|
|
lmp_clocks_status_dma_wkup[1] = lmp_clocks_status_dma_wkup[2];
|
405 |
|
|
`endif
|
406 |
|
|
|
407 |
|
|
end
|
408 |
|
|
endfunction
|
409 |
|
|
|
410 |
|
|
//----------------------------------------------------------------------------------//
|
411 |
|
|
// DETECT CLOCKS RUNNING DURING LOW-POWER-MODE //
|
412 |
|
|
//----------------------------------------------------------------------------------//
|
413 |
|
|
function [2:0] lpm_clocks_status;
|
414 |
|
|
|
415 |
|
|
input [2:0] lpm_config; // { SCG1 , SCG0 , OSCOFF }
|
416 |
|
|
|
417 |
|
|
reg [2:0] lpm_rtl_support; // { SCG1 , SCG0 , OSCOFF }
|
418 |
|
|
begin
|
419 |
|
|
|
420 |
|
|
// Get supported RTL configuration
|
421 |
|
|
lpm_rtl_support = 3'h0;
|
422 |
|
|
`ifdef OSCOFF_EN
|
423 |
|
|
lpm_rtl_support = lpm_rtl_support | 3'h1;
|
424 |
|
|
`endif
|
425 |
|
|
`ifdef SCG0_EN
|
426 |
|
|
lpm_rtl_support = lpm_rtl_support | 3'h2;
|
427 |
|
|
`endif
|
428 |
|
|
`ifdef SCG1_EN
|
429 |
|
|
lpm_rtl_support = lpm_rtl_support | 3'h4;
|
430 |
|
|
`endif
|
431 |
|
|
|
432 |
|
|
// Depending on RTL configuration, figure out which clocks are running with a given Low-Power-Mode
|
433 |
|
|
case(lpm_rtl_support)
|
434 |
|
|
// SMCLK , DCO_CLK , ACLK
|
435 |
|
|
4'b000 : lpm_clocks_status = { 1'b1 , 1'b1 , 1'b1 };
|
436 |
|
|
|
437 |
|
|
4'b001 : lpm_clocks_status = { 1'b1 , 1'b1 , ~lpm_config[0] };
|
438 |
|
|
|
439 |
|
|
4'b010 : lpm_clocks_status = { ~lpm_config[1] , ~lpm_config[1] , 1'b1 };
|
440 |
|
|
|
441 |
|
|
4'b011 : lpm_clocks_status = { ~lpm_config[1] , ~lpm_config[1] , ~lpm_config[0] };
|
442 |
|
|
|
443 |
|
|
4'b100 : lpm_clocks_status = { ~lpm_config[2] , 1'b1 , 1'b1 };
|
444 |
|
|
|
445 |
|
|
4'b101 : lpm_clocks_status = { ~lpm_config[2] , 1'b1 , ~lpm_config[0] };
|
446 |
|
|
|
447 |
|
|
4'b110 : begin
|
448 |
|
|
lpm_clocks_status = { ~lpm_config[2] , ~lpm_config[1] , 1'b1 };
|
449 |
|
|
lpm_clocks_status = { ~lpm_config[1] , 1'b1 , 1'b1 } & lpm_clocks_status;
|
450 |
|
|
end
|
451 |
|
|
4'b111 : begin
|
452 |
|
|
lpm_clocks_status = { ~lpm_config[2] , ~lpm_config[1] , ~lpm_config[0] };
|
453 |
|
|
lpm_clocks_status = { ~lpm_config[1] , 1'b1 , 1'b1 } & lpm_clocks_status;
|
454 |
|
|
end
|
455 |
|
|
endcase
|
456 |
|
|
|
457 |
|
|
// If Low-Frequency oscillator is not supported, ACLK is then clocked by DCO
|
458 |
|
|
`ifdef LFXT_DOMAIN
|
459 |
|
|
`else
|
460 |
|
|
lpm_clocks_status[0] = lpm_clocks_status[1];
|
461 |
|
|
`endif
|
462 |
|
|
|
463 |
|
|
end
|
464 |
|
|
endfunction
|
465 |
|
|
|
466 |
|
|
|